16-bit Serial-In/Parallel-Out Constant-Current LED Driver Product Description

Transcription

1 StarChips Technology V01_01; May/15 16-bit Serial-In/Parallel-ut Constant-Current LED Driver Product Description The serial-interfaced LED driver sinks 16 LED clusters with constant current to keep the uniform intensity of LED displays. In applications, an external resistor is used to set the full-scale constant output current from 1mA up to 45mA. The guarantees each output can endure maximum 17V DC voltage stress. The built-in shift registers and data latches making the effective solution in driving LED display. The output enable function gates all 16 outputs on and off, and is fast enough to be used as PWM input for LED intensity control. Since the serial data input rate can be reached up to 25MHz, the will satisfy system which needs high volume data transmission to control the LED display. Furthermore, the provides excellent temperature regulation thus it can be applied to varied of operating temperature. The built-in output pre-charge function which improves the picture quality of LED display. Features Built-in output pre-charge function. Finest grayscale response with 40ns PWM pulse width 16 robust constant current sinker with LED power-supply voltage up to 17V Constant output current : 1 30/45mA@3.3/5V Wide power supply voltages: 3.3V to 5V Excellent regulation to load, supply voltage and temperature Load regulation: ±0.1%/V Line regulation: ±0.5%/V High current matching accuracy: ±1% between outputs, ±2% between ICs Dropout voltage 0.5V@20mA, =5V CMS Schmitt trigger inputs with clock rate up to cascade connection The constant current value of 16 outputs is set by a single external resistor Built-in power on reset(pr) circuit forces all the outputs off while power on ESD protection ability : HBM > 7KV, MM > 350V Package: SSP24, SSP24-1, SP24 and TQFN24 Applications: LED Displays, Variable Message Signs, Illumination, LED Traffic Signs Page 1 of 20

2 UT9 UT8 UT7 UT6 UT5 UT10 UT9 UT8 UT7 UT6 UT5 16-bit Serial-In/Parallel-ut Constant-Current LED Driver Pin Configurations 1 SDI 2 CLK 3 LA/ 4 UT0 5 UT1 6 UT2 7 UT3 8 UT4 9 UT5 10 UT6 11 UT7 12 CSSG CSTG CSG A REXT 22 SD 21 E/ 20 UT15 19 UT14 18 UT13 17 UT12 16 UT11 15 UT10 14 UT9 13 UT8 LA/ 1 UT0 2 UT1 3 UT2 4 UT3 5 UT4 6 SDI 23 CLK CQNG TP() B REXT 20 SD E/ 17 UT15 16 UT14 15 UT13 14 UT12 13 UT11 LA/ 1 UT0 2 UT1 3 UT2 4 UT3 5 UT4 6 SDI 23 CLK 24 REXT AQNG TP() C SD 19 E/ UT15 17 UT14 16 UT13 15 UT12 14 UT11 13 UT10 Terminal Description Pin Name 1 Pin No. A B C 22 (TP) 10 (TP) I/ Function - Ground terminal(thermal pad included) SDI I Serial input of data shift register. CLK I LA/ I UT[0:15] E/ I SD REXT I/ Clock input of shift register, data is sampled at the rising edge of CLK. Input terminal of data strobe. Data is latched when LA/ is low. And data on shift register goes through when LA/ is high. pen-drain, constant-current outputs Supply voltage terminal utput enable signal. utput is enabled when E/ is forced to low. utput terminal of serial-data output to the SDI of next. Used to connect an external resistor for setting up all output current Page 2 of 20

3 Block Diagram UT0 UT1 UT2 UT14 UT15 REXT PR Current Regulator utput Driver E/ ST D ST D ST D ST D ST D LA/ SDI D D D D D SD C C C C C CLK Equivalent Circuits of Inputs (1) Equivalent Circuits of Inputs (2) E/ LA/ Equivalent Circuits of Inputs (3) Equivalent Circuits of utput CKI SDI SD Page 3 of 20

4 rdering Information Part Marking Package Unit per reel(pcs) CSSG CSSG Green SSP CSTG CSTG Green SSP CSG CSG Green SP CQNG 5020CQNG Green TQFN AQNG 5020AQNG Green TQFN StarChips Technology, Inc. 5F, No.5, Technology Rd., Science-Based Industrial Park, Hsin-Chu, Taiwan, R..C. Tel : Ext.555, Fax: , service@starchips.com.tw Truth Table CLK LA/ E/ SDI UT0 ~ UT15 SD Timing Diagram H L Dn Dn Dn Dn-14 Dn-15 Dn-15 L L Dn+1 No change Dn-14 H L Dn+2 Dn+2 Dn Dn-12 Dn-13 Dn-13 X L Dn+3 Dn+2 Dn Dn-12 Dn-13 Dn-13 X H Dn+3 ff Dn CLK SDI D15(MSB)=0 D14=1 D13=1 D12-3=0 D2=1 D1=0 D0(LSB)=1 LA/ E/ UT0 (LSB) UT1 UT2 UT3- UT12 UT13 UT14 UT15 (MSB) SD Previous data D15(MSB)=0 FF N FF N FF N FF N FF N FF N FF N Page 4 of 20

5 Maximum Ratings (TA = 25 C) Characteristic Symbol Rating Unit Supply voltage 7.0 V Input voltage VIN -0.2 to +0.2 V utput current IUT 60 ma/channel utput voltage SD VUT -0.2 to +0.2 V UT0~UT to 17 V Total terminals current I 960 ma Power dissipation Thermal resistance SP24 PD 1.92 SSP SSP TQFN SP24 RTH(j-a) 65 SSP24 88 SSP TQFN24 60 perating junction temperature TJ(max) 150 C perating temperature TPR -40 to +85 C Storage temperature TSTG -55 to +150 C W C /W The absolute maximum ratings are a set of ratings not to be exceeded. Stresses beyond those listed under Maximum Ratings may cause the device breakdown, deterioration even permanent damage. Exposure to the maximum rating conditions for extended periods may affect device reliability. Recommended perating Conditions (TA= -40 to 85 C unless otherwise noted) Characteristic Symbol Conditions Min. Typ. Max. Unit Supply voltage V utput voltage VUT utput FF V utput N V utput current IUT =3.3/5V 2-30/45 ma VIH Input signals V Input voltage VIL Input signals V E/ pulse width tw(e) =3.3V/5V ns 1. The output current keep constant in range of 5-45mA if V UT=1V. However, user can minimize V UT to reduce power dissipation according to used current, e.g., set V UT to 0.6V if I UT=20mA. 2. The maximum Vout is package thermal limited, user should keep Vout under maximum power dissipation. Page 5 of 20

6 Electrical Characteristics (=3.3/5V, TA=25 C unless otherwise noted) Characteristic Symbol Conditions Min. Typ. Max. Unit Input voltage SD output voltage VIH V VIL V VH =3.3/5V, IH= -1mA V VL =3.3/5V, IL=+1mA V utput leakage current IL VUT=17V ua utput current IUT VUT=1V, REXT=900Ω ma Current bit skew 1 diut1 VUT=1V, REXT=900Ω - ±1 ±2 % Chip skew 2 diut2 VUT=1V, REXT=900Ω - ±2 ±3 % Line regulation 3 IUT vs. Load regulation 4 IUT vs. VUT %/d %/dvut 3V<<5.5V, VUT>1V, REXT=900Ω 1V<VUT<4V, IUT=20.5mA, REXT=900Ω - ±0.5 ±1 %/V - ±0.1 ±0.5 %/V Pull-up resistor RUP E/ KΩ Pull-down resistor RDWN LA/ KΩ Supply current FF N IDD(FF)1 IDD(FF)2 IDD(N) 1. Bit skew=(i UT-I AVG) / I AVG, where I AVG=(I UT(max)+ I UT(min))/2 =3.3/5V, REXT=pen, UT[0:15]=FF(to VCC) =3.3/5V, REXT=900Ω, UT[0:15]=FF(to VCC) =3.3/5V, REXT=900 Ω, UT[0:15]=N Chip skew=(i AVG-I CEN) / I CEN*100(%), where I CEN is the statistics distribution center of output currents. 3. Line regulation=[i UT(V DD=5.5V)-I UT(V DD=3V)] / {[I UT(V DD=5.5V)+I UT(V DD=3V)]/2} / (5.5V-3V)*100(%/V) 4. Load regulation=[i UT(V UT=4V)-I UT(V UT=1V)] / {[I UT(V UT=4V)+I UT(V UT=1V)]/2} / (4V-1V)*100(%/V) ma Test Circuit for Electrical Characteristics C1=1uF SDI CLK LA/ E/ IDD UT0 UT1 IUT VLED REXT ±1mA REXT SD UT15 VUT CLED=10uF Page 6 of 20

7 Switching Characteristics (TA=25 C unless otherwise noted) Propagation delay time ( L to H ) Propagation delay time ( H to L ) Characteristic Symbol Conditions Min. Typ. Max. Unit CLK - UTn tplh1 LA/ - UTn tphl ns E/ - UT0 tphl3 = 3.3/5V ns VLED CLK - SD = 5V tphl ns VIH = VIL= ns LA/ - UTn tplh ns E/ - UT0 tplh ns CLK - SD tplh ns CLK - UTn tphl ns CLK tw(clk) ns Pulse width LA/ tw(l) REXT = 900Ω ns E/ RL = 180Ω tw(e) ns CL = 10pF Setup time for SDI ts(d) C1 = 1uF ns Hold time for SDI thd) CLED = 10uF 15 ns Setup time for LA/ ts(l) ns Hold time for LA/ th(l) ns SD rise time tsdr ns SD fall time tsdf ns utput rise time of IUT tr ns utput fall time of IUT tf ns Slow CLK rise time 1 tr ns Cascade Slow CLK fall time tf ns Test Circuit for Switching Characteristics VIL C1 * VIH tr = tf = 10 ns SDI CLK LA/ E/ IDD UT0 UT1 VLED IUT CLED * CL REXT CL REXT SD UT15 VUT RL Page 7 of 20

8 Timing Waveform LA/ Control utput t W(CLK) t R t F CLK 50% 50% 10% 90% 90% 50% 50% 10% t S(D) t H(D) SDI 50% 50% t PLH/PHL SD 50% 10% 90% t SDR/SDL t H(L) t S(L) LA/ 50% 50% t W(L) E/ LW = ALL UTPUTS ENABLED t PHL2/PLH2 HIGH = UTPUT FF UTn 50% t PHL1/PLH1 LW = UTPUT N E/ Control utput E/ t W(E) t PHL3 t PLH3 UTn 90% 50% 50% 10% 10% 90% t F t R Page 8 of 20

9 Adjusting utput Current The s output current (IUT) are set by one external resistor at pin REXT. The output current IUT versus resistance of REXT is shown as the following figure. 70 I UT vs. R A =25 C V<V UT <4V IUT(mA) R EXT (KΩ) According to I-V curve of the output of, the output voltage should be larger than 1V to get 45 ma constant current. By applying proper output voltage, the output current set by an external resistor is approximate to: IUT = 30(615 / REXT) (ma) (chip skew < ±3%). Thus the output current is set to be about 20.5mA at REXT = 900Ω. utput Characteristics The current characteristic of output curve is flat. The output current can be kept constant regardless of the variations of LED forward voltage when VUT > VD (Drop-ut voltage). The relationship between IUT and VUT is shown below. The output voltage should be kept as low as possible to prevent the from being overheated. 70 I UT vs. V A =25 C IUT(mA) Drop-out voltage is current dependent, e. g., V =0. 5V@ I =20mA V UT (V) Page 9 of 20

10 45 I UT vs. V A =25 C IUT(mA) V UT (V) Power Dissipation The maximum power dissipation (PD(max)) of a semiconductor chip varies with different packages and ambient temperature. It s determined as PD(max)=(TJ(max) TA)/RTH(j-a) where TJ(max): maximum chip junction temperature is usually considered as 150 C, TA: ambient temperature, RTH(j-a): thermal resistance. Since P=IV, for sinking larger IUT, users had better add proper voltage reducers on outputs to reduce the heat generated from the. SCT5050 P D(max) vs. T A P D(max) (W) TQFN24:R TH(j-a) =60 C/W 2.SP24:R TH(j-a) =65 C/W 3.SSP24-1:R TH(j-a) =72 C/W 4.SSP24:R TH(j-a) =88 C/W T A ( C) Page 10 of 20

11 Limitation on Maximum utput Current The maximum output current vs. duty cycle is estimated by: IUT(max)=(((TJ(max)-TA)/RTH(j-a))-(*IDD))/VUT/Duty/N where TJ(max)=150 C, N=16(all N) 50 I UT(max) vs. C/W 45 V UT =4V V UT =3V I UT(max) (ma) V UT =4V V UT =3V V UT =2V T A =85 C T A =25 C Duty(%) 50 I UT(max) vs. C/W 45 V UT =4V V UT =3V 40 I UT(max) (ma) V UT =4V V UT =3V V UT =2V T A =85 C T A =25 C Duty(%) Page 11 of 20

12 50 I UT(max) vs. C/W V UT =4V V UT =3V IUT(max)(mA) V UT =4V V UT =3V V UT =2V T A =85 C T A =25 C Duty(% ) 50 I UT(max) vs. C/W V UT =4V V UT =3V V UT =2V IUT(max)(mA) V UT =4V V UT =3V V UT =2V T A =85 C T A =25 C Duty(% ) Load Supply Voltage (VLED) The can be operated very well when VUT ranges from 1V to 4V. However, it is recommended to use the lowest possible supply voltage or set a voltage reducer to reduce the VUT voltage, at the same time reduce the power dissipation of the. Suggested VUT is to be set greater than VD and less than 1V. The VD is dependent on the IUT current as indicated in section utput Characteristics. Follow the diagram instructions shown below to lower down the output voltage. This can be done by adding additional resistor or zener diode, thus VUT=VLED-VDRP-VF. Page 12 of 20

13 VLED VLED VDRP VDRP IUT VF IUT VF VUT VUT Typical Application Circuits Dynamic Lighting SCAN VLED PWER MSFET ARRAY which is not needed in Static driving. C.U UT0 SDI E/ LA/ CLK UT1 UT14 UT15 UT0 UT1 UT14 UT15 SD SDI E/ SD LA/ REXT CLK REXT Page 13 of 20

14 PCB Design Considerations Use the following general guide-line when designing printed circuit boards (PCB): Decoupling Capacitor Place a decoupling capacitor e.g. 1uF between and pins of. Locate the capacitor as close to the as possible. This is normally adequate for static LED driving. For dynamic scan or PWM applications, it is suggested to add an additional capacitor of 0.1uF or more to each supply for every. The necessary capacitance depends on the LED load current, PWM switching frequency, and serial-in data speed. Inadequate decoupling can cause timing problems, and very noisy LED supplies can affect LED current regulation. VLED LPF 10Ω Clock 10Ω CLK CLED 10pF 0.1uF REXT REXT External Resistor (REXT) Locate the external resistor as close to the REXT pin as possible to avoid the noise influence. Power and Ground Maximizing the width and minimizing the length of and trace improves efficiency and ground bouncing by effect of reducing both power and ground parasitic resistance and inductance. A small value of resistor, e.g., 10Ω (higher if IUT is larger) series in power input of the in conjunction with decoupling capacitor shunting the IC is recommended. Separating and feeding the LED power from another stable supply terminal VLED. Furthermore, adding a capacitor CLED greater than 10uF at VLED is recommended. EMI Reduction To reduce the EMI radiation from system, an economical solution of RC low pass filter (LPF) is suggested to be used to lower the transient edge of clock input signal, as shown in the figure above. Using at least four layers PCB board with two interior power and ground planes is a good scheme to decrease the signal current path which is the source of radiation emission. As a result, EMI radiation can be decreased. Page 14 of 20

15 Thermal Pad Consideration The thermal pad (also named as exposed pad ) TQFN package beneath used to increase the heat dissipation capability is grounded. User should be aware of this electrical connection when designing the PCB board, and make provisions for its use. In most of application, the thermal pad is electrically connected to ground plane or conduction. This makes the IC operated with more stable condition. In general, the heat generated from an IC is conducted to the PCB then radiates to the ambient. Thermal pad specifically increases the maximum power dissipation capability of the IC packages. To provide lower thermal resistance from the IC to the ambient air, PCB designers should layout larger thermal conduction areas on top layer (component side) and bottom layer (solder side) as well as thermal vias, the more the better. In addition, connecting thermal via to the ground plane also increases thermal conduction areas, this improves the heat transfer efficiency at the same time greatly dissipates heat generated from the package. Furthermore, coating solder on bottom layer and selecting, e.g., 2 oz. copper which will increase the total thickness of thermal conduction is an alternative. When making the solder paste screen, an opening should be created for the thermal pad. This way the thermal pad can be electrically and thermally connected to the PCB. As the thermal pad is soldered on copper polygon, the chance of inadvertently shorting the thermal pad to traces routed underneath it could be eliminated. Thermal conduction Thermal pad Thermal Polygon vias Multi-layers PCB Page 15 of 20

16 Package Dimension SSP24(check up-to-date version) Symbol Dimension (mm) Dimension (mil) Min. Nom. Max. Min. Nom. Max. A A A b c D E E e 0.64 BSC 25.0 BSC L y ZD 0.84 REF 33.0 REF θ Page 16 of 20

17 SSP24-1 (check up-to-date version) Symbol Dimension (mm) Dimension (mil) Min. Nom. Max. Min. Nom. Max. A A A b c D E E e 1.00 BSC 39.4 BSC L y θ Page 17 of 20

18 SP24 (check up-to-date version) Symbol Dimension (mm) Dimension (mil) Min. Nom. Max. Min. Nom. Max. A A b c D E E e 1.27 BSC 50.0 BSC L θ y Page 18 of 20

19 TQFN24-4x4(CQNG) (check up-to-date version) Symbol Dimension (mm) Dimension (mil) Min. Nom. Max. Min. Nom. Max. A A A A REF 8.0 REF b D D E E e 0.50 BSC 19.7 BSC L y Page 19 of 20

20 TQFN24-4x4(AQNG) (check up-to-date version) Symbol Dimension (mm) Dimension (mil) Min. Nom. Max. Min. Nom. Max. A A A A REF 8.0 REF b D 4.00 BSC BSC D E 4.00 BSC BSC E e 0.50 BSC 19.7 BSC L y Revision History(check up-to-date version) Data Sheet Version V01_01 Remark First released Information provided by StarChips Technology is believed to be accurate and reliable. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Starchips can not assume responsibility and any problem raising out of the use of the circuits. Starchips reserves the right to change product specification without prior notice. StarChips Technology Inc. 5F, No.5, Technology Rd.,Science-Based Industrial Park, Hsin-Chu,Taiwan, R..C. Tel: # 555 Page 20 of 20