1.5MHz, 1.5A Synchronous Step-Down Regulator

Transcription

1 1.5MHz, 1.5A Synchronous Step-Down Regulator General Description The is a high efficiency current mode synchronous buck PWM DC-DC regulator. The internal generated 0.6V precision feedback reference voltage is designed for low output voltage. Low R DS(N) synchronous switch dramatically reduces conduction loss. To extend battery life for portable application, 100% duty cycle is supported for low-dropout operation. Shutdown mode also helps saving the current consumption. The is packaged in MSP-10L, DFN-10L and SP-8L to reduce PCB space. Features Input Voltage Range: 2.5 to 5.5V Adjustable utput Voltage From 0.6V to V IN Precision Feedback Reference Voltage: 0.6V (±2%) utput Current: 1.5A (Max.) Duty Cycle: 0~100% Internal Fixed PWM Frequency: 1.5MHz Low Quiescent Current: 100μA No Schottky Diode Required Built-in Soft Start Current Mode peration ver Temperature Protection Package: MSP-10L (EP), DFN-10L (EP), SP-8L (EP) Applications Cellular Telephone Wireless and DSL Modems Digital Still Cameras Portable Products MP3 Players Typical Application Circuit 1 EN 8 V IN 2 7 VCC 3 6 AVCC SW 4 A 5 FB / VUT V UT SP-8L 1/19

2 Function Block Diagram EN AVCC VCC Enable / UVL SC SC 0.6V V REF Slope Comp FB / VUT + Error Amp Current Comp. + S Q R Q SR Latch Switching Control Logic Anti Shoot- Thru SW Current Sensing Reverse Current Detector + - PGD A 2/19

3 Pin Descriptions MSP-10L (EP) EN VCC AVCC PGD FB / VUT Top View 6162AD 9Fa86L Bottom View EP SW SW A Name No. I / Description EN 1 I Enable / UVL V CC 2 P Supply Voltage AV CC 3 P Analog Supply Voltage PGD 4 Power Good pen Drain utput FB / V UT 5 I Feedback A 6 P Analog Ground SW 7 Switch SW 8 Switch 9 P Ground 10 P Ground EP 11 P Exposed PAD - must connect to Ground DFN-10L (EP) EN VCC AVCC PGD FB / VUT Top View 6162AD 9Fa86L Bottom View EP SW SW A Name No. I / Description EN 1 I Enable / UVL V CC 2 P Supply Voltage AV CC 3 P Analog Supply Voltage PGD 4 Power Good pen Drain utput FB / V UT 5 I Feedback A 6 P Analog Ground SW 7 Switch SW 8 Switch 9 P Ground 10 P Ground EP 11 P Exposed PAD - must connect to Ground SP-8L (EP) EN 1 Top View 8 Name No. I / Description EN 1 I Enable / UVL V CC AV CC FB / V UT AD 9Fa-86L SW A V CC 2 P Supply Voltage AV CC 3 P Analog Supply Voltage FB / V UT 4 I Feedback A 5 P Analog Ground Bottom View SW 6 Switch 7 P Ground 8 P Ground EP EP 9 P Exposed PAD - must connect to Ground 3/19

4 Marking Information MSP-10L (EP) 6162AD Reference Voltage Code Ext: AD 0.6V Halogen Free Lot Number Internal ID Per-Half Month Year DFN-10L (EP) 6162AD Reference Voltage Code Ext: AD 0.6V Halogen Free Lot Number Internal ID Per-Half Month Year SP-8L (EP) 6162-AD 9Fa-86L Reference Voltage Code Ext: AD 0.6V Halogen Free Lot Number Internal ID Per-Half Month Year Halogen Free: Halogen free product indicator Lot Number: Wafer lot number s last two digits For Example: TB 86 Internal ID: Internal Identification Code Per-Half Month: Production period indicated in half month time unit For Example: January A (Front Half Month), B (Last Half Month) February C (Front Half Month), D (Last Half Month) Year: Production year s last digit 4/19

5 rdering Information Part Number perating Temperature Package MQ Description ADgR-G1-40 C ~ +85 C MSP-10L (EP) 3000EA Tape & Reel ADdR-G1-40 C ~ +85 C DFN-10L (EP) 2500EA Tape & Reel ADXR-G1-40 C ~ +85 C SP-8L (EP) 2500EA Tape & Reel Absolute Maximum Ratings Parameter Symbol Conditions Min. Typ. Max. Unit Input Supply Voltage V IN V EN, V FB, SW Pin Voltage -0.3 V IN V P-Channel Switch Source Current (DC) 2 A N-Channel Switch Source Current (DC) 2 A Peak SW Switch Sink and Source Current (AC) 3 A MSP-10L +70 C / W Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) θ JA θ JC DFN-10L +65 C / W SP-8L +50 C / W MSP-10L +10 C / W DFN-10L +10 C / W SP-8L +10 C / W perating Temperature C Junction Temperature +150 C Storage Temperature C Lead Temperature (soldering, 10 sec) +260 C IR Re-flow Soldering Curve 5/19

6 Recommended perating Conditions Parameter Symbol Conditions Min. Typ. Max. Unit Supply Voltage V IN V perating Temperature C DC Electrical Characteristics (T A = 25 C, V IN =3.6V, unless otherwise noted) Parameter Symbol Conditions Min. Typ. Max. Unit Regulated Feedback Voltage V FB T A=25 C V -40 C ~+85 C V Line Regulation with V REF V FB V IN=2.5V to 5.5V / V utput Voltage LineRegulation V UT V IN=2.5 to 5.5V % / V RDS (N) of P-Channel FET R DS (N) P I SW=100mA Ω RDS (N) of N-Channel FET R DS (N) N I SW =-100mA Ω SW Leakage I LSW V EN=0V, V IN=5V ±0.01 ±1 µa Peak Inductor Current I PK V FB=0.5V A Input Voltage Range V IN V Quiescent Current I CC Shutdown, V EN=0V µa Active, V FB=0.5V, V EN=V IN 100 µa PFM, V FB=0.7V, V EN=V IN 80 µa EN Threshold V EN V EN Leakage Current I EN ±0.01 ±1 µa scillator Frequency F SC V FB=0.6V, -40 C ~+85 C MHz 6/19

7 Frequency (MHz) SWITCH LEAKAGE(nA) Reference Voltage (V) Frequency (MHz) Supply Current (ua) Reference Voltage (V) Supply Current (ua) Supply Current (ua) Typical perating Characteristics (T A = 25 C, V IN =3.6V, unless otherwise noted) Supply Current vs. V IN Supply Current vs. V IN 140 V FB =0.5V V IN (V) 80 V FB=0.65V V IN (V) Supply Current vs. V IN 0.5 Shutdown V IN (V) Line Regulation 0.61 T A= V IN (V) Reference Voltage vs. Temperature Frequency vs. V IN V IN=3.6V Temperature ( ) 1.55 T A = V IN (V) Frequency vs. Temerature SWITCH LEAKAGE vs. INPUT VLTAGE 1.52 V IN =3.6V Temperature( ) 1.2 T A = SYNCHRNU 0.4 MAIN SWITCH V IN (V) 7/19

8 Function Description Control Loop The is a high efficiency current mode synchronous buck regulator. Both the main (P-channel MSFET) and synchronous (N-channel MSFET) switches are built internally. With current mode operation, the PWM duty is controlled both by the error amplifier output and the peak inductor current. At the beginning of each cycle, the oscillator turn on the P-MSFET switch to source current from V IN to SW output. Then, the chip starts to compare the inductor current with the error amplifier output. nce the inductor current is larger than the error amplifier output, the P-MSFET switch is turned off. When the load current increases, the feedback voltage FB will slightly drop. This causes the error amplifier to output a higher current level until the prior mentioned peak inductor current reach the same level. The output voltage then can be sustained at the same. When the top P-MSFET switch is off, the bottom synchronous N-MSFET switch is turned on. nce the inductor current reverses, both top and bottom MSFET will be turn off to leave the SW pin into high impedance state. The s current mode control loop also contains slope compensation to suppress sub-harmonic oscillations at high duty cycles. This slope compensation is achieved by adding a compensation ramp to the inductor current signal. LD Mode The s maximum duty cycle can reach 100%. That means the driver main switch is turn on through out whole clock cycle. nce the duty reaches 100%, the feedback path no longer controls the output voltage. The output voltage will be the input voltage minus the main switch voltage drop. ver Current Protection limits the peak main switch current cycle by cycle. When over current happens, chip will turn off the main switch and turn the synchronous switch on until next cycle. Short Circuit Protection When the FB pin drops below 300mV, the chip will tri-state the output pin SW automatically. After 300us rest to avoid over heating, chip will re-initiate PWM operation with soft start. Power Good The power good pin is an open-drain output. Connects a 100kΩ pull up resistor between V IN and 8/19

9 this pin to obtain a PGD voltage. When the output voltage is not within ±10% of setting output voltage, the PGD pin will be pulled down to ground immediately. After the output voltage is within ± 10% of setting output voltage for 175ms (typ.), the PGD pin pull-down is turned off. Then it can be pulled up to V IN through external pull-high resister. Connect this pin to A if not used. Thermal Protection will shutdown automatically when the internal junction temperature reaches 150 to protect both the part and the system. 9/19

10 Application Information Input capacitor Selection The input capacitor must be connected to the V IN pin and pin of the to maintain steady input voltage and filter out the pulsing input current. The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. In switch mode, the input current is discontinuous in a buck converter. The source current of the high-side MSFET is a square wave. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The RMS value of input capacitor current can be calculated by: I RMS I _ MAX V V IN V 1 V IN It can be seen that when V is half of V IN, C IN is under the worst current stress. The worst current stress on C IN is I _MAX / 2. Inductor Selection The value of the inductor is selected based on the desired ripple current. Large inductance gives low inductor ripple current and small inductance result in high ripple current. However, the larger value inductor has a larger physical size, higher series resistance, and/or lower saturation current. In experience, the value is to allow the peak-to-peak ripple current in the inductor to be 10%~20% maximum load current. The inductance value can be calculated by: (VIN V L f I L ) V V IN f (V IN V V 2 (10% ~ 20%)I VIN ) The inductor ripple current can be calculated by: I L V V 1 f L V IN Choose an inductor that does not saturate under the worst-case load conditions, which is the load current plus half the peak-to-peak inductor ripple current, even at the highest operating temperature. The peak inductor current is: I L _ PEAK I I 2 L 10/19

11 The inductors in different shape and style are available from manufacturers. Shielded inductors are small and radiate less EMI issue. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. Inductor Value (µh) Dimensions (mm) Component Supplier Model FENG-JUI TPRH8D43-2R2M FENG-JUI TPRH10D40-2R2M FENG-JUI TPRH8D43-3R3M FENG-JUI TPRH10D40-3R3M FENG-JUI TPRH8D43-4R7M FENG-JUI TPRH10D40-4R7M utput Capacitor Selection The output capacitor is required to maintain the DC output voltage. Low ESR capacitors are preferred to keep the output voltage ripple low. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. The output ripple is determined by: V I L ESR CUT 1 8 f C UT Where f = operating frequency, CUT= output capacitance and ΔIL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Capacitor Value Case Size Component Supplier Model 10μF 0805 Taiyo Yuden JMK212BJ106MG 10μF 0805 TDK C12012X5RJ106K 22μF TDK C2012JB0J226M Using Ceramic Input and utput Capacitors Care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. 11/19

12 utput Voltage Programming In the adjustable version, the output voltage is set using a resistive voltage divider from the output voltage to FB. The output voltage is: V R 0.6V 1 R 1 2 The recommended resistor value is summarized below: V UT (V) R 1 (Ω) R 2 (Ω) C 3 (F) k Not Used Not Used k 200k 10p k 200k 10p k 100k 10p k 85k 10p k 68k 10p PC Board Layout Checklist 1. The power traces, consisting of the trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Place CIN near V IN Pin as closely as possible. To maintain input voltage steady and filter out the pulsing input current. 3. The resistive divider R1and R2 must be connected to FB pin directly as closely as possible. 4. FB is a sensitive node. Please keep it away from switching node, SW. A good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and the layer on which the feedback trace is routed. This reduces EMI radiation on to the DC-DC converter s own voltage feedback trace. 5. Keep the plates of C IN and C UT as close as possible. Then connect this to the ground-plane (if one is used) with several vias. This reduces ground plane noise by preventing the switching currents from circulating through the ground plane. It also reduces ground bounce at the by giving it a low impedance ground connection. 12/19

13 C1 V IN 1 10 C2 2 9 V UT VIA T V UT R C3 5 6 R1 R2 Suggested Layout for DFN-10L / MSP-10L C1 V IN 1 8 C2 2 7 V UT VIA T V UT 3 6 C3 4 5 R1 R2 Suggested Layout for SP-8L 13/19

14 Typical Application 1 EN 10 V IN 2.5V / 5.5V C1 22μF R3 100K V CC AV CC SW 7 PGD SW 6 FB / VUT A 9 8 L1 3.3μH R1 200K C3 10pF C2 22μF V UT 1.8V / 1.5A R2 100K DFN-10L / MSP-10L 1 EN 8 V IN 2.5V / 5.5V 2 3 V CC AV CC 7 6 SW L1 3.3µH V UT 2.5V /1.5A C1 22µF 4 5 FB / VUT A R1 270K C3 10pF C2 22µF R2 85K SP-8L 14/19

15 Efficiency (%) Efficiency I LAD : 100mA~1.5A I LAD : 500mA~1.5A Ch1:V UT Ch4: I SW Ch1:V UT Ch4: I SW EN n waveform (V UT : 1.8V) Efficiency (V UT : 1.8V) Efficiency VS utp utput Curren Vin=2. Vin=3. Vin=4. Ch1:EN Ch2: SW Ch3:V UT Ch4:I SW PGD waveform (V UT : 1.8V) Efficiency (V IN : 5.3V) Efficiency VS utput Current utput Current (ma) Vout=3.3V Vout=1.8V Vout=1.2V 15/19

16 Package utline MSP-10L (EP) UNIT: mm Symbols Min. (mm) Max. (mm) A A A b c D BSC. E BSC. E BSC. e BSC. L L REF. θ /19

17 MSP-10L (EP) continued Exposed PAD Dimensions: Symbols Min. (mm) Max. (mm) E REF D REF Note: 1. Package dimensions are in compliance with JEDEC outline: M-187 BA-T. 2. Dimension D does not include molding flash, protrusions or gate burrs. 3. Dimension E1 does not include inter-lead flash or protrusions. 17/19

18 DFN-10L (EP) UNIT: mm Symbols Min. (mm) Max. (mm) A A A3 0.20REF b D 3.00 E 3.00 D E e L K /19

19 SP-8L (EP) UNIT: mm Symbols Min. (mm) Max. (mm) A A A D E H L θ 0 8 Exposed PAD Dimensions: Symbols Min. (mm) Max. (mm) E REF D REF Note: 1. Package dimensions are in compliance with JEDEC outline: MS-012 AA. 2. Dimension D does not include molding flash, protrusions or gate burrs. 3. Dimension E does not include inter-lead flash or protrusions 19/19