Broadband Drivers with Wave Shape Control for Optical Fiber and Backplane Applications. Recommended reading: 1) Chapters 7 and 8, Sackinger
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1 Broadband Drivers with Wave Shape Control for Optical Fiber and Backplane Applications Recommended reading: 1) Chapters 7 and 8, Sackinger 1
2 Outline Types of drivers Driver specification Driver building blocks and architecture Driver implementation and design examples 2
3 Types of drivers: backplane, cable IM + RL - + LASER VMOD EAM D D CK CK IM + - VMOD VMOD D D CK + - VMOD - RL MZM CK I/O (RL=50 Ω) backplane driver Coaxial cable (HDTV) (RL=75 Ω) Laser driver EAM (Electro-Absorption Modulator) driver MZM (Mach-Zehnder Modulator) driver 3
4 Types of drivers: DFB/FB Laser, VCSEL VDD = 1.2 V VFB R R L L 20µm/80nm Q3 32µm/80nm Q1 Q2 32µm/80nm Q4 48µm/80nm IT C. Kromer et al ISSCC 2005 Laser driver (RL=5..25 Ω, CL= pf) 4
5 EAML = EA Modulator + Laser [2] 5
6 Types of drivers: EAM EAM driver (RL=50 Ω, CL= pf) 6
7 2Vpp, 40-Gb/s mod. driver in 45-nm SOI Based on PA super-cascode concept (J. Buckwalter, UCSD, CICC-2010) 7
8 Types of drivers: Mach Zehnder Modulator [2] 8
9 Example of Mach-Zehnder Driver INP OUTP Q4 INN Q3 OUTN Q1 Q2 RE IE F IE F VOA RE Q5 RB 9
10 Outline Types of drivers Driver specification Driver building blocks and architecture Driver implementation and design examples 10
11 Driver Specification Modulation and bias current range (lasers) Voltage swing and bias voltage (modulators) Rise and fall time Input/output matching Pulse width distortion Jitter generation Eye-diagram mask test 11
12 Modulation and bias current range Directly modulated lasers Pout Temp IL IB DFB, VCSEL IB = (20) ma IM O D = (15) ma Threshold and slope are temperature dependent IMOD DC or AC coupled 12
13 Voltage swing and bias voltage range Externally modulated laser with EAM V = V B VMOD = V VB (DC offset) must be adjustable from driver DC-coupled 13
14 Voltage swing and bias voltage range Externally modulated laser with MZM V = V B Pou t VMOD = V VM VB MZM VB must be accurately set for V /2 VMOD AC or DC coupled 14
15 Rise and fall time B (or Rb) =bit rate T= period tr and tf defined at 20% to 80% less used: 10% to 90% T = 1/B tr tf 15
16 Input and output match: S1 1, S2 2 < -15 db for f < B/2 < -10 db for f < B < -5 db for B<f<2B 16
17 Pulse width distortion (PWD or DCD) T = 1/B tpwd T remains unchanged Eye crossing <> 50% Eye crossing tf Pulse width distorted 17
18 Jitter generation Deterministic jitter double-edging Peak-to-peak spec tjrpp tjfpp Random jitter rms spec. tjpp = 14 x tjrms 18
19 Eye mask test ISI vnrms VDTH vspp eye height T = 1/B tr tf random jitter tjrpp decision point Q = 1/(2Btjrms) Noise tjfpp Q = vsp p/(2vnr m s) 19
20 Outline Types of drivers Driver specification Driver building blocks and architecture Driver implementation and design examples 20
21 Driver architecture: traditional Pre-driver Output buffer Input buffer Pre-driver Optional DFF re-timer Output buffer 21
22 Driver architecture: DAC Latest trend, especially in long-haul fiberoptics Output swing limited to 400mVpp per side (to date) InP HBT, SiGe HBT and 65-nm CMOS 22
23 Driver building blocks Input buffer Pulse-width (duty cycle) control circuit Output buffer with amplitude control (all) with pre-emphasis control (VCSEL/DFB, equalizer) with DC offset control (EAM) 23
24 Output buffer: 10 Gb/s 1.8V 0.18 m CMOS Inductive peaking in penultimate stage» use 3-term ind. L = CR2/3.1(2.4) for best group delay (flat gain response) M.M. Green et al. ISSCC
25 0.13 m CMOS design example V= 0.6 Vpp per side IMOD= 24 ma IMOD/ (JpfT) =W (Q1,2) W= 24mA/(0.3mA/ m) = 80 m W f = 4 m, Nf = 20 Veff = 0.3V; gm = 64 ms 25
26 0.13 m CMOS design example (ii) τ = RG(Cgs + 3Cgd) + 25 (Cdb + Cgd+ CPAD) τ = 10(100 ff ff) + 25 (140 ff + 40 ff + 50 ff) = 2.2 ps ps => BW 3 d B = 20 GHz In reality input node time constant limited by previous stage R o To improve speed: add inductive peaking, use distributed topology or else reduce swing 26
27 Output amplitude control applied at 40 Gb/s in GaAs p-hemt driver Low amplitude Maximum amplitude Output swing of 1.7 V Output swing of 3 V D. McPherson et al. GaAs IC Symposium
28 Output amplitude control in 45-Gb/s SiGe BiCMOS driver Input (top) Output (bottom): 270 mvp p- per side Output: 611 mvp p- per side T. Dickson (JSSC, Aug. 2006) 28
29 Pre-emphasis control concept τ C R v emph t = pp vo v opp Frequency domain t t 29
30 Output buffer with analog pre-emphasis main path with amplitude control Parallel path with differentiator and current summer 30
31 Pre-emphasis in Gb/s backplane driver No peaking 25% peaking Courtesy of Quake Technologies,
32 Pulse-Width Control Concept Pre- and post hard limiter required High speed data signal DIN + DC control DCAP 32
33 PW control in 25-Gb/s 0.13 m CMOS driver 50% 40% 60% P. Westergaard et al. CICC
34 PW control at 40 Gb/s in GaAs p-hemt driver 30% DCD 66% DCD D. McPherson et al. GaAs IC Symposium
35 Output buffer with digital pre-emphasis main path with amplitude control two parallel paths with differentiator for leading and falling edge, respectively 35
36 Pre-emphasis control with 800 mvpp per side in 10-Gb/s SiGe BiCMOS VCSEL driver No peaking 25% peaking S. P. Voinigescu et al. CICC
37 Output DC offset control implementation Output offset control 37
38 Output DC offset control applied at 40 Gb/s Minimum offset Maximum offset "1" level at -0.2 V "1" level of 1.2 V D. McPherson et al. GaAs IC Symposium
39 Distributed output stage 1 BW 3dB= R L C T Lumped output: L/2 L C C Distributed output: C T =n C L C C L ZO= C L L L/2 C 1 BW 3dB= L C 39
40 40-Gb/s EA driver schematic 40
41 Gain block architecture D. McPherson et. al. GaAs IC Symposium
42 40-Gb/s EA modulator driver layout D. McPherson et. al. GaAs IC Symposium
43 On-Wafer S22 Measurements: 18 parts 43
44 Nominal eye-diagrams 40 Gb/s 44 Gb/s Output swing of 3.0 Vp - p per side Rise/fall times are 10.9/11.4 ps Jitter is 8.6 ps (peak to peak) 44
45 Pre-driver 45
46 SiGe BiCMOS input buffer example 46
47 Optional retimer [2] 47
48 Receiver linear pre-emphasis concept for cable equalizers ZC IN OUT ZE ZC IN OUT ZE 48
49 Gilbert-cell based driver pre-emphasis Summing outputs from R VDD R a stage with constant gain vs. OUTP OUTN Cntr 0.65 freq 0.65 a stage with Zpeak peaking gain (with INP INN R 4 capacitive degeneration) H. Shakiba, Gennum, ISSCC Gb/s cable equalizer 49
50 Low-frequency path A. Balteanu, BCTM
51 High-frequency path A. Balteanu, BCTM
52 Compensates for cable loss vs. freq. A. Balteanu, BCTM
53 Examples of 40+Gb/s equalizers, drivers and DACs with waveshape control 53
54 A 1.8V SiGe BiCMOS Cable Equalizer with 40-dB Peaking Control up to 60 GHz Ioannis Sarkas and Sorin Voinigescu CSICS
55 Continuous Time Linear Equalizers 55
56 First Two Stages 56
57 Middle Stages Adjustable DC gain also Important for linearity Adjustable zero frequency 57
58 Output Driver & Predriver 58 58
59 Die Photo STMicroelectronics 130nm SiGe BiCMOS process with ft/ fmax =220/280 GHz 1 0.7mm PDC = 250mW 59 59
60 Equalizer S-parameters S-Parameters (db) S S S Bits grouped: 3 gain 2 peaking 1 gain-inductive peaking Frequency (GHz) 60
61 6.1m Cable 44-Gb/s Equalized Eye 27-1 length 61
62 6.1m Cable 44-Gb/s Equalized Eye length 62
63 6.1m Cable 44-Gb/s Bathtub length 63
64 Setup for Cable 80Gb/s 64
65 80-Gb/s PRBS Output 27-1 length 65
66 2.7m Output Eyes 27-1 length 66
67 3.9m Cable Equalized S-parameters 0 Cable + Equalizer Cable S21 (db) dB Frequency (GHz) 30dB 40GHz BW = 50GHz after equalization 67
68 3.9m Cable Equalized Eye 68
69 Distributed 49-Gb/s equalizer in 0.18 m SiGe BiCMOS Output Driver Input A. Hazneci CSICS-2004 Matching & Comparator Pulse Width Control Delay Buffers 69
70 SiGe BiCMOS distributed amplifier/equalizer layout 70
71 40-Gb/s Distributed Cable Driver with Preemphasis Control (R.Aroca, CSICS-2007) 75Ω 75Ω Microstrip T-Line Sections INP 8V 75Ω 75Ω OUT P 5V 1 INN 8V Pre-Driver 8V AM P DCC OUTN 8V Amp & PreEmphasis Itail CNTRL 75Ω IOUT = 5Vpp/(75Ω//75Ω) = 133mA 19mA/section Must fully switch the DA predriver: 1.5Vpp, 40mA Gain of predriver = 1.5/0.2 = 18dB, 3dB/stage 6 stages Amplitude control is implemented in both the DA and predriver 71
72 DA Section Schematic ~5 V T-line section T-line compensation HV-HBT IO F F C ~5 V ft=75ghz fmax=100gh z C IM A I N R R VP RE VP RE IP R E 0.18µm n-mosfets ft=50ghz, fmax=75ghz RC-HPF & Digital HBT ft=160ghz, fmax=160ghz 72
73 Driver Microphotograph 1.2mm Predriver Distributed Amplifier 2.5mm 73
74 S-parameter Measurements vs. Simulations: 10dB of Amplitude Control 22GHz 10d B 74
75 S-Parameter Measurements vs. Simulations: 25 db of Pre-Emphasis Control 25d B 75
76 2.4Vpp, 60-Gb/s DAC-Driver in 65-nm CMOS (R. Aroca, et al, CSICS-10) 50Ω microstrip T-lines VIPDA VOPDA 1:2 1:2 1:2 1:2 1:2 1:2 50Ω 50Ω TIALA RETIMER [2] VIP 50Ω 4-bit CNTL 5 1.2V 4-bit CNTL 1.2V 4-bit CNTL 50Ω 2:1 2:1 2:1 4-bit CNTL 2: bit CNTL 4 VDD1 = 1.2V 2:1 INP INN 3 2:1 8mA 2 VONDA VINDA CLK ITAIL 1 VDD2 = 2V 12mA 4-bit Gain CNTRL 16mA 24mA 12mA Ω Binary-weighted, segmented diff pair: (W/L)M1 = 20 * (1µm/65nm) (W/L)M2 = 21 * (1µm/65nm) Lp3 (W/L)M5 = 24 * (1µm/65nm) 1.2V 1.2V 1.2V 75Ω V Lp3 1.2V Ls3 Deep Nwell 2V 50Ω Lp2 Ls1 M5 M4 M3 M2 Ls2 M1 M5 M2 M3 M4 M5 OUTP OUTN 50Ω 75Ω Lp1 OUTP OUTN V 1.2V Lp4 M5 M1,2,3,4 60x1µm LVT Ls4 Lbb5 INP LVT 26x0.8µm LVT 38x0.8µm INP VTAIL 8mA Stage 1 VTAIL 12mA Stage 2 B4 B3 B2 B1 B4 B3 B2 B1 Lbb3 B1,2,3,4 B1,2,3,4 Lbb3 HVT 38x0.8µm LVT 50x0.8µm VTAIL 16mA Stage 4 SVT 76x0.8µm VTAIL 24mA Stage 5 76
77 DA-only S-param meas.: all peaking states 77
78 Full driver S-param measurements 78
79 40-Gb/s eyes with ampl. cntr. DR = 30 db 1.2Vpp mVpp
80 40-Gb/s eyes with peaking control: 8 db 0.55Vp p 0.85Vp p Vp p
81 60-Gb/s Eyes with 500mVpp and 800mVpp swing per side 81
82 56-Gb/s DAC in 65-nm p-mos CML (Ciena ISSCC 2011) 82
83 Back-up 83
84 Design example: 40 Gb/s, 2V SiGe HBT driver 2V over 25 Ω load results in 80 ma tail current. IMOD= 80 ma, AE= 80mA/9mA = 9 µm2, LE = 45 µm gm = 1.6 S, Rb=6.7 Ω Cπ = 1.05 pf, Ccs = 50 ff, Cµ= 99 ff Use emitter degeneration (RE=12.5 Ω) such that Av= -2 (previous stage needs 1V swing!) τ = Rb[Cπ/(1+gmRE)+ 3 Cµ] + 25 (Ccs + Cµ + CPAD) 84
85 Design example: 40-Gb/s, 2V SiGe HBT driver τ = 6.7x(1.05p / p) + 25x 0.199ps τ = 2.3ps + 5ps = 8.3ps Assuming emitter followers to reduce source impedance BW 3dB = 19 GHz (not adequate) Inductive peaking not possible: current is too large and SRF becomes too low Use distributed amp with 5 stages, each with 16 ma tail 85
86 Design example: 40-Gb/s, 2Vswing SiGe HBT driver Gain per stage is still 2 gm = 0.32 S, Rb=33.5 Ω Cπ = 201 ff, Ccs = 10 ff, Cµ= 20 ff The input/output lines can be loaded by a unit capacitance of 100 ff L = C Zo2 = 250 ph BW 3dB = 1/[π(LC)1/2] = 63 GHz... but will be limited by frequency at which transistor MAG = 6 db (A v= 2) 86
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