Merging parallel optics packaging and surface mount technologies

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1 Merging parallel optics packaging and surface mount technologies Christophe Kopp* a, Marion Volpert a, Julien Routin a Stéphane Bernabé b, Cyrille Rossat b, Myriam Tournaire b, Régis Hamelin b a CEA-LETI, Minatec, 17 rue des martyrs, Grenoble, FRANCE b INTEXYS PHOTONICS, 15 avenue d'hermès, L'Union, FRANCE ABSTRACT Optical links are well known to present significant advantages over electrical links for very high-speed data rate at 10Gpbs and above per channel. However, the transition towards optical interconnects solutions for short and very short reach applications requires the development of innovative packaging solutions that would deal with very high volume production capability and very low cost per unit. Moreover, the optoelectronic transceiver components must be able to move from the edge to anywhere on the printed circuit board, for instance close to integrated circuits with high speed IO. In this paper, we present an original packaging design to manufacture parallel optic transceivers that are surface mount devices. The package combines highly integrated Multi-Chip-Module on glass and usual IC ceramics packaging. The use of ceramic and the development of sealing technologies achieve hermetic requirements. Moreover, thanks to a chip scale package approach the final device exhibits a much minimized footprint. One of the main advantages of the package is its flexibility to be soldered or plugged anywhere on the printed circuit board as any other electronic device. As a demonstrator we present a 2 by 4 10Gbps transceiver operating at 850nm. Keywords: Datacom, Packaging, Optical interconnects, Parallel Optics, Transceiver 1. INTRODUCTION The development of optical networks technologies, namely DWDM (Dense Wavelength Division Multiplexing) and optical fiber amplifiers, has made possible the tremendous increase of data communication related to the wide spreading of Internet in the nineties. More recently, fiber interconnections have spread in LANs (Local Area Networks) and SANs (Storage Area Networks) using dedicated Ethernet and Fiber Channel protocols. In the past few years optical media have been used at the access networks with the deployment of FTTH networks, mainly in North America, Japan, Korea and Scandinavian countries. The direct result of such a communication increase is a rising need for bandwidth at the network s nodes, that is, at the Internet switches level which still uses copper technologies. Indeed, these switches now have to cope with data aggregated rate higher than 1 Terabit per second (1 Tbps) [1]. Moreover, the increase of the Internet traffic and bandwidth has led to the installation of multi-rack switches equipments. As a result, high data rate connections (>10 Gbps) have to be established between racks with lengths now exceeding the meters. This unavoidable increase of both connection lengths and data rate makes the legacy copper technology obsolete, and is now pushing the installation of optical fiber interconnections for Very Short Reach links at the switch level but also in large computer servers systems. This situation has stimulated the development of parallel optic devices in the past few years. In fact, modules following the already existing Multi Source Agreements, like POP-4 and SNAP-12 [2], have begun to be installed for such applications. These modules are designed to achieve parallel transmission of 2.5 Gbps signals on respectively 4 or 12 channels, held by multimode optical fiber ribbons, and using Infiniband protocol [3]. In addition, optical fiber cables and connectors lead to less cumbersome harness and easier cable management. Moreover they are insensitive to electromagnetic interferences. However, these modules that find their origin in the Siemens PAROLI precursor [4], already suffer from inherent limitations: mainly cost, large form factors, power dissipation and data rate. They embed VCSELs as light emitters, whose theoretical bandwidth could be pushed to 20 GHz, assuming that 10 Gbps VCSELs are nowaday a standard widely used in 10G Ethernet LANs. As a result, a new generation of optical parallel optic devices should rapidly replace the existing modules. These new modules could also find a market niche in the supercomputer market, where a shift to optical technologies is forecast in the next years, as it is the best way to improve inter-node data transmission and speed up the systems [5]. Photonics Packaging, Integration, and Interconnects VIII, edited by Alexei L. Glebov, Ray T. Chen Proc. of SPIE Vol. 6899, 68990Y, (2008) X/08/$18 doi: / SPIE Digital Library -- Subscriber Archive Copy Proc. of SPIE Vol Y-1

2 Finally, the main challenges and requirements to be addressed by this new class of devices should be the following: - High bandwidth over distances in the range between 1m to 100m. - Multichannel optical device using VCSELs as emitters. VCSEL are now a mature product, widely used for datacom emitters, as they allow high speed (up to 10 Gbps), high efficiency, efficient launch into standard multimode fibers, low noise. Moreover, they are reliable, small size, wafer level testable, and VCSEL arrays are easy to obtain. The wavelength used should be 850 nm, as 850nm high data rate VCSELs are a mature product, and multimode fibers are convenient for use on short reaches (several tens of meters). - Low profile dimensions (<8 mm height) and small form factor. Indeed, existing standards like POP-4 exhibits standard dimensions of 43x18x15 mm, that is not small regarding the high aggregated bandwidth targeted at the backplane. In addition, small form factor modules enable an easier HF lines management. - Power dissipation has to be kept below 1W in order to achieve easy heat dissipation, even when Small Form Factor cases are used. - Low cost (in order to stay competitive with copper-based solutions). This requirement leads to the use of advanced packaging technology like flip-chip bonding that exhibits high yields and high throughputs. - As far as possible, one can expect that equipment manufacturers would prefer considering the optical device just like any other electrical Multi-Chip-Module (MCM). So it should be either Surface Mountable, or a pluggable device. - Signal Integrity. Bit Error Rate < s -1 is required in most optical links applications. - Scalability to higher bandwidth and/or channel count. A last the location of the optical device onto the electronic card should be carefully examined. As data rate increased, traditional PCB made of FR-4 material also exhibits limitations in term of maximum HF line length allowed. SNAP12 and POP4 modules are used to be mounted at the edge of the cards, potentially quite far from the last electronic processor IC. The new class of devices must offer the flexibility to be soldered or plugged anywhere on the printed circuit board (PCB) as any other electronic device, for instance close to integrated circuits with high speed IO. In the past, some research works have been led following the previous requirements, with aggregated bandwidth of 100 Gb/s or more [6, 7]. The modules reported always use VCSELs and multifiber MTP(R) connectors as optical interfaces. Among the advanced works studied in the past year, one should already mention the MAUI project, whose demonstrators combine CWDM and Parallel optics technologies to get 500 Gbp/s aggregated bandwidth using 4 multiplexed wavelengths per channel [8]. In this document, we present a market oriented approach, using extensively advanced packaging technologies to cope with the previously quoted requirements. The transceiver (4-channel emitter/4-channel receiver) that have been developed by Intexys Photonics together with CEA-LETI/MINATEC is a Multi Chip Module based on VCSEL and Photodiode arrays flip-chipped onto a glass chip motherboard with the related electronics (Laser Diode Driver and Transimpedance Amplifier). This approach combines state-of-the-art surface mount technologies and advanced MCM technologies. We will see how it has led to a very compact module that can be mounted onto a PCB as any other component. We will also describe how this design is compatible with a hermetic sealing process we have developed. Finally, the optical coupler of the module with a multiple fibers connector is presented in detail from the set up to the alignment method. 2. MULTI-CHIP-MODULE TECHNOLOGY The design presented here is based on advanced MCM technologies well known in the microelectronic industry [9]. The basic concept is to integrate both OE chips (ex : VCSEL array, photodiode array) and IC chips (ex : driver, transimpedance amplifier) onto a very small motherboard (fig. 1). The motherboards are manufactured on wafers using microelectronic technologies which are already available and compatible with mass production. Typically, for 2x4 or 1x12 transceivers, the motherboard is only 10x10mm² maximum. In the same way, the chips are bonded using collective flip-chip hybridization technologies on a wafer to address the requirements for low cost and high yield manufacturability. Typically, we use self-aligning indium micro-bumping hybridisation for OEs and gold stud-bumping for ICs. The positioning accuracy of those technologies achieves very compact modules with chips less than 200 microns from each Proc. of SPIE Vol Y-2

other. In this case, the use of fused bumps instead of wire bonds and the shortness of the RF lines between ICs and OEs lead to a high signal integrity even at a fast rate. OEs ICs 2mm Fig. 1.

3 other. In this case, the use of fused bumps instead of wire bonds and the shortness of the RF lines between ICs and OEs lead to a high signal integrity even at a fast rate. OEs ICs 2mm Fig. 1. Top view of a MCM on a glass motherboard with VCSELs array chip, photodiodes array chip, ICs, and SMCs. For the laser emitters, multimode VCSELs have been selected as they exhibit several advantages including commercial availability at 850nm, reliability (demonstrated to be substantially higher than EELs) and lower cost, due to on-wafer testability [10]. In term of optical characteristics, VCSELs exhibit a circular low divergent beam allowing high fiber coupling ratio. VCSELs and photodiodes arrays are flip-chip bonded via a CEA licensed technique using indium microbumping. The self-alignment accuracy of this technique has been measured to be less than a few tenths of a micron [11]. This way, we may consider that the optical axis of all the VCSELs and all the photodiodes are respectively perfectly aligned. This pre-alignment is a determining advantage for the optical coupling with a single multifiber ribbon or a parallel connector as they are defined with a standard pitch. Advantageously, we have selected a transparent material at 850nm for the wafer dedicated to receive the motherboard circuit. This way, the electrical contacts and the chips are placed with the circuit on the front side of the motherboard while optical laser signals are emitted or received through the back side. This distinction offers flexibility in the packaging design : on the front side we only deal with electrical interconnects and heat dissipation, on the back side we only deal with optical fibers coupling. Moreover, we will see later in this paper how this design is also favourable to a hermetic packaging. 3. SURFACE MOUNT OPTICAL DEVICE APPROACH The approach we present has been selected in order to both combine state-of-the-art surface mount technologies and advanced MCM technologies. The objective is to obtain a surface mount optical device (SMOD). This way, such an optical component can be managed as any other electrical component in the assembly line onto PBC. Moreover, compared with SNAP12 or POP4 modules, these optoelectronic transceiver components are able to move from the edge to anywhere on the PCB. For instance, they can be placed very close to integrated circuits with high speed IO in order to deal with PCB limited bandwidth with lines length. Then, we have chosen to mount our MCM into a package with standard electrical interface as Leadless Chip Carrier (LCC) or Land-Grid-Array (LGA). The package is just slightly larger than the MCM in order to preserve our small footprint objective (fig. 2). In this paper we present a R&D demonstrator made using a standard 17x17mm² LCC44 package in co-fired alumina : a smaller package could be obtained with a custom design. A BGA or pluggable version is also available to withstand specification of the most demanding application where reparability is a major concern. Proc. of SPIE Vol Y-3

glass motherboard IC laser signal OE Fig. 2. Schematic of the architecture with MCM connected and bonded onto a ceramic package.

Indeed, thermally the ICs dissipation is done from the MCM through the package towards the PCB. Electrically, the MCM contacts are all around on the edge of the motherboard.

Initially, the gold studs are about 80µm high. After the thermocompression bonding the gold stud height is reduced to about 50µm (fig. 3)

50µm height gold studs between the MCM motherboard and the ceramic package Thermally, there is a gap of about 100 to 150µm to fill between the ICs and the package (fig.

Therefore, a thermal joint is added during the stud bumps thermocompression.

4 glass motherboard IC laser signal OE Fig. 2. Schematic of the architecture with MCM connected and bonded onto a ceramic package. Thus the two main challenges to deal with are the MCM/package electrical interconnects and ICs/ package thermal joint. Indeed, thermally the ICs dissipation is done from the MCM through the package towards the PCB. Electrically, the MCM contacts are all around on the edge of the motherboard. This bonding must deal with the ceramic package bow which is typically about 10-20µm over a 10mm length. Therefore we have selected and validated a gold-stud bumping bonding process. Initially, the gold studs are about 80µm high. After the thermocompression bonding the gold stud height is reduced to about 50µm (fig. 3). ceramic package MCM motherboard Fig µm height gold studs between the MCM motherboard and the ceramic package Thermally, there is a gap of about 100 to 150µm to fill between the ICs and the package (fig. 2), depending on the components thickness tolerances. Such a gap in the air would lead to a thermal resistance higher than 500 C/W for an area of about 8mm². Therefore, a thermal joint is added during the stud bumps thermocompression. Indeed, this process requires typically a pressure of about 4kg with a heating peak at 200 C, which is enough to cure a thermally conductive adhesive or to mold a soft metal like indium. With thermal conductivity of about 20W/m.K for a very good thermally conductive adhesive and 80W/m.K for indium, the thermal resistance is then reduced to less than 1 C/W. Thus, the module has an appropriate package to be mounted onto a PCB by soldering or plugged into a socket as any other surface mountable component. 4. HERMETICITY Additionally a hermetic approach is investigated to be compatible with telecom standards. The cavity size of our system is less than 10mm 3 and according to norm MIL-STD-883E for such cavities the reject limit is a leak rate of atm.cc/s of Helium. So, the glass motherboard which contains all the optoelectronics components is bonded onto a ceramic cap via a metallic ring for hermeticity and gold stud bumps for electrical signals. Gold stud bumps are connected to vias which are placed inside the seal ring (Fig. 4) so that the RF lines do not cross the metallic ring which would then act as a barrier on signals. Proc. of SPIE Vol Y-4

cavity. This process is based on thermocompression : this way, the hermetic sealing and the electrical contacts are obtained simultaneously with the thermal joint presented previously.

The gross leak rate may be performed using a perfluorocarbon detector and indicator fluid. For leaks greater than 10-3 atm.

Possible leaks are observed by a stream of bubbles of entrapped air expanding and escaping from the device. It is also possible to measure leak rate greater than 10-5 atm.

5 seal ring electrical vias Fig. 4. Ceramic package with a metallic seal ring A collective fluxless and no-clean process to achieve this bonding has been developed in order to be able to trap only an inert gas as nitrogen into the cavity. This process is based on thermocompression : this way, the hermetic sealing and the electrical contacts are obtained simultaneously with the thermal joint presented previously. Following the norm, two leak rate tests have been performed to validate our sealing process: a gross leak rate and a fine leak rate. The gross leak rate may be performed using a perfluorocarbon detector and indicator fluid. For leaks greater than 10-3 atm.cc/s the component is placed at least two inches below the surface of the indicating fluid, maintained at 125 +/-5 C. Possible leaks are observed by a stream of bubbles of entrapped air expanding and escaping from the device. It is also possible to measure leak rate greater than 10-5 atm.cc/s, by placing the device under vacuum and covering the device with the fluorinert detector fluid followed by at least 3 hours of pressurization. Following this step the device is placed under the detector fluid at 125 C, the low boiling detector fluid entrapped will then vaporize in a stream of bubbles easily identified. This final gross leak closes the sensitivity gap between gross leak and fine leak test. Several techniques may be used to measure fine leak rate, typically the device is placed under a Helium pressurized chamber then placed under a vacuum chamber connected to a mass spectrometer able to detect Helium. In this case the time between immersion in Helium and detection is generally too long to detect gross leaks (leaks greater than 10-5 atm.cc/s) as the gas has already left the sample before being measured. However in our lab we have set up a leak rate procedure using an aspersion method that follows the test condition A4 of the norm. In this method a fixture is directly mounted onto the leak detector (a Helium spectrometer) and proof of the fixture integrity is first demonstrated (that is no leak at the interface between the fixture and the detector is observed). A cavity must be performed through the package to be tested and mounted hermetically to the fixture. The external portion of the package is flooded with Helium gas and the resulting leak rate is measured, the sensitivity of our device here is about atm.cc/s. Using this method there is no dwell time between the aspersion and the measurement so that both fine leaks and gross leaks may be tested, it is however a destructive test as it implies to drill a hole in the cavity to be measured. Four modules were then fabricated and first measured out house using the Helium pressurized test, then measured in house using the aspersion test. They were all measured with a leak rate below atm.cc/s. These samples were then subjected to 30 thermal shocks, that is an immersion in iced water followed by an immersion in boiling water and the leak rate was measured again. After the 30 shocks no modification of the leak rate was noticed indicating a reliable joint. 5. OPTICAL COUPLING The module presented here is a 2x4 10Gbps transceiver with one emitter array with four 850nm VCSELs and one receiver array with four photodiodes (PD). The optical coupling is required with multimode fibers, typically 50/125 OM2 or OM3. Thanks to our self-aligning flip-chip bonding technology, we benefit from a submicron positioning accuracy between the VCSEL array and the PD array : therefore both emitters and receivers optical axis are all aligned on an array with a standard 250µm pitch. This way, we can use a single lens array with 250µm pitch for optical coupling with a standard multiple fibers connector. We have then developed a very compact and low profile optical coupler through the back side of the transparent motherboard. A moulded corner type coupler array has been selected to obtain appropriate magnification ratios for both VCSEL to fiber coupling and fiber to PD coupling (Fig. 5). Indeed, comparing the numerical apertures (NA), VCSEL to fiber coupling requires a magnification ratio greater than 1 as VCSEL NA is about 0.3 while 50/125 fiber NA is about Proc. of SPIE Vol Y-5

0.2. For fiber to PD coupling, if we compare the fiber core diameter of 50µm with the PD active area diameter of 70µm, then a magnification ratio smaller than 1.4 is required.

Moulded corner type coupler array mounted at the back side of the transparent motherboard for optical coupling Measured optical coupling performances are about 2dB insertion losses for VCSEL to fiber

6 0.2. For fiber to PD coupling, if we compare the fiber core diameter of 50µm with the PD active area diameter of 70µm, then a magnification ratio smaller than 1.4 is required. Let s note that the selected lenses array is also designed for passive alignment with standard multiple fibers connector as two 700µm guiding pin holes are available. Fig. 5. Moulded corner type coupler array mounted at the back side of the transparent motherboard for optical coupling Measured optical coupling performances are about 2dB insertion losses for VCSEL to fiber coupling and 1dB for fiber to PD coupling. Typically, positioning tolerance is about ±5µm for 1dB additional losses. Then, a visual alignment of the lenses with the VCSELs and the PDs with a flip-chip bonding equipment leads to 1-2dB additional losses. Those losses are mainly due to fabrication tolerances on the plastic lens array, however we have also validated an alignment method to reduce their impact. This method is still a visual alignment with a flip-chip bonding equipment but the points to align with the VCSELs and the PDs are accurately localized by coupling light from a multiple fiber connector (Fig. 6). flip-chip vision module Ceramic package MCM optical spots multiple fibers connector 850nm Fig. 6. Optical coupler alignment set up on a flip-chip bonding equipment Proc. of SPIE Vol Y-6

Super-imposition of alignment spots images with VCSELs (left) and PD (right) image This method suppresses the impact of some fabrication tolerances on the plastic lenses array (ex : corner angle) as

7 The focused spots are then at the exact locations where the VCSELs and the PDs (fig. 7) must be aligned. Fig. 7. Super-imposition of alignment spots images with VCSELs (left) and PD (right) image This method suppresses the impact of some fabrication tolerances on the plastic lenses array (ex : corner angle) as well as some placement tolerance (ex : parallelism between the lens and the motherboard). This way, additional losses due to alignment and placement are reduced to less than 1dB. So, the average launched power level is typically about -1dBm. 6. CONCLUSION The high speed transceiver presented here introduces a merging approach of parallel optics packaging and surface mount technologies. Optical and Electrical packaging issues have been treated simultaneously in order to develop a compact and low profile module that can be placed anywhere on a PCB, and especially very close to integrated circuits requiring high speed IO. Our approach both combines state-of-the-art surface mount technologies and advanced MCM technologies. The ceramic package used exhibits standard electrical interface to be soldered onto a PCB or plugged into a socket. Moreover, this package makes it possible to obtain a hermetically sealed module. On another hand, MCM technologies with flip-chip bonding offer several benefits. First, well-known advantages are high I O density and small footprint which makes this first-level interconnection technique very attractive considering high-frequency communications. Second, the accurate self-alignment property of our indium micro-bumping hybridization achieves a design with a very simple optical coupler compatible with a very accurate visual alignment method. This approach is currently applied to a 2x4x10Gbps transceiver following the required specifications of the 10G Ethernet standard. This standard defines a version of Ethernet with a nominal data rate of 10 Gbit/s over fiber and InfiniBand "like" copper cabling specified by the IEEE standard. Today, the full experimental demonstration of this design requires the use of high speed ICs currently under evaluation. Proc. of SPIE Vol Y-7

8 REFERENCES 1. C. Berger, M.A.Kossel, C. Menolfi, T.Morf, T.Toifl, M.L. Schmatz, "High-density optical interconnects within large-scale systems", Proceedings SPIE 4942, (2003) 2. Internet site : 3. A.F. Benner, M.Ignatowski, J.A.Kash, D.M. Kuchta, M.B. Ritter, "Exploitation of optical interconnects in future server architectures", IBM J. Res. & Dev., 49 (4/5), (2005) 4. H. Karstensen et al., Parallel Optical Link (PAROLI) for Multichannel Gigabit Rate Interconnections, Proc. ECTC (1998) 5. K. Takeushi, "Technical Trends in Optical Interconnection Technology", Science and Technology Trends, Quarterly review, (12), (2006) 6. L.A Buckman et al., Parallel-Optical Interconnects >100 Gb/s, J. Of Lightwave Tech., 22 (9), (2004) 7. D.M. Kuchta et al., 120 Gb/s VCSEL-Based Parallel-Optical Interconnect and Custom 120-Gb/s Testing Station, J. Of Lightwave Tech., 22 (9), (2004) 8. B.E. Lemoff et al., 500 Gbps Parallel-WDM Optical Interconnects, Proc. ECTC (2005) 9. R. Tummala, Fundamentals of Microsystems Packaging, McGraw Hill (2001) 10. B. hawkins et al., «Reliability of various size oxide aperture VCSELs», Proc. ECTC (2002) 11. S. Bernabé et al., Highly integrated laser/driver module for 10 Gb/s miniature optical assembly», Proc. ECTC (2005) Proc. of SPIE Vol Y-8

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