Noncoherent Equalizer for DECT System. Master of Science Thesis in the Programme Integrated Electronic System Design XIAOYU TENG WEICHAO ZHANG

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1 Noncoheren Equalizer for DECT Sysem Maser of Science Thesis in he Programme Inegraed Elecronic Sysem Design XIAOYU TENG WEICHAO ZHANG Chalmers Universiy of Technology Universiy of Gohenburg Deparmen of Compuer Science and Engineering Göeborg, Sweden, May 1

2 The Auhor grans o Chalmers Universiy of Technology and Universiy of Gohenburg he non-exclusive righ o publish he Work elecronically and in a non-commercial purpose make i accessible on he Inerne. The Auhor warrans ha he/she is he auhor o he Work, and warrans ha he Work does no conain ex, picures or oher maerial ha violaes copyrigh law. The Auhor shall, when ransferring he righs of he Work o a hird pary for example a publisher or a company, acknowledge he hird pary abou his agreemen. If he Auhor has signed a copyrigh agreemen wih a hird pary regarding he Work, he Auhor warrans hereby ha he/she has obained any necessary permission from his hird pary o le Chalmers Universiy of Technology and Universiy of Gohenburg sore he Work elecronically and make i accessible on he Inerne. Noncoheren equalizer for DECT sysem Xiaoyu Teng Weichao Zhang Xiaoyu Teng, May 1. Weichao Zhang, May 1. Examiner: Lars Svensson Chalmers Universiy of Technology Universiy of Gohenburg Deparmen of Compuer Science and Engineering SE Göeborg Sweden Telephone Cover picure: A ypical srong reflecive environmen, see deailed informaion abou fading channel in Chaper 3. Deparmen of Compuer Science and Engineering Göeborg, Sweden May 1

3 Absrac Digial European Cordless Telecommunicaion DECT, as a sandard for cordless indoor wireless communicaion in Europe, is widely used in hospials, offices and facories. Bu is performance can be consrained by channel dispersion, and his can limi he use of DECT sysem in reflecive environmens. In his maser hesis projec, non-coheren equalizaion schemes are invesigaed. Differen equalizaion algorihms are simulaed in Malab and a leas mean square LMS algorihm based baseband equalizer is implemened in a field programmable gae array FPGA. Bu his mehod is proved insufficien o solve he severe mulipah fading problem. Anoher ype of equalizer called passband equalizer is saed aferwards, and a required bi error rae BER can be achieved in mulipah fading channels up o 5 ns delay spread. This projec includes boh simulaion and hardware implemenaion. In his hesis, simulaions of wo ypes of equalizaion mehods LMS baseband and passband equalizer and implemenaion of he LMS baseband equalizer in FPGA are inroduced. The challenge of fuure work and is possible refinemen are also analyzed. Key word: DECT, non-coheren equalizer, LMS algorihm.

4 Acknowledgemen We would like o hank he hardware secion of ASCOM Sweden AB for giving us his opporuniy o work in such an ineresing projec. We would also like o hank he manager Thomas Harju and our supervisor Mikael Nysröm for heir generous suppor. Moreover, we would like o hank our examiners from Chalmers Universiy of Technology, Mas Viberg and Lars Svensson, for heir valuable feedback and proof reading on his maser hesis. This hesis work has been performed a ASCOM in Gohenburg from March o July, 9. Abou ASCOM Wireless Soluions: ASCOM Wireless Soluions leads he way in delivering value for cusomers by providing hem wih compeiive soluions for wireless on-sie communicaion o suppor and opimize heir mission-criical processes.

5 Table of Conen 1. Inroducion Background Problem Descripion Thesis Ouline Lis of Acronyms.... DECT Sysems Descripion Proocol and Packe Forma Transceiver Scheme Mobile Radio Channel and Projec Specificaions Pah loss, Large Scale Fading and Small Scale Fading Impulse Response of he Wireless Radio Channel Parameers of Mobile radio channel Limiaions of This Projec Modern Elecronic Technologies of Digial Signal Processing Digial Signal Processors DSPs Applicaion Specific Inegraed Circui ASIC Field Programmable Gae Array FPGA FIR Filer and Equalizer Techniques Inersymbol Inerference Digial LTI Filer and Adapive Filer Baseband Equalizaion Passband Equalizaion and Fracionally Spaced Equalizaion Sysem Design and Simulaion Resul Analysis Overview of he Design

6 6. AD Conversion Demodulaion Mehod Simulaion and Resul analysis LMS Baseband Equalizer and Resul Analysis Limiaion of LMS Baseband Equalizaion for Non-coheren Demodulaion Hardware Implemenaion and Verificaion Exernal PCB Board FPGA Developmen Board Basic DSP Arihmeic Implemenaion on FPGA Band-Pass Filer and Lowpass Filer Demodulaion Synchronizaion LMS Equalizer Resource Uilizaion Simulaion and Verificaion Passband Equalizaion and Analysis of he Resul Poenial Mehods for Improving he Equalizer Passband Equalizaion Performance of Passband Equalizaion Conclusions and Suggesions for Fuure Work Conclusion Hardware Implemenaion Analysis Issues for Passband Equalizer Implemenaion References... 8

7 1. Inroducion 1.1 Background As a low cos and reliable digial voice elecommunicaion sysem, DECT can provide cordless communicaions for high raffic densiy, shor range communicaions, and covers a broad range of applicaions and environmens [1]. Bu wih he populariy of DECT increasing, he sysem can also run ino problems in cerain environmens. For example, he DECT sysem is very sensiive o he environmens like seel consruced workshops, in which srong reflecion of microwaves can occur. Unlike Global Sysem for Mobile communicaion GSM, he DECT sandard does no have any advanced equalizaion echnologies o fix his mulipah propagaion problem due o is low cos sraegy. As he desire of improving DECT sysem performance srongly grows and he cos of elecronic devices like FPGA and digial signal processors DSPs decreases, some simple and efficien mehods can be implemened in he DECT sysem. Some echniques have already been used o fix mulipah fading problems in wireless communicaions, such as increasing he complexiy of he modulaion scheme, space diversiy and equalizaion. Previously, he anenna diversiy has been inegraed o he handses and base saions of he DECT sysem []. Apparenly, he performance can be improved o a cerain level. Bu in order o obain higher voice qualiy and daa ransmission reliabiliy, some oher echniques need o be invesigaed. The iniiaor of he projec, ASCOM Sweden AB, decided o explore equalizaion mehods for DECT. Thereby, ASCOM Sweden AB sared his hesis in March 9 in cooperaion wih he Signal and Sysems and Compuer Engineering deparmens a Chalmers o invesigae he DECT receiver sysem. 1. Problem Descripion Due o is good performance and low cos in erms of implemenaion, he non-coheren receiver has been a very aracive mehod applied in wireless ransceiver design. Equalizaion is an efficien echnique o recover he desired signals from he Iner-symbol Inerference ISI. The purpose of his hesis is o improve he performance of he DECT sysem in severe ISI environmens on he premise of low power cos by invesigaing a feasible equalizaion algorihm and inegraing i ino he non-coheren receiver. 1.3 Thesis Ouline This repor consiss of 1 chapers. 1

8 Chaper 1 is a brief inroducion of he projec. Chaper gives an overview of he DECT sysem. Chaper 3 gives a general descripion of he mulipah channel. Chaper 4 saes modern elecronic echniques for DSP. Chaper 5 inroduces differen equalizaion srucures for ISI eliminaion. Chaper 6 focuses on he design of an LMS baseband equalizer and analysis of is performance. Chaper 7 inroduces hardware implemenaion of an LMS baseband equalizer. Chaper 8 is devoed o he design of a passband equalizer. Chaper 9 provides he conclusion and some prospecive fuure work. Chaper 1 liss he references. 1.4 Lis of Acronyms Abbreviaions ASIC Applicaion-Specific Inegraed Circui CMOS DECT DFE DSP ETSI FDMA FPGA GFSK GMSK GSM ISI LPF LMS Complemenary Meal-Oxide-Semiconducor Digial Enhancemen Cordless Telecommunicaions Decision Feedback Equalizer Digial Signal Processing European Telecommunicaions Sandards Insiue Frequency Division Muliple Access Field Programmable Gae Array Gaussian Frequency Shif Keying Gaussian Minimum Shif Keying Global Sysems of Mobile communicaions Iner-Symbol Inerference Low Pass Filer Leas Mean Square

9 MLSE PCB RLS TDMA TDD VCO Maximum Likelihood Sequence Esimaor Prined Circui Board Recursive Leas Square Time Division Muliple Access Time Division Duplex Volage Conrolled Oscillaor 3

10 . DECT Sysems Descripion.1 Proocol and Packe Forma DECT, also known as Digial European Cordless Telephones, is a sandard developed by European Telecommunicaions Sandards Insiue ETSI and was finalized in 199 [1]. DECT provides personal communicaions wih cordless indoor communicaion sysems insead of he wired soluion. An in-building Privae Branch Exchange PBX or he Public Swiched Telephone Nework PSTN is used o supply he connecion among he headses [3]. As i is defined in he DECT sandard, DECT can provide low power radio access beween handses and fixed base saions a a range of up o a few hundred meers. TDMA/FDMA/TDD is employed in DECT physical layer. There are 1 pairs of ime slos in one frame of 1ms lengh. The firs 1 of hem are used for uplink, and he res are used for downlink. The channel bandwidh is 1738 khz which is 1.5 imes he daa rae of 115 kbps according he specificaion of he sysem. The DECT sysem occupies he radio specrum from 188 MHz o 19 MHz and 1 carrier frequencies are allocaed wihin his specrum. Each carrier can handle an enire frame including boh uplink and downlink which is differen from he GSM sandard. Each ime slo consiss of 48 bis, where he firs 3 bis and he las 6 bis are defined as preamble bis and guard ime respecively, and he middle 388 bis are daa. The srucure of one frame is depiced in Figure 1. Figure 1: The srucure of one ime slo. The firs 16 bis of preamble consising of are used for clock recovery and frequency offse compensaion; he laer 16 bis paern is he slo synchronizaion in digial field. The daa sequence is made up by 388 bis including he payload and error deecion par, bu here is no error correcion in his field. 4

11 . Transceiver Scheme..1 Modulaion Scheme The modulaion scheme applied in DECT is Gaussian frequency shif keying GFSK wih modulaion index of.5, which can also be acceped as a special case of Gaussian minimum shif keying GMSK commonly known from GSM. As a binary modulaion scheme, he phase of GFSK is roaed by ±9º in one symbol duraion o presen he coming symbol as 1 or. The meri of GFSK is is low cos in hardware and requiring low power amplifier design due o is consan envelope. Specrum efficiency is anoher aracive poin of GFSK. Since he digial sequence is shaped wih a Gaussian low pass filer prior o he frequency modulaor, he side lobe level is lowered, which reduces he inerference from adjacen carriers effecively. Because of hese wo advanages, GFSK is widely used in personal wireless communicaions like DECT and Blueooh. The deailed characerisics abou GFSK are described in [4] and [5]. In his projec, only he implemenaion is presened. Normally, he GFSK signal is generaed by passing a non-reurn-ozero NRZ sequence hrough a Gaussian low pass filer followed by an FM-VCO. Anoher implemenaion mehod called quadraure baseband modulaion is no used here due o is complexiy. The mahemaical expression of he Gaussian low pass filer can be wrien as.1, and he block diagram of he GMSK modulaor is shown in Figure. 1 g = exp.1 πσt σ T whereσ = ln / πbt, and T is used o denoe he symbol duraion. GMSK modualaion Inpu daa Gaussian LPF VCO GMSK signals Figure : Block diagram of GMSK modulaion. LPF: low pass filer, VCO: volage-conrolled oscillaor.. Demodulaion Scheme In a DECT receiver, i is common o use a quadraure deecor o exrac he baseband signals from inermediae frequency IF signals. The enire demodulaor srucure is shown in Figure 3. Compared o he coheren demodulaion mehod, he non-coheren demodulaion has a slighly higher BER [17]. However, he complexiy of a non-coheren demodulaor is much lower. There 5

12 are also some oher demodulaion schemes discussed in [1] and [6]. Due o he advanage of low cos, quadraure deecor is he main demodulaion mehod o be invesigaed in his projec. GMSK demodulaion Modulaed IF inpu signal 9º LPF Demodulaed oupu Figure 3: GMSK non-coheren demodulaion. 6

13 3. Mobile Radio Channel and Projec Specificaions 3.1 Pah loss, Large Scale Fading and Small Scale Fading The mobile radio channel places fundamenal limiaions on he performance of wireless communicaions. Compared o he saionary and predicable wired channel, he wireless channel characerisic is varying wih ime beween he mobile saions and handses. Thereby, i is very difficul o analyze he wireless channel. In general, he variaion of he channel can be aribued o wo main caegories, he large scale fading effecs and he small scale fading effecs [7]. Large scale fading effecs mainly describe he aenuaions of signal power caused by absorpion, reflecion, scaering and he dissipaion of he power radiaed beween he base saions and mobile handses. Usually hey are called pah loss and shadowing. Variaions due o pah loss occur over long disances 1~1 meers. Shadowing is caused by obsacles beween he ransmier and receiver, and i occurs over disances proporional o he lengh of he obsacles 1~1 meers. Small scale fading effecs refer o he channel variaion caused by he consrucive or desrucive addiion of mulipah componens. This usually happens over shor disances, especially in indoor environmens; hence, he mulipah fading is he main facor o affec he communicaion qualiy of DECT. Figures 4 and 5 illusrae he mulipah fading environmen and is mahemaical model. Mulipah propagaion and he speed of a mobile are wo main facors influencing small scale fading effecs. Mulipah propagaion, jus as is name implies, means ha he ransmied signals arrives a he receiver from differen pahs a slighly differen imes. This phenomenon, which is caused by reflecion and scaering from he objecs in he ransmission pahs, could inroduce signal variaions in boh ampliude and phase when differen pah componens combine a he receiver side. This can cause a severe flucuaion in he signal srengh, and disor he original signals severely. Besides, he ime dispersion caused by he mulipah propagaion, will inroduce ISI o he received signals. If he ime dispersion is severe, his canno be acceped by he receiver. The moion beween he base saions and handses or he movemen of objecs in he ransmission pah can resul in Doppler frequency shif, and he incoming waves would experience a random frequency modulaion during he ransmission. If he Doppler shif is relaively serious, he designed informaion canno be exraced wihou addiional echniques a he receiver side. 7

14 Figure 4: Mulipah signals during he ransmission IFsignals -1.5 Delayed IF Delayed IF Combinaion Figure 5: Simulaion of mulipah ransmission. 3. Impulse Response of he Wireless Radio Channel When a single pulse passes hrough a mulipah channel, a pulse rain will appear a he receiver wih each pulse corresponding o he line-of-sigh LOS or mulipah delay componens. So a linear finie impulse response FIR filer is quie inuiive o model he ime invarian channel []. However, in realiy, ime variaion is a feaure of wireless radio channels. Thus, an FIR filer wih ime varying impulse response is more suiable o represen he radio channel. The mulipah fading channel model is illusraed in Figure 6. 8

15 Figure 6: The ime varying discree model for mulipah channels. If here is no LOS componen in he channel, like sae 1 in Figure 6, he small scale fading envelope obeys a Rayleigh disribuion given by r r p r = exp r σ σ 3.1 r < where σ is he ime-average power of he received signals and r is he envelope of he received signals. If a dominan LOS componen exiss, he envelope is Ricean disribued. The Ricean disribuion is defined by r r + A Ar p r = exp I r σ σ σ 3. r < Here, A is he peak ampliude of he dominan signal, whereas I is he modified Bessel funcion of he firs kind and order zero. Usually, he Ricean disribuion is specified by a parameer K, which is he raio beween he deerminisic signal power and he variance of he mulipah as described in 3.3. A K = 3.3 σ 9

16 When K equals o, he Ricean disribuion reduces o he Rayleigh disribuion, which also means ha he LOS disappears. 3.3 Parameers of Mobile radio channel The mos imporan characerisics of he channel, including power delay profile, coherence bandwidh, Doppler power specrum and coherence ime, are all derived from he channel auocorrelaion and scaering funcions. Denoing he ime varying channel impulse response by c,, he saisical characerisics of c, are described by is auocorrelaion funcion, given by: A c 1 1, ;, = E[ c ; c ; + ] 3.4 Moreover, when he channel is wide-sense saionary WSS channel wih uncorrelaed scaering US, 3.4 can be compressed as: E [ c 1 c 1 1 c ; c ; + ] = A ; δ[ ] = A, 3.5 The power delay profile A c is deermined by he auocorrelaion 3.5 wih Δ =. The scaering funcion is defined as he Fourier ransform of A c, Δ wih respec o Δ: jπρ S, ρ = A, e d c c 3.6 a. Rms Delay Spread and Coheren Bandwidh The mean delay spread μ Tm and roo mean square rms delay spread σ Tm are defined in erms of he power delay profile A c as: µ Tm = A c d A d c 3.7 µ Tm Ac d σ Tm = 3.8 A d c where μ Tm and σ Tm are he mean and rms values of T m, respecively. The rms delay spread can be used o roughly characerize he channel. Denoing he symbol period by T, when T > σ Tm, he signals will experience negligible ISI. Conversely, he signals will experience significan ISI when T < σ Tm. 1

17 This characerisic can also be obained in he frequency domain by aking he Fourier ransform of he power delay profile A c, resuling in A c Δf. The frequency B c, saisfying A c Δf when Δf > B c, is called he coherence bandwidh of he channel. If he ransmied signal occupies a wider bandwidh compared o he channel coherence bandwidh, given by B > Bc, he specrum magniude of he signal will experience differen fading in differen frequencies. This phenomenon is called frequency selecive fading. Conversely, if he signal bandwidh is lower han he coherence bandwidh B < B c, every par of he specrum will experience similar fading, which is called fla fading. A comparison beween frequency selecive fading and fla fading is shown in Figure 7. Figure 7: rms delay spread and coherence bandwidh for narrowband and wideband, respecively [7]. b. Doppler Spread and Coheren Time The ime variaion of he channel is deermined by he Doppler spread, which can be characerized from he Fourier ransform of he scaering funcion wih respec o, as wrien in 3.9: jπ f S f, ρ = S, ρ e d 3.9 c c When Δf =, S c ρ is he Doppler spread specrum of he channel. The maximum value of ρ, such ha S c ρ is greaer han zero, is called he Doppler spread of he channel, denoed by B D. The coherence ime can be obained by aking he inverse Fourier ransform of S c ρ, which leads o T c 1/B D. The relaionship beween Doppler spread and coherence ime is shown in Figure 8. 11

18 Figure 8: Coherence ime and Doppler spread [7]. Therefore, he channel can be classified as eiher slow fading channel or fas fading channel. In he slow fading channel, he channel impulse response changes a a rae much slower han he ransmied symbols, given by T < T c. In he fas fading channel, he channel impulse response changes faser han he symbols, i.e. T > T c. 3.4 Limiaions of This Projec Channel Specificaion The conen above in his chaper is he general knowledge of wireless radio channels. There are also some channel specificaions for DECT communicaion sysems. As menioned before, DECT is an indoor elecommunicaion applicaion. The proocol of DECT specifies he daa rae as 1.15 Mbps, which means ha he symbol duraion is.868ms. When he delay spread of indoor environmens is longer han 1% of he symbol ime, he inersymbol inerference canno be negligible [8]. In oher words, he ransmied signal would experience frequency selecive fading. Tha is, significan ISI would occur a he receiver. DECT is an applicaion ha only covers a range up o several hundred meers, which implies ha i is impossible o make a call in a high-speed vehicle. The maximum moion speed of he handses is up o 1.5 m/s like normal walking speed. Therefore, he Doppler specrum is much smaller han he signal bandwidh, and he slow fading will occur. In his case, a linear FIR filer can be used o model he DECT channel in one ime slo, as depiced in Figure 9. 1

19 Time invarian model for DECT channel h Figure 9: Discree ime model for he DECT channel. Two models of he mulipah channel are used in our simulaions. One is he channel impulse response wih each mulipah componen having equal gain as model D in Table 1; in he oher model, each pah gain is aenuaed as he delay is increasing as model E in Table 1. In Table 1, each value indicaes he delay spread versus he pah gain. Model Pah 1 Pah Pah 3 Pah 4 Pah 5 Pah 6 A ns/db / 5/-1 1/-13 15/-16 /-19 5/- B ns/db / 5/-5 1/-8 15/-15 /-1 5-/-9 C ns/db / 1/-17 /- 3/-3 4/-6 5/-9 D ns/db /-6 5/ 1/ 15/ / 5/ E ns/db / 1/ /-7 3/-13 4/-1 5/-8 F ns/db / 1/-1 /-13 3/-16 4/-19 5/-6 Table 1: The sandard discree-ime channel models in a wireless radio channel [9] Sysem specificaion In order o simulae he sysem in a more pracical way, a connecion is buil beween a handse and a signal generaor, which is similar o he connecion o a base saion. The uplink and downlink signals can be measured by connecing he oscilloscope o he exernal board as shown in Figure 1. The wave snapshos on he oscilloscope include he IF signals, he ransmied digial daa and he demodulaed or equalized signals, as shown in Figure 11, which can be used in Malab and Modelsim simulaions. 13

20 In he implemenaion, a pre-purchased FPGA developmen board Low Power Reference Plaform from Arrow Elecronics is used as he main developmen plaform. A differenial IF signal is exraced from he headse as inpu o he FPGA. A sequence of digial daa is oupu from he FPGA and fed back o he headse. The sysem clock of he handse wih he frequency of MHz is also used as a clock inpu o he FPGA and he exernal ADC board. This also consrains he maximum clock frequency of FPGA a MHz. Figure 1: The connecion beween he handse and he oscilloscope. Figure 11: Snapsho on he oscilloscope. 14

21 Figure 1: The differenial IF signal sampled in he oscilloscope. 15

22 4. Modern Elecronic Technologies of Digial Signal Processing Figure 13 shows a ypical applicaion of a digial signal processing DSP sysem, which can be found in mos wireless communicaion sysems and as in his projec. The analog signal is firsly fed hrough an analog ani-aliasing filer o suppress he unwaned frequency componens. I is hen followed by an analog-o-digial converer ADC, which is normally implemened wih a sample-and-hold componen and a quanizaion circui o conver he analog signal ino digial domain. The digial signal processing circuis perform he nex seps o process he digial signal such as filering, which is he mos frequenly used. Afer he DSP sysem, we could furher process he daa or generae an analog oupu signal such as an audio signal hrough a digial-oanalog converer DAC [1]. Digi Ou Analog In Ani Aliasing Filer ADC Digi Signal DSP Sysem DAC Analog Ou Figure 13: A ypical DSP applicaion. The inerfaces, beween he analog and digial world, ADC and DAC are very imporan componens in curren research and indusry. A fully-differenial ADC is used in his projec and will be inroduced laer. The DSP componens, which are always he key par in any projecs, can be implemened wih many alernaives bu he mos common ones are DSP, ASIC and FPGA. In his chaper, we give an inroducion o he mos popular inegraed circuis IC used for digial signal processing, and also some comparisons beween hem. 4.1 Digial Signal Processors DSPs Digial signal processors DSPs normally refer o specially designed processors for digial signal processing. Mos DSPs are sequenial insrucion based processors ha provide fas mahemaical compuing, such as shif and addiion, muliplicaion and addiion. Bu unlike ordinary microprocessors, DSPs are ofen used as a ype of embedded processors ha are buil ino anoher piece of equipmen and used for a special group of asks [11]. In his case, he DSPs assis he general purpose microprocessors such as microconrollers. This has been widely seen in cellular elephones, auomobiles and pleny of advanced scienific insrumens. 16

23 In fac, no many people use he word DSP o mean digial signal processor bu only hardware engineers. On he oher hand, i always refers o digial signal processing as in communicaion engineering. Mosly, digial signal processors are designed for digial signal processing. For example, a real world signal mosly in analog form can be convered ino digial daa and hen be analyzed. This analysis is always done in digial domain because when a signal has been convered ino digis; is componens can be isolaed, analyzed and rearranged more easily han in analog [11]. And afer DSP sysem finishing is work, hese digial daa can be convered back o an analog signal wih improved qualiy, such as removed inerference, amplified ampliude, ec, as has been described in Figure 14. For his purpose, hey usually have buil-in mahemaical blocks such as mulipliers, arihmeic logic unis ALU and shifers ha are special for DSP funcions. DSPs can be classified by heir dynamic inpu/oupu range ha is he processor s daa widh he number of bis i manipulaes and he arihmeic ype. Typically, hey are 3-bi, 16-bi or floaing-poin, fixed-poin. Each ype of DSP is suied for a paricular range of applicaions. Such as, 3-bi floaing-poin processor is used for image processing, 3-D graphics and scienific simulaions and 16-bi fixed-poin processor is usually for speech processing. Bu mosly, here is usually a wase of resource since he dynamic range is fixed for each DSP. 4. Applicaion Specific Inegraed Circui ASIC ASIC, as he name indicaes, is an inegraed circui which is designed for a paricular use. Normally, an ASIC is dedicaed o a single funcion, or a few funcions ha are unchangeable. The developmen period of an ASIC is relaively long when comparing wih a programmable circui ha ASICs could ake a year or even more o finish. Despie he cos of an ASIC design, i could be very cos effecive when he amoun is high, and normally i gives beer performance han is opponens. In mos cases, i is possible o make an ASIC o mee he exac requiremen for a specific applicaion and use an exac number of componens for his applicaion o avoid any addiional wase of resources. Nowadays, mixed signal ASIC enables boh analogue and digial funcions incorporaing ino one piece of IC. Therefore, ASIC is widely used in high volume producs such as cell phone, audio/video player, auomobile or oher similar applicaions. Tradiionally, ASICs were designed by direcly enering he silicon layou for he specified funcion, and his requires much longer developmen imes han nowadays. The siuaion has changed wih he improvemens in compuer-aided design CAD ools, and his enables more complicaed design of circuis. Designers ofen use a hardware descripion language such as VHDL or Verilog o describe he funcionaliy of heir circuis, and use a compiler o generae he silicon layou auomaically. Since he developmen and manufacuring of an ASIC is very expensive boh in ime and cos, here are differen levels of cusomizaion o reduce he cos. From he leas cusomizable level, hey are Gae Array level, Cell level and Full-cusom designs [1]. The more cusomizaion required, he more cos will be needed and also here will be higher risks of redesign as well as higher performance. A general ASIC design flow is shown in Figure 14. As shown, designing an ASIC is a long procedure, and here is a risk ha defecs could be found ou afer apeou for which he cos would be as high as redoing i again. 17

24 Archiecural Design Behavioral Modeling RTL Design Funcional Verificaion Synhesis Timing Verificaion Floor Plan and Rouing Archiecural Design Pos Rouing Verificaion Tape Ou Figure 14: General ASIC design flow. 4.3 Field Programmable Gae Array FPGA FPGA FPGA has experienced a remendous growh in recen years, and i has become a major player in he elecronic indusry. FPGA is an inegraed circui ha can be elecrically reprogrammed o become any kind of digial circui or sysem by he cusomer or designer. FPGA conains an array of user-programmable logical blocks ha could be designed o implemen combinaorial and sequenial circuis. FPGA could be considered as a simple glue logics echnology ha provides 18

25 programmable conneciviy beween hese logic blocks where he programmabiliy is based on eiher ani-fuse, EPROM or SRAM [13]. FPGA could be argued as a ype of ASIC echnology, since FPGA is an applicaion specified IC. Bu classic ASIC design requires addiional processing seps beyond hose required for an FPGA. These addiional seps provide ASIC wih performance and power advanage, bu also wih high non-recurring engineering NRE coss. On he oher hand, FPGA could gain a lo more ime o mee he ime-o-marke requiremen, and allows design errors being recognized a he lae sage of developmen o be correced wih very low coss. The mos common FPGA archiecure, as illusraed in Figure 15, consiss of an array of programmable blocks of differen ypes including logic block, memory and in recen devices DSP block. These blocks are surrounded by a programmable rouing channel ha allows he inerconnecion of he blocks o be cusomable. These channels are surrounded by programmable inpu/oupus ha connec he FPGA o he oher circuis. Figure 15: A simplified FPGA srucure. The logic block is he smalles programmable uni in he FPGA device archiecure. A ypical logic block consiss of a 4-inpu look-up able LUT and a flip flop, as shown in Figure 16. There is only one oupu, which can be eiher he regisered or he unregisered LUT oupu, and four inpus for he LUT and one clock inpu. In modern FPGAs, hese logic blocks could also be mulipliers, DSP blocks, embedded memories, ec. Some FPGA families employ PLL in he devices o enable muli-clock sysem and eliminae synchronizaion problem. 19

26 Figure 16: Srucure of logic block [38]. The funcions of an FPGA are usually defined by hardware descripion language HDL or a schemaic design. For a bigger sysem, HDL is ofen easier for he designer. By using elecronic design auomaion EDA ools, his funcion or behavior descripion is ranslaed ino a nelis which conveys he conneciviy informaion. This nelis can be fied ino he FPGA by using place-and-roue and hen a binary file is generaed which could be used o configure he FPGA. Mos modern FPGA vendors provide a library of predefined circuis or componens called IP cores, which could be in RTL regiser ransfer level level or nelis level, o simplify he design of a complex sysem. For example, in he Alera FPGA, a predefined library called Megafuncion is provided in heir EDA ool, which conains housands of IPs such as DSP funcions, I/O prooypes, memories and embedded processors ha are opimized srucure for Alera FPGA archiecures [14] FPGA Versus DSP and ASIC Tradiionally, DSP processors have overwhelming advanages over FPGAs. FPGAs were used as a co-processor or conroller while he DSP processors deal wih he main calculaions. However, as he cos of FPGA decreases and he higher needs for processing capabiliies, high-end, DSPoriened FPGAs already have a huge advanage over high-performance DSP processors in erms of performance/cos [15]. In mos wireless applicaions, power is also a major consideraion for designers. Previously, FPGA was viewed as oo power-hungry as compared o DSP processors. Bu hanks o he developmen of CMOS echnologies, here has been a number of low-power FPGAs which could compee wih DSP processors in erms of power. Also, FPGAs, which are no consrained by a specific applicaion or hardware srucure, are much more flexible han DSP processors. Due o he highly flexible archiecure, FPGAs can ake advanage of heir highly parallel archiecure and offer an advanage in erms of performance/power. On he oher hand, DSP applicaions implemened on FPGAs ypically ake much more ime and effor han on a DSP processor, since mos FPGA designers sill use low level hardware descripion languages, while DSP processors are mosly programmed in he more sysem level C language. Alhough here has been some effor on high level FPGA design ools such as Sysem Generaor [39] from Xilinx and DSP builder [4] from Alera, hese ools have no been widely used ye. They are always hard o undersand and require engineers o do heir work in a new and unfamiliar way. Till now, here are sill big gaps from FPGA o ASIC in erms of higher performance, higher capaciy, lower power, more efficiency, mixed signal inegraion performance and uni cos for high volume, alhough mos FPGA vendors claims ha heir high-end FPGAs are a compelling

27 proposiion for ASICs design. According o recen experimenal measuremen [16], here is sill a quie significan gap beween FPGAs and ASICs. For modern FPGAs, here are 1 imes differences in silicon area, 3 o 4 imes in criical pah iming and 1 imes for dynamic power consumpion. However, due o heir archiecure, FPGA designs are much faser and easier and here is almos no recurring expenses when compare o ASIC design. So hey are much more suiable for experimenal applicaions and prooyping soluions. In wireless applicaions, FPGAs could be used o cope wih he ime-o-marke issue and defec debugging purpose and hen move on o build up heir own ASICs laer on. So, in his hesis projec, FPGA is used o fulfill he experimenal purpose. 1

28 5. FIR Filer and Equalizer Techniques In his secion, ISI and he soluions o ISI are discussed. Several ypes of equalizaion mehods are inroduced in his chaper. 5.1 Inersymbol Inerference Inersymbol inerference is a common disorion in elecommunicaion, which means ha one received symbol is inerfered by he neighboring symbols [18]. The following equaions are referenced from [19]. Denoing he received signal by rn, rn equals o he convoluion resul beween he ransmied signal xn and he discree channel impulse response h n wih lengh of L+1, and n is used o denoe he discree ime index: L r n = x n l h l + ω n l= L 5.1 Here, ωn is addiive whie Gaussian noise AWGN. The equaion can also be wrien as: 1 r n = x n h + x n l hl + x n l hl + ω n l= L L k = 1 5. where xn is he dominaing symbol in he receiver a ime n. There is also inerference from he previous and laer symbols, which is inferred by he second and hird erms in 5.. In his case, he receiver canno make an accurae decision when xn comes. Hence, some echniques should be employed in he receiver o reduce he inerference. One of he effecive soluions for ISI disorion is equalizaion o compensae or reduce he ISI effec. 5. Digial LTI Filer and Adapive Filer Digial demodulaors and equalizers can be considered as digial filers wih specified funcions. A digial filer performs mahemaical operaions on sampled, discree-ime signals o reduce or enhance cerain aribues in ime or frequency domain []. This is in conras o analog filers, which work on coninuous-ime signals. The mos commonly used digial filers are linear and ime invarian LTI, which means ha he impulse response of he filer ineracs wih he inpu signals hrough a linear convoluion. The linear convoluion process in he discree domain is formally defined by: x l f n l = f l x n y n = x n * f n = l 5.3 l l

29 where fn is he filer s impulse response, xn is he inpu signal and yn is he convolved oupu. Digial filers can be classified as FIR filers and infinie impulse response IIR filers, respecively [3]. As is name indicaes, FIR filers consis of a finie number of sample values, which reduce he above convoluion sum o a finie sum for each oupu sample insan. An IIR filer, on he oher hand, requires an infinie sum. The oupu of an FIR and an IIR filer a ime n in erms of heir inpu are described in 5.4 and 5.5, respecively: L y n = al x n l l= 5.4 L1 l= L y n = a x n l b y n l 5.5 l l= 1 l The filer can also be characerized by is sysem funcion. The ransfer funcion of FIR and IIR filers in he Z-domain are depiced in 5.6 and 5.7, respecively: L l= l H z = a l z 5.6 L1 l= 1 l al z l= H z = L l b z l Some imporan differences beween FIR and IIR filers are summarized as follows [1]: Normally, FIR filers require subsanially more filer coefficiens or aps han IIR filers for equivalen responses o perform he same funcionaliy. An FIR filer can be designed o have a linear phase response. Cerain ypes of FIR filers can be configured in a symmerical srucure o save compuaional resources. Symmerical even order FIR filers will require half he number of mulipliers and consume less logic space. An IIR filer conains poles. Sabiliy is deermined by ensuring ha he magniudes of he poles are less han uniy, i.e. he poles are wihin he uni circle. FIR filers are implemened direcly and always sable due o no poles, which can be inferred from 5.6 and

30 IIR filers can direcly emulae analog filers. Sandard ransformaions can be used o conver Buerworh, Bessel, and oher convenional analog filers ino digial filers. IIR filers performance is more sensiive o quanizaion error. Due o poenial sabiliy problems and more sensiiviy o quanizaion error, IIR filers are no used in his projec, even hough i has some advanages over FIR filers. Therefore, all filers involved in his projec are designed as FIR filers. Equalizers, as a special form of digial filers, will be inroduced in following pages. 5.3 Baseband Equalizaion According o heir posiion a he receiver, equalizers can be divided ino wo caegories: one is baseband equalizer, and he oher is passband equalizer. Simple block diagrams of hese wo ypes of equalizer are shown in Figure 17. Baseband Equalizer IF signal Demodul -aor Baseband signal Equalizer Esimaed symbol Passband Equalizer IF signal Equalizer Baseband signal Demodul -aor Esimaed symbol Figure 17: Block diagrams of baseband and passband equalizers, respecively. Equalizaion can also be classified as eiher linear equalizaion or non-linear equalizaion in erms of is characerisics. Baseband linear equalizaion, as a simpler mehod in equalizaion echniques, is discussed firsly Linear Equalizaion Linear equalizaion mainly includes zero forcing equalizaion and minimum mean square error MMSE equalizaion. Zero forcing equalizaion does no consider he effec of noise, and i is herefore seldom used in pracical design. Hence, MMSE and is adapive form are invesigaed in his secion. The coefficiens of MMSE equalizers are chosen o minimize he mean-square error, which consiss of he sum of he squares of all he ISI erms plus he noise power a he equalizer oupu [17]. Therefore, he signal-o-disorion raio could be maximized. The MSE crierion is defined as 5.8, and he minimizing coefficien vecor is given by 5.9 [19]. 4

31 T L MSE = E C R n d n 5.8 L where n is used o denoe he discree ime index ha represens as n = nt; he subscrip L is used o denoe he number of delay sages in he equalizer; is he received vecor, dn is he desired symbol and C R L n = [rn rn rn - L + 1] T L = [c c1... c L 1 ] equalizer weighs. The vecor of MMSE equalizer coefficiens, which minimizes 5.8, is given by: is he vecor of T C L 1 rr = R R 5.9 rd where R rr = E[ R n R n r n r n 1 r n = E... r n L + 1 r n L L T ] r n r n 1 r n 1... r n l r n r n r n L + 1 r n 1 r n L r n L and R rd = E[ R L n d n] = E[ d n r n d n r n 1... d n r n L + 1] T 5.11 As an LTI filer, he coefficiens of he MMSE equalizer do no change over ime. Bu in ypical DSP fields, such as speech processing, echo cancellaion, radar, sonar, seismology, or biomedicine, he applicaions require he filer coefficiens o vary over ime. A filer wih adjusable coefficiens is called an adapive filer [3]. Two basic algorihms for adapive filering will be aken ino consideraion in he following secions, i.e. LMS and RLS. a. LMS Algorihm LMS and RLS, as wo basic algorihms, are widely used in adapive filering. In he LMS algorihm, he updae a ime n is compued as : ˆ T d n = C n 1 R n 5.1 L L e n = d n dˆ n 5.13 C n = C n 1 + µ e n R n 5.14 L L L where d ˆ n is he esimaed oupu of equalizer, e n is he predicion error and µ is he sep size. 5

32 Apparenly, he desired symbol dn canno always be known by he receiver side. In order o keep updaing all he ime, he equalizer has o work in wo modes. The firs is he raining mode: in his mode, he equalizer knows a par of he desired symbols raining sequence. By deecing he raining sequence in he received signals, he adapive algorihm can compue and minimize he error by adjusing he ap weighs [1]. The lengh of he raining sequence depends on he number of equalizer coefficiens, which mus be deermined on beforehand. Normally, he duraion of he raining mode is no more han ens of symbols. I mus be noed ha if he channel has changed, he equalizer mus be rerained. In his projec, since he channel is ime invarian during one ime slo, he equalizer is no rerained in ha duraion, bu i mus be rained when nex ime slo comes. The direc decision mode comes afer he raining mode. To keep adapaion afer he raining sequence, dn in 5.13 direcly depends on he oupu of receiver, as d direc n in Figure 18, and hus, some errors can happen when d direc n is incorrecly esimaed. Bu in pracical ess, he BER is lower when having he direc decision mode as compared o no updaing during he daa mode. The block diagram of hese wo modes is depiced in Figure 18. IF signals Demodulaor rn Σ Equalizer d ˆ n d direc n AWGN Training sequence Σ dn Figure 18: The block diagram of raining racking equalizer. In he LMS equalizers, several imporan issues should be emphasized. Firsly, he vecor C mus be iniialized. Theoreically, i can be chosen arbirarily, bu in his projec, i is defined as an all zero vecor, since each iniializaion corresponds o a new ime slo. Secondly, when he ransmied signals are specified, he convergence speed only depends on he facor of µ given in 5.14 called sep size. The sep size needs o be well defined o fi he sysem requiremens. Oherwise, he LMS algorihm can be eiher unsable or converge very slowly. To preven he adapaion from becoming unsable, he value of µ mus saisfy [3]: < µ < 5.15 λ max where λ max is he larges eigenvalue of R rr. Thirdly, in his projec he equalizer is quie sensiive o he synchronizaion resul. When a raining sequence is used in he equalizaion, he synchronizaion of he raining sequence mus be 6

33 in a high level of accuracy. If no, he weighs of equalizer canno be rained sufficienly and may cause even more desrucive effecs o he received signals. b. RLS Algorihm LMS algorihm is a low cos compuaion mehod and easier o implemen in hardware. However, i usually needs ens or even hundreds of ieraions o converge. Someimes, his is unaccepably slow. Insead, RLS can give a higher convergence speed wih he rade off in compuaion complexiy. Iniialize C =, P = δi LL, where I LL is an L L ideniy marix, and δ is a large posiive consan, The RLS algorihm compuaion is hen described as follows [33]: Compue he filer oupu: ˆ T d n = C n 1 R n 5.16 Compue he error: L L e n = d n dˆ n 5.17 Compue he Kalman gain vecor and he inverse of correlaion marix: K L P n 1 R L n n = 5.18 T ω + R n P n 1 R n L L 1 T P n = [ P n 1 K L n R L n P n 1] ω 5.19 Updae he coefficien vecor of filer: C n = C n 1 + K n e n 5. L L L In 5.18, ω is he weighing facor ha can une he performance of he RLS equalizer. If he channel is ime invarian, ω can be se o one. Usually, i is in he range of.8, 1. The value of ω canno affec he convergence speed of he equalizer, bu can deermine he racking abiliy of he RLS equalizer [1]. When i is smaller, he racking abiliy is beer, bu a smaller value of ω leads higher noise sensiiviy. The convergence speed of LMS and RLS is illusraed in Figure 19. As menioned above, he convergence speed can be increased a lo by using RLS insead of LMS, bu he cos is much higher in erms of compuaion complexiy. 7

34 Figure 19: he convergence speed analysis of RLS and LMS. The compuaion complexiy of hese wo algorihms is lised in Table. Because of he huge compuaion cos of he RLS algorihm, i is no possible o implemen he RLS adapive equalizer on he FPGA developmen board given in his projec. Algorihm Compuaional Load Muliplicaion Division LMS L+1 - RLSKalman.5L +4.5L Table : The compuaion complexiy of LMS and RLS Nonlinear Equalizaion When he ISI is much more severe, he linear filer may no recover he disored signals very well, and a nonlinear equalizer can be an effecive mehod in his case. Two main ypes of nonlinear equalizers are described in his secion. One is decision feedback equalizer DFE and he oher is maximum likelihood sequence esimaor MLSE. a. Decision Feedback Equalizaion DFE The DFE equalizer consiss of a feedforward filer FFF wih he received symbols as is inpu and a feedback filer FBF wih he oupu deecor as is inpu. The srucure of DFE is shown in Figure. Once a symbol is deeced and decided, by using he feedback filer, he ISI i induces on fuure symbols can be subraced before he deecion of he coming symbols. 8

35 rn Feedforward Filer Σ d ˆ n Symbol by symbol deecion ~ d n Feedback Filer Figure : The srucure of DFE. The mahemaical expression of a DFE is given by following equaions: ~ d ˆ n = b d n l 5.1 L a + l= L1 + 1 l r n l l= 1 l where a l and b l denoes he coefficiens of FFF and FBF, respecively. Eiher ZF or MMSE crierion can be employed o design he feedforward filer. Moreover, he adapive mehods like LMS and RLS are also suiable for DFE. For insance, if LMS is employed, he compuaions of he DFE coefficiens are shown below [33]: Compue he error: e n = d n dˆ n 5. Updae he coefficiens of wo filers: a n = a n 1 + µ R n e 5.3 L1 L1 L1 n ~ b n = b n 1 + µ d n e 5.4 L L L n where an and bn is he weighs vecor of FFF and FBF a ime n, respecively. The subscrips of L1 and L are used o denoe he lengh of hese wo filers. Alhough he DFE equalizaion shows superior performance over he linear equalizaion, here are also defecs of he DFE equalizer. For example, once an error happens in he decision par, he inpu of he FBF is no he one as expeced, and he ISI effecs from previous symbols is wrongly esimaed, hen he error propagaion occurs. This will degrade he signal seriously. b. Maximum Likelihood Sequence Esimaor MLSE MLSE can avoid many problems in he equalizers discussed above. MLSE esimaes he ransmied signals according o he knowledge of he channel, which is differen from he equalizaion mehods discussed before. The srucure is he same as he upper plo of Figure 17, when replacing he equalizer block by a MLSE esimaion algorihm block. Usually, he Vierbi algorihm [17] is employed in he MLSE receiver. MLSE is he opimal receiver wih a sacrifice on he compuaion complexiy. The compuaion complexiy increases exponenially as he 9

36 number of signal saes increase. Hence, i is no considered in his projec. Figure 1 illusraes he BER by using differen equalizers. Figure 1: BER wih differen ype of equalizer. 5.4 Passband Equalizaion and Fracionally Spaced Equalizaion The equalizer does no only work wih baseband signals bu i can also be used wih passband signals. For example, passband equalizaion can be an effecive opion when he demodulaor inroduces some nonlinear effecs, which is relaively ough for he linear baseband equalizer o deal wih. Since he sampling rae of passband signals is greaer han he symbol rae according o he Nyquis crierion, an over-sampling equalizer, known as fracionally spaced equalizer FSE, is used for he passband equalizaion. The sampling rae is a leas as fas as he Nyquis rae. 3

37 6. Sysem Design and Simulaion Resul Analysis 6.1 Overview of he Design A sysem block diagram of he design is shown in Figure. The funcion of each componen is described in following secions. IF signals ADC BPF Demo Sync Equalizer Oupu Demodulaor Equalizer Figure : Sysem block diagram of non-coheren equalizer. 6. AD Conversion An FPGA works in digial world and he signals ransmied over air have o be analogue. So, an analog o digial converer is needed o conver he analog signals o digial bis. In order o ge idenical resuls beween he Modelsim and Malab simulaion, he daa used in Malab simulaions are also based on he oupu of he AD converer. The daa sampled from he AD converer is en bis; he Peak o Peak value of he ADC is V. I is a en bis quanizaion 1 levels o he raw analog daa. The sampled oupu from he oscilloscope is 1 bis wihin he range of -3768, 3767, so i needs o be rescaled. The analog daa, he sampled daa and he rescaled daa are shown in Figures

38 1 The ADC inpu ampliude of IF signals ime x 1-3 Figure 3: The IF signal before AD conversion. 4 x 14 Daa from oscilloscope 3 IF signals sampled from oscilloscope ime x 1-3 Figure 4: The oupu from he ADC sampled from he oscilloscope. 3

39 .8 IF signal afer downsampling and rescaling.6.4. ampliude ime x 1-3 Figure 5: The rescaled version of Figure Demodulaion Mehod Simulaion and Resul analysis The demodulaion srucure consiss of wo pars: an IF bandpass filer and a demodulaor. The funcion of each componen is lised below. IF bandpass filer: he inpu digial signals from he ADC conain boh high frequency noise and DC volage offse. Bu only he inermediae frequency signals are of ineres. An FIR bandpass filer is used o remove hese inerferences. Demodulaor: he demodulaor componen convers he IF signals o baseband. I basically consiss of one delay pah referred o as shif regisers in hardware, a muliplier and a lowpass filer. The incoming IF signals are firsly self-muliplied, which generaes mixed signals including boh he baseband componen and he high frequency componen. And hen he high frequency componen of he mixed signals is filered ou by a lowpass filer LPF. The demodulaion process is shown in Figure 3. In order o ge higher specrum efficiency, DECT uses GFSK as he modulaion scheme. The baseband digial pulse and he baseband Gaussian pulse are shown in Figures 6 and 7, respecively. 33

40 1.5 Transmied sequence a[n] 1 ransmied sequence ime.5 3 x 1-6 Figure 6: Digial NRZ sequence. 1.5 Daa afer Gaussian pulse shaping filer 1.5 Gassian pusle ime s x 1-6 Figure 7: Gaussian pulse sequence. The Gaussian pulse sequence is modulaed o passband afer he Gaussian pulse shaping filer. In he DECT sysem, he carrier frequency of he IF signals is 864 khz. The mahemaical expression of he modulaion is given by 6.1, where is used o denoe he coninuous ime due o he analog modulaion. Figure 8 shows a represenaive example of a GFSK modulaed signal. 34

41 s f N π d cos π f c + a n g v nt dv 6.1 T n= 1 = where f c is he carrier frequency, f d is he deviaion frequency and g is he Gaussian pulse. 1.5 GFSK modulaed signals 1.5 GFSK signals ime x 1-5 Figure 8: GFSK Modulaed signal wih modulaion index of.5. A quadraure deecor is used as he demodulaion scheme, which is a sandard choice. The coninuous ime block diagram is illusraed in Figure 9. Denoing he delay in erms of 9 degree phase shif by, m is given by 6.. y m LPF r 9 Figure 9: Block diagram of quadraure deecor in coninuous ime domain. 35

42 = + + = = dv nt v g a T f dv nt v g a T f f f f dv v g a T f f dv nt v g a T f f dv nt v g a T f f y y m n n d n n d c c c n d c n n d c n n d c cos 1/ cos 1/ cos cos π π π π π π π π π 6. Afer lowpass filering, only he firs erm in 6. is preserved. Le / π π = f c, hen he baseband componen of 6. reduces o: dv v g a T f dv v g a T f dv v g a T f dv v g a T f f n d n d n d n d c = + = + sin cos cos π π π π π π 6.3 The approximaion in 6.3 is based on he propery of 1 sin lim = x x x, so when x is relaively small, we have x x sin. If he inegraion inerval is relaively small, he resul of he inegraion is low enough o saisfy he propery menioned above. Thus, we can make he decision according o he sign of he demodulaor oupu. When i is negaive, he ransmied bi is 1, and vice versa. Two issues in he demodulaion should be noiced. One is calculaing he demodulaion delay The delay of and he oher is he design of LPF in he quadraure deecor / / T T f f c c = = = π π is given by 6.4 where T is he symbol duraion. In his projec, all signals are processed in he digial domain, so all signals denoed in Figure 9 should be discree, as shown in Figure 3 n is used o denoe discree ime index ha represens n = nt s, where T s =1/sampling frequency. According o he resul of 6.4, if he sampling rae of ADC is an ineger muliple of 3, he number of samples corresponding o is easy o define. In his projec, he sampling rae is predefined as 1368 khz which is 9 imes of he symbol rae. So he number of samples corresponding o is 3.

43 y ynt s mnt s rnt s LPF n =nt s 9 Figure 3: Block diagram of quadraure demodulaor in discree ime domain. As shown in Figures 9 and 3, he LPF is applied afer he muliply operaion. The cuoff frequency of he LPF is one of he main facors in he demodulaion. Usually, i is deermined by he 3 db law. Figure 31 shows he specrum of ynt s in he ideal channel. 5 Magniude Response db 4 Magniude db Normalized Frequency π rad/sample Figure 31: The specrum of IF signals ynt s. Figure 3 depics he specrum of he signal mnt s, which includes boh he baseband and passband componens. 37

44 Magniude Response db 5 4 Magniude db Normalized Frequency π rad/sample Figure 3: The specrum of mixed signal mnt s. According o he 3 db cuoff law, he firs rough of he specrum is he ideal poin for he cuoff frequency, which equals.15. Two kinds of window funcions, recangle and hamming, are esed in he filer design, and hey are shown in Figure 33. Ampliude Time domain Magniude db Frequency domain Samples Normalized Frequency π rad/sample Figure 33: Comparison beween a recangle window and a hamming window in boh ime domain lef and frequency domain righ. The FIR low pass filers consruced by hese wo windows are shown in Figures 34 and 35. Figure 34 shows he frequency response wih lengh of 3, and Figure 35 corresponds o he filer lengh of 64. When he filer lengh is 3, he LPF wih hamming window has beer sopband aenuaion bu a wider ransiion band, and he LPF wih recangle window is in conras o his. 38

45 When increasing he lengh o 64, he LPF wih hamming window can have a beer ransiion band, and here is almos no improvemen in he recangle filer s specrum. Therefore, he hamming LPF wih filer lengh of 64 is used in he demodulaion. Apparenly, he longer he filer, he higher he performance, bu he higher compuaion complexiy and longer delay will be inroduced. Magniude db Filer comparison wih lengh of 3 hamming recwin Normalized Frequency π rad/sample Phase degrees -5 recwin hamming Normalized Frequency π rad/sample Figure 34: FIR filer comparison wih lengh 3. 39

46 Magniude db Comparison beween wo filers wih lengh of 64 hamming recwin Normalized Frequency π rad/sample Phase degrees -5-1 recwin hamming Normalized Frequency π rad/sample Figure 35: FIR filer comparison wih lengh 64. All componens depiced in Figure 3 have been defined above, and Figure 36 shows he demodulaed resul of a noise free IF signal from an ideal channel. 1.5 Demodulaion Resul 1 demodulaed signals ime x 1-4 Figure 36: The demodulaed signal. Wihou aking he mulipah fading effecs ino consideraion, here are also some oher inerferences degrading he performance of demodulaion. In he ideal ADC, due o he idenical 4

47 direc curren DC offse of he differenial oupus, he DC offse can be removed afer subracion. However, in a pracical applicaion, he DC offse of he differenial IF signals will be dynamic wihin a small range, which is desrucive for he performance of he demodulaor. If here is an exra DC offse adding o he resul of 6.3, he decision is no only decided by he sign of he demodulaed resuls anymore. Therefore, a componen for removing he DC offse of he IF signals should be consruced prior o he demodulaor. Figure 37 shows he specrum of he IF signal ynt s wih DC offse. Magniude Response db Normalized Frequency π rad/sample Figure 37: The specrum of IF signals wih DC offse. Two mehods are esed o remove he DC offse. One is direcly subracing a consan value from he IF signals. By coninuous ess, The DC offse always flucuaes round.8. Afer subracing his consan value, he new DC offse could fall ino an accepable level, and he demodulaion is no so sensiive o his DC offse as before. Alhough he demodulaion performs beer by his mehod, i is sill a risk when he ADC is changed. Apparenly, i is unrealisic o measure and une ha consan value ime and again in a pracical implemenaion. A more common mehod for removing he offse is o filer ou he DC offse by eiher a high pass filer HPF or a bandpass filer BPF. A 18 order FIR ype of BPF is used in his projec, by which boh DC offse and he noise ouside he signal band is removed. Figure 38 shows he frequency response of his bandpass filer. 41

48 5 Bandpass Filer Magniude db Normalized Frequency π rad/sample Phase degrees Normalized Frequency π rad/sample Figure 38: The frequency response of he bandpass filer. Wih all componens discussed before, an enire srucure of he digial non-coheren demodulaor is available. Figures 39 and 4 depic he demodulaion resuls in he channel wih differen levels of fading. Since The GMSK modulaion is consan envelope modulaion, he envelope of he IF signals is kep consan in he normal channel, as shown in Figure 39. The demodulaed resul saisfies he BER requiremen. However, when he mulipah fading is severe, he envelope of he IF signal is no longer consan, as shown in Figure 4. Moreover, he BER is increased. The BER of he baseband signal in he lower plo of Figure 4 is higher han 5%, which degrades he audio qualiy significanly. Thus, equalizaion echniques should be used. 4

49 1 IF Signal in less fading channel ampliude ime x 1-4 Demodulaion Resul 4 ampliude ime x 1-4 Figure 39: Demodulaion resul wih less fading effecs. 1 IF Signal wih severe ISI ampliude ampliude ime x 1-4 Demodulaion Resul ime x 1-4 Figure 4: Demodulaion resul wih severe ISI effecs. 6.4 LMS Baseband Equalizer and Resul Analysis An LMS baseband equalizer as he core componen is buil ino he sysem due o is low cos in erms of implemenaion. Two componens are included in his block, namely: synchronizer and equalizer. A brief inroducion o each componen is lised below. 43

50 Synchronizer: his componen is used o deec where he sar of he raining sequence in each ime slo is, and hus enable he equalizer. Equalizer: as he essenial par of our design, he equalizer is designed as a fracionally spaced equalizer due o is less sensiiviy o he synchronizaion accuracy. When he synchronizaion componen finds he sar of raining sequence, he equalizer updaes is coefficiens according o he raining sequence in he raining mode, and hen keeps updaing according o direc decision. According o he sampling rae of he receiver, nine samples are used o represen one symbol, and he coefficiens are updaed every 9 samples, which mainains he saionariy of he LMS adapive filer Synchronizaion The firs 16 bis in he synchronizaion field of he daa package are used as he syncword and raining sequence, which are A maximum value can be found by aking he cross correlaion beween he demodulaed signals and he syncword, as shown in Figure 41. Since he equalizer is a fracionally spaced equalizer, he cross correlaion should also be aken in an oversampled mode. The ampliudes of he demodulaed signals are dynamic wih respec o he dynamic ampliude of he received IF signals. So, only he sign of each sample is reaed in he cross correlaion. As 1 symbol is represened by 9 samples, he ideal maximum value of he cross-correlaion is 7. Bu i seldom reaches his ideal value due o disorion. The peak value is mosly around 6 according o he resuls from a large amoun of simulaions, and a value of 55 is defined as he hreshold for searching for he peak. The synchronizaion will fail, if he peak is lower han 55, and he equalizer will no be acivaed. The synchronizaion error is wihin samples, which does no degrade he performance of he baseband equalizer Figure 41: The oupu of he synchronizaion componen cross correlaor. 44

51 6.4. LMS baseband Equalizaion Figure 4 illusraes he influence of severe mulipah fading. To eliminae his disorion, he baseband equalizer is cascaded wih he demodulaor. Due o he higher compuaion complexiy of he RLS algorihm, he LMS baseband equalizer will be discussed in his secion. The srucure is shown in Figure 18. The lengh of he equalizer depends on he lengh of he delay spread. Tha is o say, i depends on he number of symbols from he pas and fuure ha can affec he curren symbol. The maximum delay spread of channel model D and E is 5ns and 5ns, respecively, which is a mos /3 of one symbol duraion. The final lengh for he baseband equalizer is defined as 7. This corresponds o 3 imes he symbol duraion. As discussed before, LMS has a disadvanage of low convergence speed, and he lengh of he raining sequence 16 bis used in he equalizer is oo shor o learn he channel. To compensae for his problem, a large sep size is used in he equalizer. The value of.65 is seleced from he range.1,.3, according o simulaion resuls in Malab. In addiion, his value can be expressed as.1 in binary form, for which he muliplicaion in LMS algorihm can be replaced by a shif operaion 4 bis lef shif in he hardware implemenaion. Afer all facors of he LMS equalizer are defined, he equalizer works according o he principles given in In his projec, he signal o noise raio SNR is fixed. So, he SNR-BER plo canno be used o evaluae he performance of he equalizer. Insead, he hisogram of he baseband signals and insananeous BER are used. The following figures show he baseband equalizer performance wih differen ISI disorion. Figures 4-44 show ha when mulipah fading channel model D is no very severe, he equalizer can recover he daa correcly. The BER of he equalizer oupu is. The hisograms in Figure 44 illusrae ha when using he baseband equalizer, he baseband oupu is equally disribued around he decision level of. However, when he equalizer is no used, he baseband oupu is severely disored. 45

52 .8 IF Signal wih less fading.6.4. ampliude ime x 1-4 Figure 4: IF signal in a less severe fading channel. 1 Direc Demodulaion Resul ampliude -1 ampliude - 1 ime 3 4 x 1-4 Equalizaion Resul ime x 1-4 Figure 43: Comparison on baseband signal wih or wihou he baseband equalizer. 46

53 4 Performance of Direc Demodulaion 3 number Ampliude values for direc demodulaed baseband signals Performance of equalizaion 8 6 number Ampliude values for equalized baseband signals Figure 44: Hisogram comparison on he resuls of Figure 43. When he disorion is even worse, as shown in Figure 45, he BER of he baseband signals upper plo Figure 46 is 7.5% wihou using he equalizer. When he equalizer is used, he BER is six imes lower han before. The hisograms in Figure 47 also indicae ha some negaive symbols are inerfered o he posiive par when he equalizer is no used. 1 IF Signal wih severe fading ampliude ime x 1-4 Figure 45: IF signal in a severe mulipah fading channel model E. 47

54 Direc Demodulaion Resul ampliude 1 ampliude -1 1 ime 3 4 x 1-4 Equalizaion Resul ime x 1-4 Figure 46: The comparison beween wih and wihou he baseband equalizer. 3 Performance of Direc Demodulaion number Ampliude values for direc demodulaed baseband signals Performance of equalizaion 1 number Ampliude values for equalized baseband signals Figure 47: Hisogram comparison on he resuls of Figure

55 6.5 Limiaion of LMS Baseband Equalizaion for Non-coheren Demodulaion From he resuls of a large amoun of simulaions, we have found ha he baseband equalizer can only improve he performance o some exen. When he mulipah fading is paricularly severe, he desired daa canno be recovered from he demodulaed signals. Moreover, here are no peaks over he pre-defined hreshold of 55 in he synchronizaion process, as shown in he lower plo of Figure 48 channel model E. Therefore, he equalizer does no work in such cases. ampliude ampliude correlaion resul 1 IF Signal wih Severe Fading ime x 1-4 Direc Demodulaion Resul ime x 1-4 Oupu of Synchronizaion ime Figure 48: Resuls when severe ISI occurs. In order o check he performance of he LMS baseband equalizaion, he demodulaed signals are forced passing hrough he equalizer by finding he synchronizaion posiion manually. However, he resul is no good, as expeced. An analysis of his problem is presened as follows: Here we use coninuous ime signals o do he analysis. In he ideal channel, he noise-free IF signal is wrien as: [ ω + ] y = cos c ϕ 6.6 where ωc is he cener frequency of he carrier, informaion, and is used o denoe he coninuous ime. πf d ϕ = an g v nt dv is he T n 49

56 5 Figure 49: Two-ray channel model. When a -ray channel wih equal gain is used as he simulaion channel as in Figure 49, y can be wrien as: [ ] [ ] cos cos ϕ ω ϕ ω = A A y c c 6.7 The firs erm of 6.7 is he desired IF signals wihou any delay. The second erm is from he pah wih delay. In he receiver, we apply quadraure deecion shown in Figure 5 o demodulae he received signals. The demodulaion process of y can be wrien as , where LPF 9 y r m is used o denoe he delay corresponding o 9 roaion. Figure 5: Block diagram of demodulaion sysem. [ ] [ ] { } [ ] [ ] { } cos cos cos cos ϕ ω ϕ ω ϕ ω ϕ ω = = A A A A m y y m c c c c 6.8 Afer passing hough LPF, he baseband signal r can be wrien as: [ ] [ ] [ ] / cos / cos cos ϕ ϕ ω ϕ ϕ ω ϕ ϕ ω = A A A r c c c 6.9 Since π ω = c, 6.9 can be wrien as: [ ] [ ] [ ] / cos / cos sin ϕ ϕ ω ϕ ϕ ω ϕ ϕ = A A A r c c 6.1 If here is no mulipah fading, 6.1 only conains he firs erm. According o 6.3, he demodulaion resuls are decided by he sign of he firs erm. However, when mulipah fading exiss, he resuls will be inerfered by nonlinear effecs, as he second and he hird erms in

57 6.1, and his is non-negligible. So, when he fading is smaller, he nonlinear erms can be approximaed as a linear effec which can be effecively fixed by a linear equalizer. Bu, when he delay spread is longer, he linear baseband equalizer is no so effecive o solve he nonlinear inerference inroduced by he quadraure demodulaion. 51

58 7. Hardware Implemenaion and Verificaion 7.1 Exernal PCB Board Figure 51: Block diagram of exernal PCB. As has been shown in he sysem diagram, before he FPGA here is an exra board as in Figure 51 for convering he analog IF signal o digial form for digial signal processing wihin he FPGA. The analog IF inpu signal from he DECT sysem as shown in he above diagram is in he form of differenial signaling. Differenial signaling is a mehod of ransmiing informaion elecrically by means of wo complemenary signals sen on wo separae wires []. Due o is inheren resisance o exernal noise, differenial signaling is becoming popular in high speed daa acquisiion, and nowadays high speed and high accurae ADC s inpus are differenial. Therefore, o achieve he noise resisance of differenial signaling, fully differenial amplifier and differenial analog o digial converer are chosen for he analog o digial conversion Differenial amplifier A fully differenial amplifier is similar o a sandard volage feedback operaional amplifier, see Figure 5. Boh ypes of amplifier have differenial inpus. Bu fully differenial amplifiers have differenial oupus, while a sandard operaional amplifier s oupu is single ended. The oupu of a fully differenial amplifier can be conrolled by he oupu common mode volage Vocm, which could be conrolled independenly of he differenial inpu volage. The usage of Vocm inpu o he amplifier is o se he oupu common mode volage. There are several advanages by using a fully differenial amplifier: [3] 5

59 Figure 5: Fully differenial amplifier versus sandard operaional amplifier [3]. Increased noise immuniy: unavoidably, when signals are ransmied from one place o anoher, noise is coupled ino he wires. In a differenial sysem, keeping he wires as close as possible o one anoher makes he noise coupled ino he signals as a common mode volage. Since he differenial signaling rejecs common mode volages, he sysem is more immune o exernal noise [3]. Twice oupu volage swing: because of he change in phase beween he differenial oupus, he oupu volage swing increases by a facor of wo over he sandard single ended oupu wih he same volage swing. Figure 53 [3] illusraes his condiion, where Vod is he oupu volage, defined as: Vod = Vou+ Vou 7.1 Figure 53: Fully differenial amplifier has double oupu volage swing. Besides all menioned above, he fully differenial amplifier could reduce he even order harmonics and is ideal for low volage sysems, hanks o he increased oupu volage swing. In he applicaion of he fully differenial amplifier, here could be wo possible feedback pahs, one for each side. Figure 54 shows he mos ypical configuraion of a fully differenial amplifier wih negaive feedback o conrol he gain. In a real design, i is imporan o keep he wo pahs symmeric. If we define he differenial inpu as Vid and differenial oupu as Vod hen: 53

60 Vid = Vin+ Vin 7. Vod = Vou+ Vou 7.3 If he feedback loops are symmery, hen Vod = Vou+ Vou = A Vid 7.4 where A = Rf Rg Figure 54: Typical connecion of a fully differenial amplifier. In his projec, as he inpu range of he IF signal is from -.3 V o.3 V and he desired inpu range for he ADC is from -1 V o 1 V, Rfs are se o be 3.3 kω and Rgs o be 1 kω o have a 3 imes amplificaion Differenial ADC As he advanages of differenial signaling have been saed in previous pages, a differenial inpu ADC is chosen o be used in he exernal PCB. The pin allocaion is shown in Figure 55 [4]. 54

61 Figure 55: Pin allocaion of AD935. As we can see, here are 1 bis for digial oupus. Bu only he firs 1 bis are used in his design due o he limiaion of I/Os of he FPGA developmen board. Also, 1 bis resoluion has been proved o be sufficien according o Malab simulaion. The oupu code could be expressed by he following equaion [4]: n Vin+ Vin Digi = 7.5 V REF The pin funcion descripions are shown in Table 3 [4]. 55

62 Pin No. Mnemonic Descripion 1 OTR Ou-of-Range Indicaor. MODE Daa Forma and Clock Duy Cycle Sabilizer DCS Mode Selecion. 3 SENSE Reference Mode Selecion. 4 VREF Volage Reference Inpu/Oupu. 5 REFB Differenial Reference. 6 REFT Differenial Reference +. 7, 1 AVDD Analog Power Supply. 8, 11 AGND Analog Ground. 9 VIN+ Analog Inpu Pin +. 1 VIN Analog Inpu Pin. 13 CLK Clock Inpu Pin. 14 PDWN Power-Down Funcion Selecion Acive High. 15 o, 5 o D LSB o D11 Daa Oupu Bis. 8 MSB 3 DGND Digial Oupu Ground. 4 DRVDD Digial Oupu Driver Supply. Table 3: Pin funcion of AD935. The MODE pin is a muli level inpu ha conrols he daa forma and duy cycle sabilizer sae. The mode selecions are saed in Table 4. In his design, he MOED pin is conneced o /3 AVDD o ge a wo s complemen oupu and enabled duy cycle sabilizer. MODE Volage Daa Forma Duy Cycle Sabilizer AVDD Twos Complemen Disabled /3 AVDD Twos Complemen Enabled 1/3 AVDD Offse Binary Enabled AGND Defaul Offse Binary Disabled Table 4: MODE pin configuraion of AD935. SENSE pin is used o configure he reference volage ino one of he four possible saes which are shown in Table 5. To ge a sable inernal volage ladder and V peak-o-peak volage, where he inpu volage is from -1 o 1 V, he SENSE pin is conneced o ground o selec he Inernal Fixed Reference mode. 56

63 Seleced Mode SENSE Volage Inernal Swich Posiion Resuling VREF V Resuling Differenial Span V p-p Exernal Reference AVDD N/A N/A Exernal Reference Inernal Fixed VREF SENSE.5 1. Reference Programmable Reference. V o VREF SENSE R/R1 VREF See Figure 4 Inernal Fixed Reference AGND o. V Inernal Divider 1.. Table 5: SENSE and VRET pin configuraion of AD935. Furher, VREF is grounded, and CLK, as he clock inpu pin used as sampling frequency, is conneced o 1.368MHz which is aken from he DECT sysem o ge synchronized wih he sysem. Anoher reason of choosing 1.368MHz as sysem clock is ha i is easy o do he demodulaion. As has been shown in previous chapers, he demodulaion is o muliply he signal wih iself delayed. The demodulaion delay equals o 1/3 of he symbol period, while he clock frequency = 1.368MHz = 9/symbol period, which makes he demodulaion easy o implemen see equaion 6.4. The 1bis digial oupus are conneced o he FPGA board by using an I/O header. 7. FPGA Developmen Board The selecion of FPGA developmen board is narrowed down o Low Power Reference Plaform LPRP from Arrow Elecronics, Inc [5] because i was pre-purchased by he company and is powerfulness by means of FPGA device. This board conains of a low power Alera Cyclone III FPGA EP3C5, onboard baery for power supply, 1 user I/Os, an ADC and a DAC which was no used, wo clocks and several push buons and LEDs. 57

64 Figure 56: A layou of LPRP FPGA developmen board. Figure 56 shows he layou of he LPRP FPGA developmen board. I feaures he devices lised below [6]. The EP3C5 Cyclone III low cos and low power FPGA can be seen in he middle righ of he board, and is marked as U1 in he figure. This FPGA is used as he main processor in his design. I finishes he asks including filering, demodulaion, synchronizaion and equalizaion. This FPGA conains large amoun of resources, and is enough for a big DSP design and low power device which employs 65-nm processing. More feaures and resources of his Cyclone III FPGA are inroduced in laer pages. Power converers from Linear Technology, including he LT3455 which works as a power supply for all he componens. Cellular RAM, NOR Flash and removable SD memory devices ha could all be used as exernal memory. Bu since his design does need much memory resources, only he onboard memory of he FPGA is used such as he sorage of filer coefficiens. 1.1 inch monochrome grayscale display: his display could be used as an oupu of any signals and here is a sofware driver for his device from he board package. 58

65 Audio CODEC and headphone amplifier and ADC which have no been used in his design. Buons & LEDs: Several buons have been used, such as Rese, Sar, Mode Swich, ec. All LEDs have been used as indicaors. General Purpose I/O header: This I/O header has been used as he main inpu and oupu for he FPGA board including 1 bis inpu from he ADC, 1 MHz clock inpu and demodulaed daa oupu EP3C5 EP3C5 Cyclone III FPGA works as he main processor in his design, and i is in charge of mos of he digial signal processing and conrol asks. This Cyclone III chip feaures cos-opimized and memory-rich minimized power consumpion and is herefore ideal for wireless communicaion sysems. The device feaure of his FPGA has been shown in following Table 6 [7]. As we can see, i has rich resources and is sufficien for such a medium sized DSP and conrolling design. Alera supplies an embedded sof core soluion Nios, which enables a combinaion of VHDL design and C programming. Feaure EP3C5 Logic Elemens 4,64 Memory kb 594 Mulipliers 66 PLLS 4 Global Clock Neworks Table 6: Cyclone III FPGA feaures. 7.3 Basic DSP Arihmeic Implemenaion on FPGA Number Represenaion An ineger or fracion number could be represened by fixed poin or floaing poin form, and i is preferable o decide i in he early sage of he projec. Generally, fixed poin represenaion has higher speed and lower cos, while floaing poin implemenaion has higher dynamic range and no need for scaling which is more aracive for complex sysems. To decrease he use of he FPGA resource, we choose o use fixed poin represenaion in his design, which is also more suiable for FPGA. The daa processed by he FPGA, such as he inpu signal, he coefficiens of he filer and he oupu signal could be posiive or negaive. Accordingly, i is necessary o employ a signed number for expressing all he daa in FPGA. In signed sysem, he magniude and sign are represened by separae bis. The firs bi i.e. he MSB represens he sign and he remaining bis he magniude in his design. So a decimal number X represened by N bis in signed form is given by 59

66 X = N n x n n = N x n n = n X X < 7.6 where xn is he nh bi of he binary number x could be eiher or 1. The digi x is he leas significan bi LSB and he digi xn-1 is he mos significan bi MSB which represens he sign of number X. The dynamic range of his represenaion is [- N-1-1, N-1-1]. The advanage of his signed represenaion is simplified prevenion of overflows, bu he disadvanage is ha he addiion mus be spli depending on which operand is larger. Two s complemen represenaion is one of he signed represenaions and he mos popular signed numbering sysem for DSP use. This is because i is possible o add several signed numbers, and any overflow could be ignored as long as he sum is wihin N bis range. Furher, i is easy o do he subracion in his arihmeic operaion, where i is jus adding he invered subrahend number o he subrahend. Two s complemen numbers can also be used for N implemening modulo arihmeic operaion, which is useful for muliplicaion and division. A wo s complemen represenaion of a signed ineger is given by: X = N 1 N n x n X n = N n + x n n = X < 7.7 Plus, wo s complemen number is included in he VHDL and Verilog library which makes i easier o read and program Adder/Subracor Addiion and subracion is he mos common compuaion block for DSP applicaions such as filers. A basic N bis adder/subracor consiss of N full adders FA. A full adder can be expressed by he following Boolean equaions: SUM n = X n XOR Y n XOR C n 7.8 which define he sum bi and X and Y are he operand. The carry bi C can be expressed by: C n + 1 = X n AND Y n OR OR Y n AND C n X n AND C n 7.9 According o Alera EDA ool Quarus II 9. handbook [14], he synhesis ool could choose beween each srucure and find he mos suiable srucure o mee he iming and power requiremen. 6

67 7.3.3 Muliplier Muliplicaion is anoher widely used arihmeic operaion in DSP applicaions. Mos modern FPGAs have embedded muliplier blocks ha are opimized o suppor muliplier inensive applicaions such as FIR filers, FFT and encoders. These embedded mulipliers are dedicaedly designed for fas muliplicaion, resuling in efficien resource uilizaion, improved performance and daa hroughpu as compared o using logic blocks. Similarly o he laes device from Alera, Cyclone III devices offer up o 88 embedded muliplier blocks and suppors individual 18-bi 18-bi muliplicaions per block, or wo individual 9-bi 9-bi muliplicaions per block. Besides he embedded mulipliers, Cyclone III conains a combinaion of on chip resources and exernal inerfaces ha help increasing he performance, reduce sysem cos, and lower he power consumpion of digial signal processing. I focuses on opimizing he device for applicaions and benefis from an abundance of parallel processing resources, including video and image processing, inermediae frequency modems used in wireless communicaion sysems, and mulichannel communicaions and video sysems [7]. To infer he mulipliers for Alera devices, here is a buil-in library called Megafuncion in Quarus II sofware. From here, MegaWizard Plug-In Manager could help o creae he Megafuncions in he Quarus II GUI ha insaniae a muliplier. The MegaWizard Plug-In Manager provides a GUI o cusomize and parameerize Megafuncions, and ensures ha all Megafuncion parameers are properly configured [14]. The MegaWizard Plug-In Manager insaniaes he Megafuncion wih he correc parameers and generaes a Megafuncion variaion file in HDL. Besides, he synhesis ools will look for mulipliers and conver hem o Megafuncions, or may map hem direcly o buil-in mulipliers. 7.4 Band-Pass Filer and Lowpass Filer Afer he AD conversion, we found a big offse which is around.7v afer amplificaion in he real implemenaion. According o simulaion and real ess, his DC offse could affec he demodulaion very severely as discussed before. By analysis, i was defined ha his DC offse is from one of he differenial inpu signals, since he wo wires are no symmerical o each oher. To solve his, a band-pass filer was used o filer ou he DC offse as well as he ou of band noise. According o simulaion, a 18 order bandpass filer was implemened, as he DC offse could severely affec he performance. An FIR filer was chosen o implemen his band-pass filer as i has beer sabiliy properies han IIR filers. There are several srucures for FIR filer implemenaion as saed below: Finie Impulse Response filer basic srucure The L-order FIR filer wih an inpu of x[n] and oupu of y[n] is graphically inerpreed as in Figure

68 Figure 57: A srucure of FIR filer The filer consiss of a collecion of aps i.e. f[n], delay componens, adders and mulipliers. One of he operands o he mulipliers is he FIR coefficiens he aps, and he oher is he delayed inpu samples. To implemen his srucure wih a digial circui, L muliplicaions and L-1 addiions are needed. So o implemen a 64-ap s filer, which is quie common in real life, 64 mulipliers and 63 adders will be needed. An FIR filer, on he oher hand, is quie cosly in area and iming. Some opions o improve his srucure o reduce is complexiy are saed in following pars Transposed FIR filer An FIR filer model could also be expressed by anoher srucure as shown in Figure 58 [1]. Figure 58: Srucure of ransposed FIR filer. This srucure is derived from he sandard srucure of Figure 57 by exchanging he inpu and oupu; invering he direcion of signal flow; and by subsiuing an adder by a fork. This model is called he ransposed FIR filer. This srucure is he preferred implemenaion of an FIR filer. The advanage of his one over he previous one is ha an exra shif regiser for x[n] is no needed, and here is no need for an exra pipeline sage for he adder ree of he producs. Bu for his srucure, he number of muliplicaions and addiions is sill very high. 6

69 7.4.3 Symmeric FIR filers The cener of an FIR s impulse response is an imporan poin of symmery. Such a linear and ime invarian causal sysem as described above is a causal filer. This filer s oupu only depends on he pas and presen inpus. Since he linear phase filer coefficiens are symmerical or asymmerical, he number of he muliplicaions can be reduced by firs adding pairs of samples and hen perform he muliplicaion. Such a srucure can efficienly reduce he number of mulipliers L, as shown in Figure 59 [1]. This symmeric archiecure of FIR filer implemenaion has a muliplier budge per filer cycle exacly half of ha in he previous cases i.e. L versus L/, while he number of adders remains unchanged a L-1. Figure 59: Srucure of symmeric FIR filer. The coefficiens are generaed, for example, by using Malab s filer design ools. Since he coefficiens are symmeric, a symmeric FIR filer srucure as saed in he figure above is used o implemen his band-pass filer. Figure 6: Schemaic of a bandpass filer implemenaion. 63

70 A diagram of his pre-filer is shown in Figure 6. I has clock, rese, and sar as conrol inpus; and 1 bis inpu and oupu signals. The FIR filer has 18 coefficiens. CLOCK: sysem clock connecs o MHz. RESET: synchronous rese, reses he filer o an iniial sae where all delay pahs are se o zeros. START: if his inpu is acive, he filer will sop working and keep all he delayed inpus. IN, OUT: inpu, oupu signal of he filer. COEF: 18 coefficien inpus o he filer, each coefficien has 16 bis. This implemenaion of he symmeric FIR bandpass filer conains L/ mulipliers and L-1 adders, where L equals 18 in his case. The lowpass filer for demodulaion uses he same FIR srucure as he bandpass filer, bu wih a lower order of L=3. The filer coefficiens are generaed by Malab. 7.5 Demodulaion A non-coheren quadraure demodulaion scheme is chosen for implemenaion in his design. The quadraure demodulaor srucure is shown in Figure 61. As shown below, i is simple o implemen, as i only conains one muliplier and a delay pah for he down conversion pah, and a 3 order lowpass filer afer. yn mn LPF rn 9 Figure 61: Srucure of quadraure demodulaion. The symbol of his demodulaor is shown in Figure 6. I has clock, rese and sar for conrol inpus ha rese he demodulaor o an iniial sae and sop he demodulaor, 1 bis inpus and oupus, and 3 coefficiens inpus. 64

71 Figure 6: Symbol diagram of he demodulaor. 7.6 Synchronizaion To find he saring poin of he equalizaion, synchronizaion needs o be done based on he demodulaed signal. Every DECT slo conains 48 bis as shown in Figure 1. The firs 16 bis of he preamble consis of , which is used for clock recovery and frequency offse compensaion. The las 16 bi paern is he slo synchronizaion in he digial field. Despie is auocorrelaion funcion being far from opimum i is no a Dirac dela funcion, i is a reasonable choice for he synchronizaion purpose. Insead of aking an cross-correlaion by doing several muliplicaions, a simplified digi correlaion is used for synchronizaion. This mehod works like his: if he number in he paern in he synch word is 1 hen he corresponding posiioned number in he demodulaed digi is added o he sum value. On he oher hand, if he number in he paern is, hen he corresponding demodulaed digi is subraced from he sum value. The figure below shows resul of he digi correlaion beween he demodulaed resul and he synch word. As we can see, here is an obvious peak value in he beginning of he plo in Figure 63. By doing his, he ideal peak value is 7, because one symbol conains 9 samples and here are 8 imes of addiions according o he paern above. Based on a real es, we choose 55 as he synchronizaion hreshold. 65

72 Figure 63: Digi auocorrelaion of demodulaed signal and raining paern. Therefore, here is no need for muliplicaions in his synchronizaion, and only a sequence of accumulaors are needed o perform his ask. The symbol of synchronizaion is shown in Figure 64. The synchronizaion akes he demodulaed signal from he demodulaor as inpu, and oupus he synchronized indicaor. The synchronizaion indicaor will acivae if he synch word is found and i remains acivaed for one slo ime. Figure 64: Symbol diagram of synchronizaion. 7.7 LMS Equalizer The coefficiens of he filers saed above i.e. FIR filers or IIR filers do no change over ime. Bu in his projec, he channel slowly changes over ime. This requires ha he filer coefficiens are adjused over ime, depending on he inpu signal as he channel changes. Due o he adjusmen and updaing of he filer coefficiens, implemenaion of an adapive filer is much more complex han LTI filers. Bu recenly, journal publicaions such as IEEE Transacions on signal processing show he feasibiliy [8] and sabiliy of implemenaion of LMS filer in FPGA [9]. An LMS equalizer is used as a channel equalizer in his projec. Unlike fixed coefficien filers ha have fixed weighs or coefficiens, LMS equalizer needs an algorihm o updae he filer coefficiens. Among all kinds of adapive algorihms, he LMS algorihm is known for is simpliciy, and beer performance in differen running environmens [3]. On he oher hand, Recursive Leas Squares algorihm is anoher one widely used in adapive filer. Alhough RLS 66

73 algorihm has beer convergence speed, LMS requires much less compuaion complexiy as has been discussed in previous chapers. According o he LMS adapive updaing algorihm equaions , a possible implemenaion represened by a block diagram is shown in Figure 65 [1]. Figure 65: LMS equalizer implemenaion. This LMS algorihm implemenaion uses an FIR filer srucure. As shown in he figure above, he main componen of he filer consiss of L-1 delay componens, L coefficiens and coefficiens updae blocks, where L is he lengh of he equalizer. The delay regisers can be implemened by D Flip-Flops. The filer oupu y[n] is subraced from he desired signal d[n] o produce an error signal. The error signal is fed back o he weigh updaing componens o produce he nex ses of filer coefficiens. The weigh updaing componens perform logics calculaion according o he equaion. The operaions needed in he algorihm include wo muliplicaions and one addiion. The sep size parameer µ is a decimal number, and muliplying by a decimal number is equivalen of dividing by is reciprocal. Generally, implemenaion of division is a complicaed algorihm. In order o avoid implemening complicaed and area consuming division, or floaingpoin muliplicaion, arihmeic shif operaion can be used insead o simplify and shoren he mos criical pah of he design. The arihmeic shif operaion on a s complemen ineger shifs he number n bis o he righ, while preserving he sign bi he mos significan bi. By shifing he number n bis o he righ, i is equivalen o muliplying his number by -n. Therefore, in order o achieve simpliciy and feasibiliy, he muliplicaion by µ can be replaced by an arihmeic shif operaion if µ is resriced o be µ = -n, where n is a posiive ineger. How o choose he number of µ has been discussed in oher chapers. 67

74 Figure 66: Symbol diagram of he baseband equalizer. Afer he synchronizaion componen finds he beginning of he synch word, he LMS equalizer will be acivaed. This componen symbol as shown in Figure 66 akes a demodulaed signal wih he exac saring posiion of he raining sequence as inpu and updaes he coefficiens according o he adapive equaion. I has clock, rese and sar as conrol inpus, and sync o indicae he saring of equalizaion. Once he equalizer is acivaed, he equalizer will sar equalizaion which is divided ino wo modes. The equalizer sars updaing he coefficiens during he raining mode, which updaes according o he raining sequence ha is pre-sored and calculaes he error. Afer 144 clock cycles which are he lengh of he raining sequence period, he equalizer keeps updaing according o he decision direced feedback o calculae he error and coninues unil he end of one slo. The equalizer oupus he equalized decision digial daa. Figure 67: Criical pah of LMS equalizer. 68

75 The criical pah of he equalizer has been marked red in Figure 67, which includes one muliplier and L serial addiions, which can be quie a long pah for large values of L. This criical pah is oo long o mee he ime requiremen of MHz according o Quarus II synhesize resul. So, a regiser was insered in he middle of he accumulaor, where i is before he L/-1 adder. Tha is o say his equalizer is pipelined ino wo. Afer pipelining, here is no iming problem. 7.8 Resource Uilizaion Table 7 shows he resource uilizaion in FPGA. Logic Elemens Dedicaed Muliplier9 9 LMS Equalizer 136 4% 94 7% Demodulaor 981 3% 3 17% Synch 74 1% Pre-filer 195% 118% All % 11789% Table 7: Resource uilizaion of FPGA. The able shows he mos resource consuming componens in he FPGA when hey are synhesized separaely. The LMS equalizer uses a large number of embedded DSP componens. Bu according o a publicaion [3], he DSP componen uses could be halved by a improved srucure where his needs o be furher modified. As he pre-filer has quie a large number of coefficiens, i uses he mos resources in he design. Bu his could be decreased or removed by a modified exernal ADC board. Anoher issue ha needs some aenion in his able is ha he overall use of logic elemens are more han he sum up of all four componens. This is because he overall use of mulipliers is more han he FPGA has. So, half of he mulipliers have been implemened by logic elemens. Anoher big use of logic elemens, which has no been shown in he able, is he delay regisers used o compensae he filers delay and soring daa when he sysem is searching for he sync word. The lengh of his componen could vary as he equalizer and synchronizaion changes. 7.9 Simulaion and Verificaion The design has been simulaed by using Modelsim, and a screensho of he simulaion resul of he baseband equalizer in channel model E is shown in Figure 68. The Inpu_mp and correc are he signals sampled from a real es, and convered o binary forma by using Malab and read ino 69

76 esbench. Inpu_mp signal is he oupu from he ADC and correc is he ransmied daa. Equa_deci is he equalized signal afer decision making. Thus, he resul can be compared wih he ransmied daa. Bu his comparison canno be done auomaically in Modelsim due o small jiers beween he ransmied and received signals. This comparison was done in Malab insead. In he lower par of Figure 68, he equalized signal and error paern are shown. Afer he raining updaing, he baseband signal has been dragged close o 1 and -1, and he errors are close o zero excep some small gliches. Figure 68: Simulaion resuls in Modelsim channel model E. Tesbench based verificaion is used o verify he FPGA design. The erm esbench refers o some codes used o creae a pre-deermined inpu sequence o a design, and hen opionally observing he response [31]. Figure 69 shows a esbench wih a design under verificaion DUV. The esbench provides inpus o he design and checks he oupus. So for a esbench sysem, here is no inpu or oupu. Moreover, a esbench is no synhesizable and i is jus used for simulaions. Figure 69: General srucure for esbench based verificaion. 7