A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18µm Digital CMOS

Transcription

1 A 97mW 1MS/s 12b Ppelne ADC Implemented n 0.18µm Dgtal CMOS Terje N. Andersen, Atle Brskemyr, Frode Telsto, Johnny Bjornsen, Thomas E. Bonnerud, Bjornar Hernes, Oysten Moldsvor To cte ths verson: Terje N. Andersen, Atle Brskemyr, Frode Telsto, Johnny Bjornsen, Thomas E. Bonnerud, et al.. A 97mW 1MS/s 12b Ppelne ADC Implemented n 0.18µm Dgtal CMOS. EDAA - European desgn and Automaton Assocaton. DATE 05, Mar 2005, Munch, Germany. 3, pp , <hal > HAL Id: hal Submtted on 24 Oct 2007 HAL s a mult-dscplnary open access archve for the depost and dssemnaton of scentfc research documents, whether they are publshed or not. The documents may come from teachng and research nsttutons n France or abroad, or from publc or prvate research centers. L archve ouverte plurdscplnare HAL, est destnée au dépôt et à la dffuson de documents scentfques de nveau recherche, publés ou non, émanant des établssements d ensegnement et de recherche franças ou étrangers, des laboratores publcs ou prvés.

2 A 97mW 1MS/s 12b Ppelne ADC Implemented n 0.18µm Dgtal CMOS Terje N. Andersen, Atle Brskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øysten Moldsvor Nordc Semconductor, Trondhem, Norway Abstract A 12 bt Ppelne ADC fabrcated n a 0.18 m pure dgtal CMOS technology s presented. Its nomnal converson rate s 1MS/s and the nomnal supply voltage s 1.8V. The effectve number of bts s.4 when a MHz nput sgnal wth 2V P-P sgnal swng s appled. The occuped slcon area s 0.86mm 2 and the power consumpton equals 97mW. A swtched capactor bas current crcut scale the bas current automatcally wth the converson rate, whch gves scaleable power consumpton and full performance of the ADC from 20 to 1MS/s. v IN 1. Introducton D OUT CMOS technologes moves steadly towards fner geometres, whch provde hgher dgtal capacty, lower dynamc power consumpton and smaller area. Ths results n ntegraton of whole systems, or large parts of systems, on the same chp (System on Chp, SoC). For such systems the key parameters for the buldng blocks are often low power dsspaton and small slcon area. Analog to Dgtal Converters (ADC) are mportant buldng blocks n many of the SoC applcatons. Therefore, ADCs provded as Intellectual Property (IP) blocks goes nto a wde range of applcatons, spannng from magng to ultrasound and communcaton systems. Ths means that the ADC has to occupy small area and have low power dsspaton. Further, t has to be desgned n the same technology that the rest of the system. Ths means that the power supply voltage s low and subsequently the maxmum sgnal swng s lowered. Thus, t s necessary to keep the nose and dstorton of the ADC tself low. Addtonally, to mnmze the cost of the total SoC system, the IP block should be mplemented n a pure dgtal process, avodng use of costly addtonal analog process optons. Ths paper addresses these challenges by presentng a 12 bt ppelne ADC whch utlzes a 1.8V supply voltage and s fabrcated n a 0.18 m pure dgtal CMOS technology. In secton 2 the used ppelne archtecture s presented and secton 3 explans the desgn of some key buldng blocks of the ADC. Secton 4 presents the major measurement results, whle secton 5 concludes the paper. Proceedngs of the Desgn, Automaton and Test n Europe Conference and Exhbton (DATE 05) Fg. 1. The ppelne archtecture. 2. Ppelne Archtecture The ppelne chan s shown n Fg. 1. The chan conssts of succeedng 1.5bt stages and a 2bt flash at the end. The nput sgnal s appled drectly to the 1 st stage, whch also performs sample-and-hold. Due to the X2-gan n each stage, the 1 st stage has the hghest specfcatons wth respect to nose, ncomplete settlng and dstorton. Snce the nput swtches do not utlze bootstrappng, careful desgn of these s necessary to obtan low dstorton. Further, large samplng capactors (C H ) and hgh bas currents are necessary to keep the nose low and the ncomplete settlng wthn the specfcatons. Due to relaxed requrements of the stages along the ppelne chan these stages are scaled down regards to C H and bas currents [1]-[2], the 2 nd stage wth a factor 2/3 and the rest of the stages wth 1/3. Ths result n lower area and lower power consumpton wth only small degradaton n converter performance. The dgtal output of each stage s passed to a dgtal crcut, whch perform delay and error correcton before the dgtal value appears at the output D OUT. The error correcton utlzes the half bt of redundancy n each ppelne stage and corrects for errors n the Analog to Dgtal Sub- Converter (ADSC) contaned n the stage. The operaton of ADSC s further explaned n secton 3 together wth the rest of the stage archtecture. The reference voltages, Common-Mode (CM) voltages and the bas currents are suppled to the ppelne chan from on-chp crcutry. The reference voltages are

3 derved from the band-gap voltage and are decoupled by off-chp capactors. The bas current generator s a Swtched-Capactor (SC) crcut whch automatcally scale the bas currents to the stages wth the converson rate and the absolute value of an on-chp capactor. The SC bas current generator s also explaned n the next secton. 3. Desgn of Key Buldng Blocks The constructon of the ppelne stages s equal for all stages and s shown n Fg. 2 [1]. V INP -V INN s the nput sgnal for =1 and the resdue from the precedng stage for >1. The operaton of the stage can be dvded n two phases. In the trackng phase, V INP -V INN s appled over the samplng capactor C H, whch s the parallel connecton of the parastc metal capactors C 1 and C 2. When B goes down, the samplng swtch B opens and a sample of V INP -V INN s stored at C 1 and C 2. At the same tme V INP -V INN s also sampled by the ADSC. Further, goes down and goes hgh and the swtches are opened and S 2 are closed. The opamp, a two-stage Mller opamp wth a dfferental-par output stage [3], s now connected n closed loop and the stage s n ts amplfcaton phase. ADSC resolves the nput sample and pass ts dgtal value to the Decoder and Swtchng Block (DSB). Dependent on the dgtal value, DSB connects the reference voltages (V REFP and V REFN ) or the CM-voltage to the top of C 1 and the output V OUTP - V OUTN settles towards the resdue. The resdue s sampled by the followng stage at the end of the amplfcaton phase. At ths tme nstance, the dgtal output D OUT s vald and clocked n to the dgtal crcut. Because of the low supply voltage t was necessary to pay the swtches specal attenton. The transmsson gates and S 2 experence large voltage swngs. Ths results n large transstors to keep the onresstance of the transmsson gate low enough to fulfl the settlng requrements. It s especally the PMOS transstor that becomes large due to ts lower moblty compared to the NMOS. Therefore, both and S 2 use bulk swtchng of the PMOS transstor [1]. Ths means that when the swtch s on, the bulk (N-well) of the PMOS transstor s swtched to source. Ths results n lower threshold voltage and subsequently lower onresstance of the transstor. When the swtch s off, the bulk s connected to the postve supply voltage, ncreasng the off-resstance due to ncreased threshold voltage. The samplng swtch B s connected to V CM and does not experence large voltage swngs. Thus, B consst of NMOS transstors only, provdng low onresstance and small parastc capactances at the nputs of the opamp. To obtan low power consumpton and low slcon area several actons were taken. Frst, scalng of the ppelne stages reduce both area and power consumpton. Further, n ppelne converters t s common to use non-overlap clockng to ensure that the swtches S 2 s not closed before s opened. In ths desgn the non-overlap clockng s removed and the sequental operaton of the swtches s ensured by generatng these clocks locally n each stage, as Fg. 3 shows. Removng the non-overlap means that the stage has longer tme to settle and the gan-bandwdth of the opamp can be lowered, whch further results n lower power consumpton. In modern CMOS technologes the spread n the absolute value of capactors s large. Instead of large fxed bas currents n the opamp that can handle the largest possble capactve load, the bas currents n ths desgn are made dependent on the absolute value of the capactances. Fg. 3 shows the SC bas current generator. The OTA, whch s connected n unty gan, ensures that the voltage on ts output node BIAS s approxmately equal to V BIAS. V BIAS s taken from the band-gap voltage crcut and s near ndependent of varatons n process parameters, temperature and supply voltage. The current through the OTA output transstor M0 s set up by V BIAS and the load seen from the node BIAS to ground. Ths load s the equvalent resstance seen nto the SC-crcut. The SC-crcut s clocked by the system clock (CLK) at the converson rate frequency f CR. Further, the current through M0 s mrrored to I 1 BIAS to I BIAS, whch are appled to stage 1 to, respectvely. The value of these currents are gven by (1) (next page), whch shows that the bas current depends on the absolute value of the capactor C B. Thus, by ths technque the nomnal bas currents n the opamp can be set lower than n a conventonal desgn and the power consumpton s V BIAS V INP VREFP VREFN V CM S 2 C 1 C 2 V OUTP 1 I BIAS I BIAS B 1B VCM V OUTN C 1 C 2 V INN D OUT S 2 C B B B Fg. 2. The ppelne stage. Fg. 3. The SC-bas current crcut. Proceedngs of the Desgn, Automaton and Test n Europe Conference and Exhbton (DATE 05)

4 reduced. Further, (1) shows that the bas currents to the ppelne stages are also lnearly dependent on f CR. Ths means that the bas currents, and subsequently the power consumpton of the ADC, are automatcally scaled wth the appled clock frequency. Ths s an mportant feature n an ADC made as an IP-block due to the wde range of possble applcatons that ths block should ft n to. The effect of the power scalng versus converson rate s shown n the next secton. I C f V (1) BIAS B CR BIAS 4. Measurement Results Fg. 4 shows the power dsspaton of the ADC (exludng output drvers) versus converson rate. As predcted by (1) the bas currents, and subsequently the power dsspaton, s lnearly scaled versus converson rate. The plot shows a power dsspaton of 97mW at 1MS/s and 1mW at 130MS/s. The dynamc measurements were done by usng RF-sources for the nput sgnal and the clockng of the ADC. Both where fltered usng hgh order passve bandpass flters around the appled frequency to remove harmoncs and whte nose produced by the sources. Fg. 5 shows measurements of SNR, Sgnal-to-Nose-and- Dstorton Rato (SNDR) and Spurous-Free-Dynamc- Range (SFDR) versus converson rate. At 1MS/s, SNR and SNDR equal 67.1dB and 64.2dB, respectvely. Further, the plot shows that SNDR s above 64dB from 20MS/s up to 120MS/s and s above 62dB (equals effectve number of bts) up to 1MS/s. SFDR s above 69 db from 5MS/s up to 1MS/s. The sgnal frequency was MHz for these measurements. Fg. 6 shows measurements of SNR, SNDR and SFDR versus nput frequency at a converson rate of 1MS/s. SNR remans above 66dB up to 0MHz. Above 0MHz, jtter s the man nose contrbuton and SNR s fallng wth ncreasng nput frequency. SNDR s larger than db up to MHz and s thereafter fallng due to decreasng SFDR. The reason why SFDR, and subsequently SNDR, are fallng off at hgh nput frequences s the nonlnearty ntroduced by the nput swtches of the ADC. These swtches are transmsson gates where both the channel resstance and the parastc capactances are nonlnear. Ths problem can be solved by usng bootstrappng, but ths s not done n ths desgn due to potental lfetme ssues. The measurements presented n Fg. 5 and Fg. 6 are done wth sgnal ampltude near full scale (2V P-P ). In Fg. 7 (next page) the de photograph of the crcut s shown. The layout became compact due to many factors such as strappng the power routng n all metal layers, scalng the power routng for low-power areas and routng above actve area. The key measurement results are summarzed n Table I (next page). Addtonal nformaton here s that DNL and INL are ±1.2 LSB and -1.5/+1 LSB, respectvely, and the ADC slcon area s 0.86mm 2. Equaton (2) (next page) s the Fgure of Mert (FM) gven n [4] adjusted such that also the ADC area s Proceedngs of the Desgn, Automaton and Test n Europe Conference and Exhbton (DATE 05) Power Dsspaton (mw) db SFDR SNR SNDR Converson Rate (MS/s) Fg. 5. SFDR, SNR, and SNDR versus converson rate. The nput frequency and sgnal swng s MHz and 2V P-P, respectvely. db Converson Rate (MS/s) Fg. 4. Power dsspaton versus converson rate. The nput frequency and sgnal swng s MHz and 2V P-P, respectvely Input Frequency (MHz) SFDR SNR SNDR Fg. 6. SFDR, SNR and SNDR versus nput frequency. The converson rate and sgnal swng are 1MS/s and 2V P-P, respectvely.

5 000 Ppelne Chan CM-Voltage Fg. 7. De photograph. Delay and Correcton Logc SC-Bas Current Reference Voltage Buffer Bandgap Voltage 1MS/s Technology 0.18µm dgtal CMOS Nomnal supply voltage 1.8V Resoluton 12 bt Full Scale analog nput 2 V P-P Area 0.86 mm 2 Analog Power Consumpton 97 mw DNL ±1.2 LSB INL -1.5/+1 LSB SNR (f n =MHZ) 67.1 db SNDR (f n =MHZ) 64.2 db SFDR (f n =MHZ) 69.4 db ENOB (f n =MHZ).4 bt Table I. Key data for the proposed 12b ppelne ADC. ncluded. In (2) ENOB s the effectve number of bts of the ADC ncludng dstorton, f CR s the converson rate, A the ADC slcon area, and P SUP the power dsspaton. f 2 ENOB CR FM (2) A PSUP Fg. 8 shows FM (2) versus the nverse of the slcon area of 15 12b ADCs ncludng the ADC presented n ths paper (named Ths desgn ). The plot shows that ths desgn has the hghest FM and the 2 nd lowest area consumpton. Further, ths converter s the 2 nd publshed 12b ADC wth 1.8V supply voltage. The ADCs [5]-[7] are closest n FM and also area consumpton. The other ADCs n Fg. 8 are taken from IEEE Proc. of ISSCC and IEEE Symposum on VLSI Crcuts Dgest of Techncal Papers over the last 9 years. Fgure of Mert (FM) ,1 effectve number of bts s.4, the power consumpton s 97mW and the slcon area s 0.86mm 2. The ADC utlzes a SC bas current generator that scale the bas current, and subsequently the power consumpton, automatcally as a functon of the converson rate. Low area and low and scalable power dsspaton results n an ADC IP-block that s well suted for a wde range of applcaton n SoC systems. References Supply voltage=1.8v Supply voltage=[2.5v,2.7v] Supply voltage=[3v,3.3v] Supply voltage=5v Supply voltage=v 0,01 0, 1,00,00 1/A (mm^2) Fg. 8. Fgure of Mert (FM) versus 1/A for 12b ADCs. f CR s gven n MS/s, A s gven n mm 2 and P SUP s gven n mw. [1] B. Hernes, A. Brskemyr, T. N. Andersen, F. Telstø, T. E. Bonnerud, Ø. Moldsvor, A 1.2V 220MS/s b Ppelne ADC Implemented n 0.13µm Dgtal CMOS, Proc. of ISSCC2004, pp , [2] T. Byunghak Cho, P. R. Gray, A b, 20 Msample/s, 35 mw Ppelne A/D Converter, IEEE Journal of Sold-State Crcuts, Vol. 30, pp , March [3] D. Kelly, W. Yang, I. Mehr, M. Sayuk, L. Snger, A 3V 3mW 14b 75MSPS CMOS ADC wth 85dB SFDR at Nyqust, Proc. of ISSCC2001, pp. 134, [4] R. H. Walden, Analog-to-Dgtal Converter Survey and Analyss, IEEE Journal on Selected Areas n Communcatons, vol. 17, no. 4, pp , Aprl [5] A. Zjajo, H. Ploeg, M. Vertregt, "A 1.8V 12bts MSample/s Two-step ADC n 0.18-µm CMOS," Proc. of ESSCIRC2003, [6] S. Kulhall, V. Penkota, R. Asv, A 30mW 12b 21MSample/s Ppelned CMOS ADC, Proc. of ISSCC2002, [7] H. Ploeg, G. Hoogzaad, H. A. H. Termer, M. Vertregt, R. L. J. Roovers, A 2.5V 12b 54MSampel/s 0.25um CMOS ADC n 1mm 2, Proc. of ISSCC2001, Conclusons Ths paper presents a ppelne ADC wth 12 bts of resoluton and 1MS/s nomnal converson rate. The Proceedngs of the Desgn, Automaton and Test n Europe Conference and Exhbton (DATE 05)