SRAM Leakage Suppression by Minimizing Standby Supply Voltage

Transcription

1 SRAM Leakage Suppresson by Mnmzng Standby Supply Voltage Hufang Qn, Yu ao, Dejan Markovc, Andre Vladmrescu, and Jan Rabaey Department of EES, Unversty of alforna at Berkeley, Berkeley, A 947, USA Abstract Suppressng the leakage current n memores s crtcal n low-power desgn. By reducng the standby supply voltage ( ) to ts lmt, whch s the Data Retenton Voltage (DRV), leakage power can be substantally reduced. Ths paper lores how low DRV can be n a standard low leakage SRAM module and analyzes how DRV s affected by parameters such as process varatons, chp temperature, and transstor szng. An analytcal model for DRV as a functon of process and desgn parameters s presented, and forms the base for further desgn space loratons. Ths model s verfed usng smulatons as well as measurements from a 4KB SRAM chp n a.3µm technology. It s demonstrated that an SRAM cell state can be preserved at sub-3mv standby, wth more than 9% leakage power savngs.. Introducton One of the negatve sde effects of technology scalng s that leakage power of on-chp memory ncreases dramatcally and forms one of the man challenges n future systemon-a-chp (So) desgn. In battery-supported applcatons wth low duty-cycles, such as the Pco-Rado wreless sensor nodes [], cellular phones, or PDAs, leakage power can domnate system power consumpton and determne battery lfe. Therefore, an effcent memory leakage suppresson scheme s crtcal for the success of ultra low-power desgn. Varous technques have been proposed to reduce the SRAM sub-threshold leakage power. At the crcut level, dynamc control of transstor gate source and substrate source back bas were loted to create low leakage paths durng standby perods []. Yet these approaches requre many modfcatons on the SRAM cell structure, resultng n a large desgn and area overhead. Furthermore, the applcaton of reversed body bas exacerbates wthn-de varatons n threshold voltage. At the archtectural level, leakage reducton technques nclude gatng off the supply voltage ( ) of dle memory sectons, or puttng less frequently used sectons nto drowsy standby mode. These approaches loted the quadratc reducton of leakage power wth, and acheved optmal power-performance tradeoffs wth assstance of compler-level cache actvty analyss. The cache delay technque appled adaptve tmng polces n cache lne gatng, achevng 7% leakage savng at modest performance penalty [3]. To further lot leakage control on caches wth large utlzaton rato, the approach of drowsy caches allocated nactve cache lnes to a low-power mode, where was lowered but wth memory data preserved [4]. Whle the drowsy caches approach can acheve leakage energy savngs of over 7% n a data cache, the queston remans on the lower bound of standby that stll preserves data. Knowledge of the mnmum low-power mode supply voltage allows a desgner to lot the maxmum achevable leakage reducton for a gven technology. Understandngs of low voltage SRAM data preservaton behavor further open the opportunty for aggressve memory supply voltage mnmzaton, whch has been the bottleneck n VLSI system voltage scalng. Drven by the requrements of ultra low-power applcatons, ths paper presents the frst work on lorng the lmt of SRAM low voltage data preservaton under realstc condtons. In SRAM desgn, the Data Retenton Voltage (DRV) defnes the mnmum under whch the data n a memory unt s stll preserved. An analytcal model of DRV s developed to nvestgate the dependence of DRV on process and desgn parameters (Secton ). To verfy the new model and further understand the lmtatons of DRV under realstc condtons, a 4KB SRAM test chp wth dual-ral supply scheme was desgned and fabrcated n a.3µm technology, as ntroduced n Secton 3. Ths scheme targets ultra low-power applcatons and uses a customzed on-chp swtch capactor converter to generate standby. Secton 4 presents measurement results of the SRAM data preservaton and leakage suppresson. Impact of varous process and desgn factors on DRV s analyzed n Secton 5. Fnally, Secton 6 concludes current work and proposes future drectons.. Data retenton voltage analyss The crcut structure of a 6T SRAM cell s shown n Fg.. When s reduced to DRV, all sx transstors are n the sub-threshold (sub-v th ) regon, thus the capablty of SRAM data retenton strongly depends on the sub-v th current conducton behavor (.e., leakage). In order to understand M 5 Leakage current M V M M 3 V M 4 M 6 Leakage current Fgure. Standard 6T SRAM cell structure.

2 the low voltage data preservaton behavor of SRAM and the potental for leakage savng through mnmzng standby, analytcal models of SRAM DRV and cell leakage current are developed n ths secton. In a standard SRAM cell (Fg. ), when scales down to DRV, the voltage transfer curves (VT) of the nternal nverters degrade to such a level that nose margn of the SRAM cell degrades to zero, as llustrated n Fg.. Usng the notatons of Fg., ths condton s gven by: V V =, when VDD = DRV. () V V Left nverter Rght nverter If s further reduced below DRV, the nverters flp to the based state determned by the deterorated VT and lose the capablty to preserve the stored data. Based on ths observaton, the DRV of an SRAM cell can be determned by solvng the sub-v th VT equatons of the two nternal data holdng nverters, snce all the transstors conduct n weak nverson regon when s around DRV. The dervaton s presented below. When an SRAM cell (Fg. ) s n standby mode, the currents n each nternal nverter are balanced: Node V : I + I5 = I, () Node V : I + I = I. (3) Assumng that durng standby V and V, (4) and assumng that the bt-lnes are set to, I 6 s neglgble and Eq. (3) can be smplfed to: Node V : I = I. (5) 3 4 In Eqs. (, 3, 5), I s the conducton current of the th transstor (Fg. ) n the sub-v th regon. onsderng that I s domnated by the dran-source leakage n current technology (.e., gnorng gate leakage and other leakage mechansms whch have mnor effects compared to the sub-v th current), I s modeled as n [5]: Vth VGS VDS /( kt / q) I = S I ( e ) n kt q n kt q,(6) where S s the transstor (W/L) rato; I s a process-specfc current at V GS =V th for a transstor wth W/L=; T s the chp temperature; and n s the sub-v th factor, (sub-v th swng /6mV at room temperature). If we further defne: V (V) VT of SRAM cell nverters =.8V =.4V VT VT V (V) Fgure. Deteroraton of nverter VT under low-, wth zero SRAM cell nose margns at DRV. Vth A = S I, (7) n kt q I can be ressed as: VGS VDS /( kt / q) I = A ( e ) n kt q. (8) Substtutng these current models, whch are functons of V, V,, T, and other technology parameters, nto Eqs. (, 5), we obtan the VTs of the nverters n the cell. Then, together wth Eq. (), the value of the DRV (and the correspondng V and V ) can be derved. A general soluton to these equatons requres numercal teratons. To avod the teratons, we frst estmate the ntal value of DRV (DRV ), usng the approxmatons n Eq. (4): kt q ( ) ( ) = log A4 A5 A, (9) DRV n 3 n 4 n n3 A A3 n n + n where kt/q equals 6mV when T = 7. Then, usng DRV, the approxmatons n Eq. (4) are refned as: kt A + A5 DRV, () V = q A n kt q kt A 4 DRV. () V = DRV q A3 n3 kt q Wth Eqs. (-) avalable, we can refne the calculaton of DRV and a fnal resson s obtaned: V ( DRV V ) n DRV = DRV + +. () The above DRV formula only reles on the values of A and n, whch can be easly extracted from transstor characterzatons (ether by smulaton or measurement). In addton, t captures the dependence of DRV on process varatons n transstors, szng S, and chp temperature T. Based on Eqs. (7-), the mpact of these process and desgn factors on DRV can be formulated as: S DRV = DRV + a + b Vth + c T, (3) S where DRV s the nomnal value at room temperature; a, b, and c are fttng coeffcents. Wth the.3µm technology used and consderng an ndustral SRAM cell szed for optmal performance, the DRV formula predcts DRV = 77mV at perfect matchng and DRV = 69mV wth 3σ varatons n V th and channel length. These analytcal results match well wth SPIE smulated values of 78mV and 7mV, respectvely. The model coeffcents a s are extracted from smulatons: a = mv, a 3 = -4mV, a 4 = mv (a s neglgble); M M 3 5 M 4 Model 4 3 Wdth Scalng Factor Fgure 3. Modeled and smulated DRV as a functon of transstor wdth scalng.

3 b s about mv, dependng on bas condton. As demonstrated n Fg. 3, Eq. (3) fully captures the mpact of transstor szng on DRV. Due to the competng behavor of PMOS devces M and M 3, they have dfferent roles n state preservaton. Fg. 3 nfers that transstor szng s an effectve means n tunng the DRV of an SRAM cell, whch wll be further lored n Secton 5. Temperature coeffcent c s extracted as.69mv/, whch predcts an ncrease of.3mv n DRV when T rses from 7 to. Wth DRV obtaned, the total leakage of an SRAM cell n the sub-v th regon can be calculated as: I leak = I + I4 (4) V V = S n kt q kt q V DRV V + S 4 4 n kt q kt q where =I [-V th /(n kt/q)]; =.95µA and 4 = 6.78µA; DRV, V, and V are calculated from Eqs. (-3). Thus, the leakage power P leak under DRV s: Pleak = DRV I leak. (5) Leakage current I leak as provded n Eq. (4) represents the mnmum achevable leakage whle preservng state. 3. Ultra low voltage SRAM standby: Desgn and mplementaton To obtan slcon verfcaton of the presented DRV model and lore the potental of SRAM leakage suppresson wth ultra low standby, a 4KB SRAM test chp wth dual ral standby control was mplemented n a.3µm technology. Desgned for ultra low-power applcatons, ths scheme puts the entre SRAM nto deep sleep durng the system standby perod. As shown n Fg. 4, the SRAM supply ral are connected to the standard and the standby through two bg power swtches. A customzed on-chp S converter generates the standby wth hgh converson effcency. ompared to exstng SRAM leakage control technques, the smplcty of ths scheme leads to mnmzed desgn effort and maxmum leakage savng durng standby mode, whch s desred for battery-supported systems. 3.. Desgn consderatons 3... Standby stablty and nose margn analyss. In an actual mplementaton, reducng all the way down to the DRV s not really an opton, as other mechansms may St by 5: S onv 4k Bytes SRAM Fgure 4. Standby leakage suppresson scheme. dsrupt the state of the memory cell. More partcurly, these are the nose on the supply ral (mostly caused by the output voltage rpple of the swtched-capactor converter), as well as radaton partcles. To offset these effects, an approprate nose margn has to be provded. Smulaton shows that assgnng a guard band of mv above DRV for standby gves 6mV n SRAM cell Statc Nose Margn (SNM), and that the SNM degrades lnearly wth the guard band (becomng zero at the DRV). Here, the SNM s defned as the edge of the maxmum square that can ft nto the cross secton of the VT dagram of the cross-coupled nverters [6]. A guard band of mv over the DRV s suffcent to overcome the mv peak-to-peak rpple on the standby (wth worst case SNM of 55mV). The radaton partcle events pose a more serous hazard. Wth data storage node parastc capactance around ff n a.3µm technology SRAM cell, the crtcal charge (Q crtcal ) for a V s approxmately 3f. For a reduced at mv above the DRV, Q crtcal s reduced to.5f. To ensure relable state preservaton, future memores may have to add addtonal storage capactance [7]. Another opton to combat the effect of soft errors s to apply error-correcton schemes Dual voltage scheme desgn concerns. Man consderatons n a dual supply scheme nclude the operaton delay overhead due to the power swtch resstance, memory wake up delay and the power penalty durng mode transton. Targeted for ultra low-power applcatons, the system requrements of ths desgn are much more strngent on power than performance []. In such a stuaton the concern of the operaton delay overhead s not that crucal. A µm wde PMOS power swtch wth 3Ω conductng resstance s used to connect the memory module to a V operaton supply voltage. Wth the same swtch the memory wake up tme s smulated to be wthn ns, whch s typcally a small fracton of the target applcaton system cycle tme. The wake up power penalty ncurred durng swtchng from the standby mode to the full- mode determnes the mnmum standby tme for the scheme f net power savng over one standby perod are to be acheeved. Ths break-even tme s an mportant system-desgn parameter, as t helps the power control algorthm to decde when a power-down would be benefcal. Wth the parastc capactance nformaton attaned from process model, the mnmum standby tme n ths desgn s estmated to be around tens of mcroseconds, whch s much shorter than the typcal system dle tme n a battery-supported system. 3.. Test chp mplementaton Layout of the.3µm SRAM test chp s shown n Fg. 5. The two man components are a 4KB SRAM module and a Swtch apactor (S) converter. Ths memory s an IP module wth no modfcatons from ts orgnal desgn. As shown n Fg. 6, a representatve fve-stage step down dc-dc swtch capactor topology s selected to mplement the onchp standby generator [8]. ompared to magnetc-based voltage regulators, S converter provdes hgher effcency, smaller output current rpple, and easer on-chp ntegraton for small loads n the mcrowatt range. The desgn challenge

4 (a) (b) Fgure 5. A.3µm SRAM leakage-control test chp. (a) S onv desgn lk (b) Operaton phases lk Equalzng phase here resdes n handlng small output load n the range of ~µw. Wth such low power operaton, power loss ncurred by short-crcut currents durng phase swtchng becomes comparable to output power and forms a sgnfcant porton of total power loss. To maxmze power effcency, t s desrable to mnmze both the swtchng voltage drop and short-crcut current, whch have opposte dependence on devce szes. Hence the sze and type selecton of the swtch devces (.e., NMOS vs. PMOS) are carefully tuned to balance these two requrements. Fg. 6 shows the optmzed desgn, n whch an 85% converson effcency s acheved wth a V nput and an output load of estmated SRAM module leakage at standby mode. 4. Measurement results lk pf pf pf pf pf R mem (numbers ndcate transstor w dth n mcrons) R mem 4.. DRV measurement The DRV s measured by montorng the data retenton capablty of an SRAM cell wth dfferent values of standby, as demonstrated n Fg. 7. Wth swtchng between actve and standby modes, a specfc state s wrtten nto the SRAM cell under test at the end of each actve perod (t ), and then read out at the begnnng of the next actve perod (t ). Preservaton of the assgned logc state s observed when standby s hgher than DRV, whle the state s lost when standby s below DRV. The DRV was measured for 5 SRAM cells. Fgure 8 shows the dstrbuton of the total measurement results. The DRV values range from 8mV to 5mV wth the mean value of 7mV at an approxmately normal dstrbuton. Such a wde range of DRV uncertanty reflects the exstence V hargng phase R mem Fgure 6. (a) Schematc of swtch capactor converter, (b) Operaton phases. lk lk Hstogram Data Ponts 5 5 Data output SRAM supply t t t t End of State End of State standby restored standby restored Fgure 7. Waveform of DRV measurement. (a) DRV = 9mV n SRAM cell wth state, (b) DRV = 8mV n SRAM cell wth state. 5 5 Fgure 8. Dstrbuton of measured DRV data. of consderable process varatons durng fabrcaton. The 78 mv deal DRV, assumng perfect process matchng as obtaned by smulaton and analytcal modelng, shows up as the lower bound of the measured DRV dstrbuton. Wth msmatches ncluded, the measured mean value of 7mV matches the analytcal model wth 3σ varatons n V th and channel length. Moreover, temperature dependency of DRV was nvestgated wth measurement. When the test chp was heated up to, DRV was obtaned as 83mV, whch verfes the calculaton of 8mV by Eq. (3). As evaluated n Sec., our analytcal DRV model not only predcts the deal DRV values, but also fully captures the mpact of process and temperature varatons. Thus, t can serve as a convenent base for further desgn optmzatons. 4.. SRAM leakage measurement Leakage measurement result of the 4KB SRAM s shown n Fg. 9. It ncreases onentally when s hgh. Smlar as observed n the DRV measurement, ths phenomenon reflects the mpact of process varatons on SRAM leakage, more specfcally the fluctuatons n channel length and V th. For short channel transstors, dran-nduced-barrer-lowerng (DIBL) effect further causes severe V th degradaton, resultng n even hgher leakage n hgh- condtons. Furthermore, the shaded area n Fg. 9 ndcates the range of measured DRV (8-5mV). Whle the memory states can be preserved at sub-3mv, addng an extra guard band of mv to the standby enhances the nose robustness of

5 4KB SRAM Leakage urrent (µa) Measured DRV range Supply Voltage (V) Fgure 9. Measured SRAM leakage current. state preservaton as analyzed n secton 3... Wth the resultng 35mV standby, SRAM leakage current can stll be reduced by over 8%. Subsequently the leakage power, as the product of and leakage current, s effcently reduced by more than 9% Dual ral standby scheme measurement The dual ral scheme s shown to be fully functonal through the DRV measurements. Wth MHz swtch control sgnal, the S converter generates the standby wth less than mv peak-to-peak rpple. Wake up tme of ns s observed durng mode transton, whle the sleep tme spans around µs. Delay overhead durng actve operaton s measured to be about X, whch s reasonable for an ultra low-power applcaton where the system clock perod s typcally tmes the operaton cycle of a low leakage SRAM. 5. SRAM DRV mnmzaton: Analyss Whle SRAM desgns have been well optmzed for speed and power metrcs, mprovng DRV for future ultra low-voltage applcatons poses a new challenge for lowpower SRAM desgners. Results from prevous sectons have llustrated the mportance of process varatons, chp temperature, and transstor szng on DRV. A thorough understandng of ther mpacts on DRV and other performance metrcs provdes nsght nto SRAM cell desgn for ultra low-voltage and ultra low-power desgns. 5.. Process varatons and temperature mpacts Process varaton and temperature fluctuaton are the man mperfectons n a real envronment that cause degradatons n crcut performance. Fgure shows the smulated effect of these two parameters on SRAM DRV. Data shows that process varatons play a crtcal role n determnng DRV, whch ncreases by mv n the presence of 3σ msmatches n V th and channel length (L). On the other hand, temperature affects DRV n a less severe manner. When T changes from 7 to, DRV rses about 3mV, whch was verfed by test chp measurement. The dfference n process varaton and T effects on DRV s because fluctuaton n T affects all transstors n an SRAM cell unformly, whle local process varatons may change the drve strength rato between transstors, resultng n an exacerbated sub-v th VT msmatch and thus, a substantal DRV ncrement. Both effects are well captured by the analytcal models n Sec T = o T = 7 o ~3mV due to temperature fluctuaton ~mv due to process varaton (3σ) Process varaton (σ) Fgure. DRV under Process and T varatons. As observed from measurement and smulaton results n prevous sectons, mnmzng process varaton s the most effectve method to reduce DRV. Whle process varaton control becomes more dffcult n future technology nodes, t wll defne an effectve lower bound on SRAM. Another way to mprove data preservaton under low s to ensure low temperature operaton (e.g., at room temperature), whch s easer for ultra low-power applcatons. 5.. Szng optmzaton Whle szng has long been an effectve tool n conventonal power and speed optmzaton, takng DRV nto account further mproves future ultra low-power SRAM desgns. Ths secton presents DRV-aware SRAM cell optmzaton analyss based on transstor szng. Here, leakage power s consdered as the power metrc snce ths analyss targets ultra low-power desgn Read delay and area cost models. To facltate analytcal SRAM cell optmzaton, delay and area models as a functon of transstor szng are developed. In ths model, the SRAM access delay s consdered as the tme requred to pull down the bt-lne voltage by 5% of. Startng from a smple hand-calculaton model, a curve-fttng approach s used to develop a more accurate and scalable delay model as gven by analytcal dervaton: K SW + ( BL + K BL S ), (6) W tread = 3 K read A SW + B SW S N SW S N In ths model S W, represent the (W/L) rato of the wrte access transstor and the NMOS pull down transstor, respectvely, whle parameters K, K read, A, B, and are fttng parameters. They are related, but not equal to the followng physcal parameters: K read = kn ' V DSAT, VDD VthW, (7.a) A = VDD VDSAT VDSAT, VDD VthW VDSAT. (7.b) B = = ( VDD VthN ) VDD VDSAT Fttng parameters BL and K BL defne a relatonshp between the bt-lne capactance BL and the W/L rato S W of access transstors. The delay model fts smulated results as shown n Fg.. Due to a hgh layout densty of an SRAM, the SRAM cell area s smply modeled as a lnear functon of the total transstor area DRV mnmzaton. In conventonal performanceoptmzed SRAM cell desgn, the pull-down NMOS devces

6 t read (ns).5 =.6 =.4 =.77 =. =.48 Smulaton Model Wdth factor S W of access transstors Fgure. Read delay model fttng at = V. are szed substantally larger than the PMOS devces. Ths mbalance n the pull-up and pull-down paths leads to exacerbated VT deteroraton at low, and degrades DRV. It can be observed from Fg. 3 that by ether decreasng the NMOS sze or ncreasng the PMOS sze DRV can be effectvely reduced due to better balance n VT. Further takng delay and area costs nto account, NMOS tunng proves to be more desrable. Ths s because smaller NMOS mproves both DRV and area at certan delay penalty, whle larger PMOS only mproves DRV and pays large area cost, whch s ensve n memory desgn. SRAM cell optmzaton tradeoffs are shown n Fg., where the marked nomnal case s a commercal performance-optmzed cell desgn. Fg. a plots the lower bound on DRV for both 3σ process varaton (DRV = 7mV) and perfect matchng (DRV = 78mV) versus NMOS sze. In both cases DRV can be reduced by ~3mV at some delay penalty. Tradeoffs between delay, leakage power and area are llustrated n Fg. b. It can be observed that around the nomnal desgn pont, area s best traded off for performance. However, leakage power s then best traded for performance at delay of about % hgher than the nomnal pont, wth (a) nom nom p Lk / p Lk, Area / Area (b) 5 5 DRV =7mV (3σ varaton) DRV =78mV (no varaton) 3 4 nom /.5.5 p Lk ell Area DRV =7mV DRV =78mV nom t read / t read Fgure. SRAM cell desgn tradeoffs: (a) DRV vs. NMOS transstor sze, (b) Leakage power and area vs. read delay. area reduced at the same tme. Therefore, reducng sze of the cell both lowers the area and the leakage power at the ense of ncreased delay. At a 3% delay ncrease, a 5% leakage power reducton can be acheved. Furthermore, snce I leak s relatvely nsenstve to n the range around DRV as compared to hgh- condton (see Fg. ), there s only slght dfference n leakage power for the cases wth no process varaton and 3σ varaton. 6. onclusons and future work Ths paper lores the lmt of SRAM data preservaton under ultra-low standby. An analytcal model of the SRAM DRV s developed and verfed wth measurement results. A commercal SRAM module wth hgh-v th process s shown to be capable of sub-3mv standby data preservaton. Under ths low standby, leakage power savng of more than 9% can be acheved wth a dual-ral standby scheme desgned for ultra low-power applcatons. The DRV s observed to be a strong functon of process varaton and SRAM cell szng, whle the desgn tradeoffs between read delay, area and leakage power can be optmzed. Whle exstng approaches generally nvolve sgnfcant tradeoffs wth other performance metrcs or technology lmts, more opportuntes exst on archtectural level nnovatons. As an example, more SRAM leakage savngs can be acheved wth assstance from error tolerant schemes when the standby supply voltage s scaled down beyond the lmt of DRV. Future work wll be focused on lotng desgn technques to acheve even lower power and hgher relablty n memory desgn. Acknowledgements The sponsorshp of the GSR MARO center and fabrcaton support from ST Mcroelectroncs are greatly acknowledged. The authors would also lke to thank to Professor Seth Sanders and Dr. Bhusan Gupta for ther enlghtenng techncal advce. References [] J. Rabaey et al, PcoRados for Wreless Sensor Networks: The Next hallenge n Ultra-Low-Power Desgn, Proc. of ISS, pp. -, Feb. [] K. Itoh, Low Voltage Memores for Power-Aware Systems, Proc. ISLPED, pp. -6, Aug.. [3] S. Kaxras, Z. Hu, and M. Martonos, ache decay: Explotng generatonal behavor to reduce cache leakage power, Proc. of ISA, pp. 4-5, Jun-Jul. [4] K. Flautner et al, Drowsy caches: smple technques for reducng leakage power, Proc. of ISA, pp , May. [5] J. Rabaey, A. handrakasan, and B. Nkolc, Dgtal Integrated rcuts: A Desgn Perspectve, nd edton, Prentce-Hall. [6] E. Seevnck, F. J. Lst, and J. Lohstroh, Statc-nose margn analyss of MOS SRAM cells, IEEE J. Sold-State rcuts, vol. S-, No. 5, pp , Oct [7]. Lage et al., Soft error rate and stored charge requrements n advanced hgh-densty SRAMs, Proc. of IEDM, pp. 8-84, Dec.993. [8] K.D.T. Ngo and R. Webster, Steady-state analyss and desgn of a swtched-capactor D-D converter, Proc. of PES, pp , Jun-Jul 99.