Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

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1 21st Internatonal Conference on VLSI Desgn Total Power Mnmzaton n Gltch-Free CMOS Crcuts Consderng Process Varaton Yuanln Lu * Intel Corporaton Folsom, CA 95630, USA yuanln.lu@ntel.com Abstract Compared to subthreshold age, dynamc power s normally much less senstve to the process varaton due to ts approxmately lnear relaton to the process parameters. However, the average dynamc power of a crcut optmzed by determnstc gltch elmnaton (usng hazard flterng and path balancng) ncreases because gltches randomly start reappearng under the nfluence of process varaton. Combnng exstng technques, we propose a new statstcal mxed nteger lnear programmng (MILP) formulaton, whch combnes gltch elmnaton and dual-threshold desgn to statstcally mnmze the total power n a gltch-free crcut under process varaton. 1. Introducton Wth the contnuous ncrease of the densty and performance of ntegrated crcuts due to the scalng down of the CMOS technology, reducng power dsspaton becomes a serous problem that every crcut desgner has to face. At the same tme, the ncrease n varablty of several key process parameters can sgnfcantly affect the desgn and optmzaton of low power crcuts n the nanometer regme [1-3]. Due to the exponental relaton of age current wth some process parameters, such as the effectve gate length, oxde thckness and dopng concentraton, process varatons can cause a sgnfcant ncrease n the age current. To mnmze the effect of process varaton, some technques [1-3] statstcally optmze the age power and crcut performance by dual-v th assgnment. Leakage current and delay are treated as random varables. A dynamc programmng approach for age optmzaton by dual- V th assgnment has been proposed [2] usng two prunng crtera that stochastcally dentfy pareto-optmal solutons and prune the sub-optmal ones. Another approach [1] solves the statstcal age mnmzaton problem by a theoretcally rgorous formulaton for dual- V th assgnment and gate szng. Gltches are unnecessary sgnal transtons that account for 20%-70% of the dynamc swtchng power [4]. To elmnate gltches, we combne the technques of *Formerly wth Department of Electrcal and Computer Engneerng, Auburn Unversty, Auburn, AL 36849, USA. Vshwan D. Agrawal Auburn Unversty Auburn, AL 36849, USA vagrawal@eng.auburn.edu hazard flterng [5, 8-12] and path balancng [6, 8, 11], referred to n ths paper as gltch elmnaton. Compared to age power, dynamc power s normally much less senstve to the process varaton because of ts approxmately lnear dependency on the process parameters. However, any determnstc gltch elmnaton technque becomes less effectve under process varaton, snce the perfect hazard flterng condtons can be easly corrupted even wth a small varaton n some process parameters. Hu and Agrawal [13-14] proposed a technque to elmnate gltches under process varaton. However, performance s sacrfced to obtan a process-varatonresstant crcut, and the effect of process varaton on age power s not consdered. Our work s motvated by the above research. To mnmze the age power, we use a mxed nteger lnear programmng (MILP) model to determne the optmal assgnment of V th whle controllng any reducton n performance. To elmnate the gltch power, addtonal MILP constrants determne the postons and values of the delay elements to be nserted to balance path delays. Statstcal delay and age models are further adopted to reduce the total power n gltch-free crcuts consderng process varaton. 2. Background Lu and Agrawal [17] propose a statstcal MILP formulaton to mnmze the mpact of process varaton on the subthreshold age. In ths secton, we extend that dscusson to study the mpact of process varaton on dynamc power. Dynamc power comprses of two parts, logc swtchng power and gltch power: 1 2 Pdyn = CLV A F 2 = Logc swtchng power + Gltch power (1) where A s swtchng actvty and F s the crcut operatng frequency. Logc swtchng power s drectly proportonal to the loadng capactances, C L, whch lnearly depends upon gate szes, gate wdth and gate length. Local (ntra-de) process varaton causes gate szes to vary randomly and hence does not affect logc swtchng power too much. Global (nter-de) process varaton changes gate szes n smlar ways and does vary the logc swtchng power. Ths /08 $ IEEE DOI /VLSI

2 also does not affect the soluton of our MILP formulaton, snce gate delays and gate szes n the MILP constrants ether ncrease or decrease by the same percentage when global process varaton s consdered, and T max (crtcal path delay that affects the crcut performance) s assumed to change accordngly [15]. The mpact of process varaton on gltch power s dfferent and more complcated. Gltches are generated f the gltch flterng condton (2) [6] s not satsfed for cell. Snce nertal gate delays d vary wth process varatons, nequalty (2) may not be satsfed. d > T t (2) Where T t s the dfferental path delay at gate. We consder the mpact of global process varaton and local process varaton on gltch power, separately. Impact of global process varaton on gltches For every gate, the tmng wndow T - t s actually determned by two tmng paths, the fastest path (FPath) and the slowest path (SPath) from prmary nputs to gate. T s the cumulatve nertal gate delay along the slowest path, and t s the cumulatve nertal gate delay along that fastest path. Thus, m m SPath T t = d d (3) n n FPath Assumng that there s r 100% (r: 0~1) of global varaton appled to the crcut, gltch flterng condton (2) for gate remans unchanged snce both tmng wndow, T t, and gate delay vary by r 100%. Therefore, the technque of gltch elmnaton s resstant to the global process varaton. Impact of local process varaton on gltches Let us consder the mpact of local process varaton on gltch elmnaton. When local varatons occur n a crcut, T and t are the sum of gate delays, whch vary randomly, along the slowest and fastest paths from prmary nputs to cell s nputs, so, T - t s not very senstve to process varatons, whle d does change wth the process varaton. Therefore, t s very possble that the orgnal gltch flterng condtons (2) can not be satsfed n the presence of local process varaton. As shown n Fgure 1, there are three possble gltch flterng condtons. Both Fgures 1(b) and 1(c) are gltch free whle Fgure 1(a) has a gltch. In an un-optmzed crcut (wth gltches), Fgures 1(a) or 1(b) s represents a much more common condton for a gate. Although the condton of Fgure 1(c) s stll possble t has lower possblty. On the contrary, n an optmzed gltch-free crcut, Fgure 1(c) apples to many gates because Fgure 1(a) s always forced to become Fgure 1(c) by path balancng for gltch elmnaton. Wth local process varaton, Fgures 2(a) and 2(b) show that the orgnal condton s not so easly corrupted f only the varaton of the tmng wndow or the gate delay falls nto the shaded areas, whle Fgure 2(c) s extremely senstve to the local process varaton, snce a slght ncrease n the tmng wndow or decrease n the gate delay can smply let an orgnal gltch-free gate generate gltches at ts output. Fgure 1. Three possble gltch elmnaton condtons. Fgure 2. Three gltch elmnaton condtons under local process varaton. Ths explans why the dynamc power of an un-optmzed crcut s much more resstant to local process varaton than that of an optmzed gltch-free crcut. The gltch elmnaton condton shown n Fgure 1(c) cannot be really satsfed even wth qute small process varaton. Probablty d T t (a) Gltches generated d T t (a) Gltches generated Normalzed Dynamc Power 10% delay varaton 20% delay varaton 30% delay varaton Fgure 3. Normalzed dynamc power dstrbuton of unoptmzed (wth -gltches) C432 under local delay varaton. Fgure 3 demonstrates the resstance of un-optmzed crcuts to the local process varaton. We appled 10%, 20% and 30% local delay varatons, as may be caused by varatons n gate-length-ndependent V th, to an unoptmzed (wth-gltch) verson of crcut C432. The largest percentage of the mean value devated from the nomnal d T t (b) Gltch-free d T t (b) Gltch-free d T t (c) Gltch-free d T t (c) Gltch-free

3 value s 0.22% and the maxmum spread, 3 standard devaton / mean, s only 4.5%. The senstvty of optmzed gltch-free crcuts to local process varaton s llustrated n Fgure 4. Both mean value and standard devaton of dynamc power dstrbuton ncrease sgnfcantly wth the ncrease of the local process varaton. When 30% local varaton was appled to the optmzed gltch-free C432, ts average dynamc power ncreased by 32% and almost became equal to the normalzed dynamc power (1.34) of the unoptmzed C432. In Fgure 4, some samples of optmzed C432 have dynamc power even larger than We also note that every sample n Fgure 4 consumes more than the nomnal value, 1, whch s the expected mnmumnormalzed-dynamc-power of the optmzed gltch-free C432. Process varaton causes some gltches to be generated n the gltch-free crcut and hence ncreases the dynamc power. Probablty Normalzed Dyanmc Power 10% delay varaton 20% delay varaton 30% delay varaton Fgure 4. Normalzed dynamc power dstrbuton of optmzed (gltch-free) C432 under local delay varaton. It s remarkable that the advantage of gltch elmnaton s totally lost due to the local process varaton. Hence, the determnstc approach of gltch elmnaton s not useful for power optmzaton wth process varaton. In the followng secton, we combne the MILP formulatons ntroduced n [15-17], and thus a new statstcal MILP formulaton s proposed to optmze total power under process varaton and to fully utlze the advantage of the gltch elmnaton procedure. The determnstc MILP [15-16] usng gltch elmnaton and dual-v th assgnment to reduce the total power consumpton s a prerequste procedure, whch s modfed to consder process varaton. 3.1 Varables Integer varables: In our cell lbrary, each standard cell has two possble threshold voltages and three alternatve szes (1X, 2X and 4X). Therefore, ths MILP has sx nteger varables to allow alternatve choces. The varables are denoted as, X1L[, X2L[, X4L[, X1H[, X2H[, X4H[ Contnuous Varables: δ[ - relaxed varable for the gltch flterng constrant of cell. It wll be dscussed n Secton 3.3. Sze[ - sze of cell. I [ - nomnal value of age of cell. u_d[ - mean of nertal gate delay of cell. s_d[ - standard devaton of nertal gate delay. u_t[ - mean of T[. s_t[ - standard devaton of T[. u_t[ - mean of t[. s_t[ - standard devaton of t[. u_δd[,j] - mean of Δd[,j] (the delay of the nserted delay element). s_δd[,j] - standard devaton of Δd[,j]. 3.2 Constants σ r - standard devaton of the process parameter varatons. T max - the maxmum expected crcut performance. S X2 [ - gate sze of cell wth 2X drvng strength. W 1, W 2,W 3 - weght factors. I X2L [, I X2H [ - nomnal values of the subthrehold age of cell wth 2X drvng strength. D X1L [, D X2L [, D X4L [, D X1H [, D X2H [, D X4H [ - nomnal values of the nertal gate delay of cell at all sx corners. 3.3 Constrants Basc constrants Let LP solver choose one and only one optmal verson for cell. X 1 L[ + X 2L[ + X 4L[ + X1H[ + X 2H[ + X 4H[ = 1 (4) 3. Statstcal MILP for Total Power Optmzaton wth Process Varaton In the statstcal MILP formulaton, we treat all gate delays and tmng wndow varables as random varables wth normal dstrbuton whose standard devaton s σ r. Nomnal value of the subthreshold age of cell : I [ = (0.5 X1L[ + X 2L[ + 2 X 4L[ ) I X 2L[ + (0.5 X1H[ + X 2H[ + 2 X 4H[ ) I [] X 2H Mean and standard devaton of the gate delay of cell : (5)

4 u _ D [] = DX 1L[] X1L[ + DX 2L[] X 2L[ + DX 4L[] X 4L[ + D [] X1H[ + D [] X 2H[ + D [] X 4H[ X 2L [] u D[] X 2L X 4L s _ D = σ r _ (7) The sze of cell : 0.5 ( X1L[ + X1H[ ) + ( X 2L[ + X 2H[ ) + Sze[] = S X 2[] 2 ( X 4L[ + X 4H[ ) (8) For gltch elmnaton Instead of usng nequalty (2), n the statstcal method, we adopt the followng gltch flterng constrant: u _ D[] 3 s _ D[ ( u _ T[ + 3 s _ T[ ) ( u _ t[ 3 s _ t[ ) (9) Ths constrant can leave certan margn for process varaton n advance as shown n Fgure 2(b) nstead of Fgure 2(c). However, normally the above worst case constrant s too tght to make CPLEX LP solver fnd a feasble soluton. So, we add one nonnegatve relaxed varable δ[ to each gltch flterng constrant (9). δ[ ] + ( u _ D[] 3 s _ D[ ) ( u _ T[ + 3 s _ T[ ) ( u _ t[ 3 s _ t[ ) (6) (10) In the objectve functon, by mnmzng Σδ[, CPLEX LP solver wll try to fnd one optmal soluton to make as many of the constrants (10) satsfed as possble wth a zero δ[, whch means the gltches of correspondng cells can be truly elmnated even n the worst case condton of process varaton. Those constrants only beng satsfed wth the help of a postve δ[ qute lkely fal to flter gltches. For maxmal performance To keep the maxmal performance, at every prmary output k, let, u _ T[ k] + 3 s _ T[ k] T. (11) 3.4 Objectve functon max The objectve functon mnmzes the mpact of process varaton on the total power consumpton: Mn {the mpact of process varaton on the total power consumpton} = Mn {mean and standard devaton of age power + mean and standard devaton of dynamc power} W1 C1 I [] + (12) = Mn W [] [ ] 2 C2 sze + C3 μ _ Δd, j + j W 3 δ [ C 1, C 2 and C 3 are fttng parameters to let three terms (C 1 ΣI [, C 2 Σsze[ and C 3 ΣΣu_Δd[,j]) have the same unts (μw). The mpact of process varaton on both mean and standard devaton of the power consumpton should be consdered. For age, a smaller mean value automatcally mples a narrower spread of age power dstrbuton snce more gates are assgned hgh V th. Mn(C 1 ΣI [) should be enough to mnmze the mpact of process varaton on the total subthreshold age. For the dynamc power, standard devaton of the dynamc power dstrbuton s determned by Σδ[, and (C 2 Σsze[+C 3 ΣΣu_Δd[,j]) affects the average dynamc power. Therefore, we should mnmze (C 2 Σsze[+C 3 ΣΣ u_δd[,j]) and Σδ[, smultaneously. The objectve functon (12) s composed of three parts (three sngle objectves), namely, mnmze the average age power, mnmze the average dynamc power and mnmze the standard devaton of the dynamc power. It s a mult-objectve functon n whch ndvdual objectves conflct. For nstance, mnmzaton of Σδ[ results n an ncrease of ΣΣu_Δd[,j], and optmzaton of ΣI [ leads to a larger Σsze[, etc. It s not easy to get one optmum value for every sngle objectve. What we can do nstnctvely s to carefully select weght factors, W 1, W 2 and W 3 to make a tradeoff among the three objectves. It should be notced that the soluton provded by a determnstc MILP [15-16] gves us a rough dea of whch one s the domnant component between age and dynamc power. We also get ther exact optmal values (power consumpton) for the optmzed crcut. Based on that nformaton, we can choose weght factors and add some emprcal constrants on the largest allowable mnmal age or dynamc power n the statstcal MILP formulaton. The choce of mnmzng the mpact of process varaton ether on age or on dynamc power depends on whch one s the domnant power consumer, and the crcut applcatons as well. For a crcut optmzed by the determnstc MILP, we consder: Case 1 - f the optmal age s much less than the optmal dynamc power and ts large spread due to process varaton (for example, 5X dfference under 30% global process varaton ) can stll be gnored, we need put much more emphass on dynamc power changes beng resstant to process varaton; Case 2 - f the optmal age s comparable to the optmal dynamc power, and most of the tme the crcut remans n standby mode( for example, crcuts of cell phones) the mpact of process varaton on the optmal age should be mnmzed wth prorty snce age s much more senstve to the process varaton; Case 3 - f the optmal age s comparable to the optmal dynamc power, and most of the tme the

5 crcut s n the actve mode (for example, crcuts of portable GPS, portable game machnes, etc.) both the mean and standard devaton of the dynamc power dstrbuton should be optmzed. 3.5 Mnmzng mpact of process varaton on age In case 1 and case 3, dynamc power s the domnant component of the total power consumpton. Its standard devaton s determned by the number of gltch flterng constrants (10) whose δ[ have postve values. So, n the MILP objectve functon (13), we frst let W3 be nfntely large to put the hghest prorty on mnmzng Σδ[: Mn W 1 I [] [] [ ] + W 2 sze + Δd, j + W 3 δ [ W 3 > j (13) Although MILP tres to mnmze Σδ[, δ[ for some gates may stll be postve snce the constrant (9) s too tght to be satsfed wthout the help of a postve δ[. Every postve δ[ possbly results n the gltch generaton at gate s output. From Fgure 4, we also see that the average dynamc power almost lnearly ncreases wth the process varaton. Ths ncrease s contrbuted by the gltches caused by the process varato. To counteract the ncrease n the average dynamc power due to those gltches, or to let the really average dynamc power n process varaton condton stll be close to that acheved by the determnstc MILP formulaton, we sacrfce some age power and get a smaller logc swtchng power. Ths can be acheved by lettng W1 and W2 both equal to 1 n the MILP objectve functon (14) and addng a new constrant (15) to the statstcal MILP formaton. Mn C [] [] [ ] 1 I + C 2 sze + C3 Δd, j + W 3 δ [ W > j (14) [] + C Δd[ j] P / ρ C < ( ρ>1) (15) sze 2 3, dyn _ opt j P dyn_opt s the optmal dynamc power obtaned by the determnstc MILP [15-16] and ρ s a constant determned by the process varaton. By lettng ρ larger than 1, the statstcal MILP formulaton can gve an optmal crcut wth less dynamc power. 3.6 Mnmzng mpact of process varaton on age In case 2, age almost equals or s even larger than the dynamc power. Snce age s so senstve to the process varaton that we cannot mnmze the effect of process varaton on the dynamc power by sacrfcng age any more. The technque of elmnatng gltches has to be dscarded snce the ncrease n the average dynamc power under process varaton may be close to or even larger than the gltch power saved. To make the age of optmzed crcuts resstant to the process varaton, we can stll use the MILP proposed n [17] except every gate has sx possble choces nstead of two choces. Probablty statstcal µ=1.04 3σ/µ=2.82% (µ-n)/n=3.63% determstc µ=1.14 3σ/µ=5.13% (µ-n)/n=13.53% Normalzed Dynamc Power Fgure5. Comparson of the mpacts of 15% local process varaton on the dynamc power n C432 whch s optmzed by the statstcal MILP wth the emphass on the resstance of dynamc power to process varaton, or by the determnstc MILP [15-16]. (Dynamc power = 1 s the expected normalzed mnmum dynamc power n the optmzed gltch-free C432). Probablty statstcal N2=1.94 µ=2.25 σ/µ=10.24% (µ-n1)/n1=16.97% determnstc N1=1.00 µ=1.17 σ/µ=6.64% (µ-n2)/n2=15.22% Normalzed Leakage Fgure 6. Comparson of the mpacts of 15% local L eff process varaton on the age power n C432 whch are optmzed by the statstcal MILP wth the emphass on the resstance of dynamc power to process varaton, or the determnstc MILP [15-16]. (N1 and N2 are the normalzed nomnal age power n the optmzed gltchfree C432). 4. Results In C432 optmzed by the determnstc MILP formulaton [15-16], the optmzed total power comprses 59.3μW dynamc power and 5.54μW age power. Wth 15% local process varaton, the average dynamc power ncreases 13.53% wth 5.13% standard devaton. To reduce the mpact of process varaton on the dynamc power, the objectve functon (14) and constrant (15) (let P dyn_opt =59.3μW and ρ=1.10) are adopted n the statstcal MILP formulaton. The two curves n Fgure 5 show that

6 the average dynamc power only ncreases 3.63% nstead of 13.53%, and standard devaton s also reduced to 2.82% from 5.13% when 15% local process varaton s appled to the optmzed gltch-free C432, although at a cost of 94% average age power ncrease (from 1.0 to 1.94) and a lttle bt wder spread of age power dstrbuton, whch s shown n Fgure 6. Y Use statstcal MILP to mnmze process varaton mpact on dynamc power Use determnstc MILP to get the optmal power Smulate optmzed crcut wth certan process varaton, get mean and standard devaton of age Can age stll be gnored under certan process varaton? N N Is crcut most tme n standby mode? Y Use statstcal MILP to mnmze process varaton mpact on ge power Fgure 7. An algorthm to determne whether age or dynamc power should be optmzed wth process varaton. 5. Summary In ths paper, the mpact of process varaton on dynamc power s analyzed, and a statstcal MILP formulaton s presented to mnmze the total (dynamc and age) power n gltch-free crcuts consderng process varaton. The mpact of process varaton on dynamc power can be mnmzed by gvng up some age f the dynamc power s stll the domnant power component under process varaton. Fgure 7 gves a flowchart of how to make a decson about whch one, age or dynamc power, should be optmzed wth process varaton. 6. References [1] M. Man, A. Devgan, and M. Orshansky, "An Effcent Algorthm for Statstcal Mnmzaton of Total Power Under Tmng Yeld Constrants," Proc. Desgn Automaton Conference, 2005, pp [2] A. Davood and A. Srvastava, Probablstc Dual-V th Optmzaton Under Varablty, Proc. ISLPED, 2005, pp [3] A. Srvastava, D. Sylvester, D. Blaauw, Statstcal Optmzaton of Leakage Power Consderng Process Varatons Usng Dual-V th and Szng, Proc. Desgn Automaton Conf., 2004, pp [4] A. P. Chandrakasan and R. W. Brodersen, Low Power Dgtal CMOS Desgn. Boston: Sprnger, [5] V. D. Agrawal, "Low Power Desgn by Hazard Flterng," Proc. 10th Int. Conf. VLSI Desgn, 1997, pp [6] V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, "Dgtal Crcut Desgn for Mnmum Transent Energy and a Lnear Programmng Method," Proc. 12th Internatonal Conf. VLSI Desgn, 1999, pp [7] E. Jacobs and M. Berkelaar, "Usng Gate Szng to Reduce Gltch Power," Proc. PRORISC/IEEE Workshop on Crcuts, Systems and Sgnal Processng, 1996, pp [8] S. Km, J. Km, and S. Y. Hwang, "New Path Balancng Algorthm for Gltch Power Reducton," IEE Proc. Crcuts, Devces and Systems, vol. 148, no. 3, pp , [9] C. V. Schmpfle, A. Wroblewsk, and J. A. Nossek, "Transstor Szng for Swtchng Actvty Reducton n Dgtal Crcuts," Proc. European Conference on Theory and Desgn, 1999, pp [10] A. Wroblewsk, C. V. Schmpfle, and J. A. Nossek, "Automated Transstor Szng Algorthm for Mnmzng Spurous Swtchng Actvtes n CMOS Crcuts," Proc. IEEE Internatonal Symposum on Crcuts and Systems, 2000, pp [11] T. Raja, V. D. Agrawal, and M. L. Bushnell, "Mnmum Dynamc Power CMOS Crcut Desgn by a Reduced Constrant Set Lnear Program," Proc. 16th Internatonal Conf. VLSI Desgn, 2003, pp [12] T. Raja, V. D. Agrawal, and M. L. Bushnell, "Varable Input Delay CMOS Logc for Low Power Desgn, Proc. 18th Internatonal Conf. VLSI Desgn, 2005, pp [13] F. Hu and V. D. Agrawal, "Input-Specfc Dynamc Power Optmzaton for VLSI Crcuts," Proc. Int. Symp. Low Power Electroncs and Desgn, 2006, pp [14] F. Hu, "Process-Varaton-Resstant Dynamc Power Optmzaton for VLSI Crcuts," PhD Thess, Auburn, Alabama: Auburn Unversty, May [15] Y. Lu and V. D. Agrawal, "CMOS Leakage and Gltch Power Mnmzaton for Power-Performance Tradeoff," Journal of Low Power Electroncs, vol. 2, no. 3, pp , Dec [16] Y. Lu and V. D. Agrawal, "Leakage and Dynamc Gltch Power Mnmzaton Usng Integer Lnear Programmng for Vth Assgnment and Path Balancng," Proc. of the Internatonal Workshop on Power and Tmng Modelng, Optmzaton and Smulaton, 2005, pp [17] Y. Lu and V. D. Agrawal, "Statstcal Leakage and Tmng Optmzaton for Submcron Process Varaton," Proc. 20th Internatonal Conf. VLSI Desgn, 2007, pp

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