High Gain Soft-switching Bidirectional DC-DC Converters for Eco-friendly Vehicles

Transcription

1 Hgh Gan Soft-swtchng Bdrectonal DC-DC Converters for Eco-frendly ehcles Mnho Kwon, Junsung Park and Sewan Cho, EEE Senor Member Department of Electrcal and nformaton Engneerng Seoul Natonal Unversty of Scence and Technology Seoul, Korea E-mal: Abstract Ths paper proposes a non-solated soft-swtchng bdrectonal DC-DC converter sutable for hgh step-up and step-down applcatons. The proposed converter can acheve ZS turn on of all swtches and ZCS turn off of some swtches n both CCM boost and buck operatons. An optmzed swtchng strategy s presented to mnmze swtch current ratng and acheve soft-swtchng n wder range. An ntermedate swtchng pattern s ntroduced to carry out seamless mode change. Expermental results from a 5kW prototype are provded to valdate the proposed concept.. NTRODUCTON n hybrd electrc vehcles(he) the nput voltage of the nverter has a tendency to ncrease n order to use hgh speed hgh power motor and mprove the effcency and power densty of the nverter. For example, the nput voltage has ncreased from 500 to 650 n 3rd generaton PCU of Toyota Prus HE where a N-MH battery of nomnal voltage of has been nstalled[1]. n the meantme the battery voltage s preferred to be low snce parallel strngs of storage batteres not only enhance the redundancy of the back-up system but also allevate the problems assocated wth charge mbalance compared to seres strngs. Therefore, hgh effcency bdrectonal DC-DC converter (BDC) wth hgh voltage gan s necessary n the aforementoned systems. The non-solated BDC based on the half-brdge topology has a smple structure but should operate at hgh duty cycle to provde hgh step-up gan (greater than 4) when the battery voltage s low. Then, the boost dode must sustan a short pulse current wth hgh ampltude, resultng n severe reverse recovery as well as hgh EM problems. Usng an extreme duty cycle may also lead to poor dynamc responses to lne and load varatons. Moreover, the swtch should sustan hgh output voltage, and hence swtch conducton losses resultng from the hgh on drop voltage of the hgh-voltage-rated swtches are consderable. These make the conventonal halfbrdge topology neffcent n the applcatons where hgh voltage gan s requred. BDCs based on coupled or tapped nductors [2]-[5] can provde hgh output voltage wthout extreme duty cycle and yet reduce the swtch voltage stress. n these coupled nductor converters, n general, the effort to overcome the problem assocated wth leakage nductor of the couplng nductor s non-trval, and the capacty of the magnetc core should substantally be ncreased as the requred output power s ncreased. Therefore, these topologes ncorporatng the couplng nductor are not sutable for hgh power applcatons. Also, the nput current rpple s consderable due to the operaton of couplng nductor. The BDC usng swtched-capactor converter cells could have more modular structure and hgher power handlng capablty, but the requred number of swtches becomes hgh [6]-[8]. They are hard-swtched, and hgh current pulse occurs snce two capactors wth dfferent voltages are connected n parallel at each swtchng nstant. A major drawback of the swtched-capactor based converter s that ESR drop of the actve and passve devces s consderable due to hgh number of seres connected devces n the current path, resultng n reduced output voltage. Ths may restrct the power level to whch the swtched-capactor converter can be appled. Soft swtched BDCs wth a auxlary crcut have been proposed to acheve ZS or ZCS of man swtches n both boost and buck modes of operatons [9],[10]. The converter n [10] shows hgh effcency despte of ts crcut complexty. However, they are not sutable for applcatons where hgh voltage converson rato n both buck and boost operatons s requred. So far, the non-solated BDC wth hgh voltage gan that can be appled to hgh power level has rarely been proposed. n ths paper a new non-solated BDC for hgh step-up/step down and hgh power applcatons s proposed. The optmzed PWM swtchng technque for buck and boost operaton and smooth mode transton s also presented. The proposed converter has the followng advantages: Hgh voltage gans for both boost and buck mode operatons. Reduced voltage stresses of swtches. ZS turn-on of swtches n CCM operaton. Reduced energy volumes of passve components Seamless mode transton Ths work was supported by the Natonal Research Foundaton of Korea(NRF) grant funded by the Korea government(mest) (No ) /13/$ EEE 1776

2 . PROPOSED CONERTER Fg. 1 shows the crcut dagram of the proposed BDC. The proposed converter consst of a general buck/boost converter as the man crcut and an auxlary crcut whch ncludes capactor, nductor and two hgh voltage sde (HS) swtches and. The goal of control n ths paper s assumed to regulate the HS voltage whle allowng bdrectonal power flow accordng to the drecton of nductor current. A. Operatng Prncple Assume that capactances, and are large enough so that voltages C1, C2 and Ca across them are constant durng the swtchng perod T S. 1) Boost Operaton Fg. 2 and Fg. 3 show key waveforms and operaton states of the boost mode, respectvely. n ths mode, low voltage sde (LS) swtches and are operated wth asymmetrcal complementary swtchng wth duty cycles of D and 1-D, respectvely, as shown n Fg. 2. n the mean tme HS swtches and are turned on wth delay tmes of t d3 and t d4, respectvely. The operaton of the proposed converter can be dvded nto fve modes, as shown n Fg. 3 Mode [t 0 ~ t 1 ] : Ths mode begns wth turnng off of and. Then the body dodes of and are turned on. The gatng sgnal for s appled wth approprate dead-tme durng ths mode, and then could be turned on under ZS conon. nductor currents and start to ncrease and decrease, respectvely, wth the slopes determned by the followng equatons: d L = (1) Fg. 1. Proposed hgh step-up soft-swtched bdrectonal dc-dc converter. t 0 ~ t 1 t 1 ~ t 2 t 2 ~ t 3 t 3 ~ t 4 t 4 ~ t 5 Fg. 2. Key waveforms of the proposed converter(boost mode). Fg. 3. Operaton states of the proposed converter(boost mode). 1777

3 d Ca C1 =. (2) Mode [t 1 ~ t 2 ] : When the ncreasng current becomes greater than the decreasng current, current flowng through s reversed, and the man channel of conducts. Ths mode ends when the decreasng current reaches to 0A. Note that swtch s also turned off under ZCS conon. Mode [t 2 ~ t 3 ] : At t 2 current s reversed and the body dode of s turned on. For synchronous rectfcaton the gatng sgnal for can be appled after t 2. Note that s turned on under ZS conon. nductor current lnearly ncreases wth the slope determned by the followng equatons: d Ca C1 =. (3) Both nductor currents and flow through swtch. Mode [t 3 ~ t 4 ] : At t 3 swtches and are turned off, and then body dodes of and are turned on. Both nductor currents and start to decrease wth the slopes determned by the followng equatons: d L C1 = (4) d Ca =. (5) The gatng sgnal for s appled wth approprate deame durng ths mode, and then could be turned on under ZS conon. Ths mode ends when the decreasng current reaches to 0A. Note that swtch s also turned off under ZCS conon. Mode [t 4 ~ t 5 ] : Ths mode begns when current s reversed and the body dode of s turned on. For synchronous rectfcaton the gatng sgnal for can be appled after t 4. Note that s turned on under ZS conon. nductor current lnearly ncreases wth the slope determned by the followng equaton: d Ths s the end of one complete cycle. 2) Buck Operaton Ca =. (6) Fg. 4 and Fg. 5 show key waveforms and operaton states of the buck mode, respectvely. n ths mode, HS swtches and are operated wth asymmetrcal complementary swtchng wth duty cycles of D and 1-D, respectvely, as shown n Fg. 4. n the mean tme LS swtch s turned on wth delay tme of t d2. The operaton of the proposed converter can be dvded nto sx modes, as shown n Fg. 5. Mode [t 0 ~ t 1 ] : Ths mode begns wth turnng off of swtches and. Then the body dodes of and are turned on after the parastc capactors of and are completely dscharged. nductor current starts to decrease wth the slope determned by equaton(1). Mode [t 1 ~ t 2 ] : At t 1 nductor current starts to decrease wth the slope determned by equaton(3). After approprate dead-tme swtches and are turned on. The gate sgnal for should be appled before reversal of current for ZS turn on. Note s turned on wthout any delay for synchronous rectfcaton. Ths mode ends when the decreasng current reaches to 0A. Mode [t 2 ~ t 3 ] : At t 2 nductor current s reversed and starts ncreasng wth slope determned by equaton (3). From equaton (3) the postve peak value of can be obtaned as follows: 2 C = DT +. (7) Ca C1 OSS + S Mode [t 3 ~ t 4 ] : Swtches and are turned off at t 3, and then body dodes of and are turned on. nductor current starts to decrease wth the slope determned by equaton (2). Note that could be turned on under ZS conon f the gate sgnal for s appled wth approprate dead-tme before reversal of current. Ths mode ends when the decreasng Fg. 4. Key waveforms of the proposed converter(buck mode). 1778

4 t 0 ~ t 1 t 1 ~ t 2 t 2 ~ t 3 t 3 ~ t 4 t 4 ~ t 5 t 5 ~ t 6 Fg. 5. Operaton states of the proposed converter(buck mode). current reaches to 0A. Mode [t 4 ~ t 5 ] : When the ncreasng current becomes greater than the decreasng current, body dode of s turned off under ZCS conon. Then after parastc capactors of and are completely charged and dscharged, respectvely, the body dode of s turned on and nductor currents and start to decrease and ncrease, respectvely, wth slopes determned by equatons (6) and(4). The negatve peak value of s determned by the followng equaton: Δ C1 = +. (8) 2 L /(2 C ) For ZS turn on of the gate sgnal for should be appled before the decreasng current becomes smaller than the ncreasng current. Mode [t 5 ~ t 6 ] :At t 5 swtch current S2 s reversed. nductor currents and keep decreasng and ncreasng wth slopes determned by equatons (6) and (4), respectvely. At the end of ths mode and are turned off. Ths s the end of one complete cycle. B. oltage Converson Rato The HS voltage s gven by the followng equaton: 2 H = L (9) Deff where the effectve duty s defned as follows(see Fg. 2): D = D ( d + d ) (10) eff 3 4 where d 3 + d 4 means duty loss. The output voltage can also be expressed as follows: 2 H = L Δ (11) D where Δ s the voltage drop caused by the duty loss. From (9), (10) and (11) the voltage drop Δ can be obtaned as follows: 2 L ( d3+ d4) Δ =. (12) (1 D)(1 D+ d + d ) a 3 4 oltage C1 that s same as output voltage of the general boost converter can be expressed as follows: 1 C1 = L. (13) D By applyng volt-second prncple to nductor, we can obtan the mnmum delay tmes for ZS turn on of and by the followng equatons: + dt 3 S = (14) C1 C1 OSS dt 4 S =. (15) Snce the average value of swtch currents S3 and S4 s the same as that of HS current H = /R H and the dfference n duty losses d 3 and d 4 are much smaller than duty cycle D, postve and negatve peak values of the nductor current can be approxmated, respectvely, by 1779

5 2 H + T D R 2 H H H S (16) TS D R. (17) The actual delay tmes for and, t d3 and t d4, are determned, respectvely, as follows: td3 = d3ts + dead-tme (18) td4 = d4ts + dead-tme. (19) From (9), (10), (13), (14) and (15) the voltage gan can be obtaned as follows: where α = DRH and β = 4L a. H L 2 2 α (1 D) + 4 αβ α(d) = (20) β Usng (20) the voltage gan of the proposed converter s plotted as shown n Fg. 6. C. Mode Change Strategy The optmzed swtchng patterns for boost and buck operatons are dfferent as we can see from Fg. 7(a) and (c). n ths secton a mode change strategy s proposed for seamless transfer from buck mode to boost mode, and vce versa. n order to carry out seamless transfer durng mode change an ntermedate swtchng pattern (See Fg. 7(b)) s nserted between the two swtchng patterns for boost and buck modes. The swtchng sequence for transfer from boost mode to buck mode s Pattern1 Pattern2 Pattern3. The swtchng sequence for transfer from buck mode to boost mode s Pattern3 Pattern2 Pattern1. Fg. 8 and Fg. 9 show the swtchng sequence and control block dagram for the proposed BDC, respectvely. The moment at whch the swtchng pattern s changed s determned by comparng the nstantaneous average value,avg of the nductor current to the preset values of,upper or,lower. H / L Duty Fg. 6. oltage gan of the proposed converter. (a) (b) (c) Fg. 7. Swtchng pattern for each operaton. (a) Pattern 1 (boost operaton). (b) Pattern 2 (ntermedate operaton). (c) Pattern 3 (buck operaton). Pattern 1 Pattern 2 Pattern 3 Pattern 2 Pattern 1,,,avg,upper 0,lower Fg. 8. Swtchng sequence for seamless mode change. Boost Mode Buck Mode Boost Mode 1780

6 . EXPERMENTAL RESULTS The nterleavng technque can be appled to reduce the sze of passve components and current stresses. A 5kW prototype of the two-phase nterleaved verson of the proposed converter shown n Fg. 10 was bult accordng to the followng specfcaton: * * P o = 5kW = 400 = 72 f s = 20kHz = 4uH = = = 30uF Both LS and HS swtches are mplemented wth XFN100N50P(500, 90A, and 49mΩ) MOSFET. The nomnal duty cycle of 0.64 was used to acheve voltage gan of 5.5 n the both buck and boost modes of operaton. The actual delay tmes t d2, t d3 and t d4 were chosen to be 1500ns, 1500ns and 1200ns, respectvely. The pre-set values,upper and,lower for mode change were used as 1.5A and -1A, respectvely. Expermental waveforms of mode change are also shown n Fg. 11. t s seen that there are no transents caused by change of swtchng patterns durng the mode change. Expermental waveforms of the proposed converter for boost and buck operatons are shown n Fgs. 12 and 13, respectvely. Fgs. 12 (a) to (d) show voltage and current waveforms of swtches to n boost mode. Fgs. 13 (a) to (d) show voltage and current waveforms of swtches to n buck mode. t can be seen that all swtches are turned on wth ZS n both operatons. The measured effcency s shown n Fg. 14. The effcency was measured by YOKOGAWA WT3000. The maxmum effcency n boost mode and buck mode s 97.3% at 1kW and 97.2% at 2kW, respectvely.. CONCLUSON n ths paper a non-solated soft swtchng BDC has been proposed for hgh voltage gan and hgh power applcatons. Fg. 10. Crcut dagram of the two-phase nterleaved prototype converter. Fg. 11. Expermental waveforms of mode change. Fg. 9. Control block dagram of proposed converter for regulatng HS voltage under bdrectonal operaton. (a) (b) (c) (d) Fg. 12. Expermental waveforms of the proposed converter n boost mode. (a) voltage and current of swtch. (b) voltage and current of swtch. (c)voltage and current of swtch. (d) voltage and current of swtch. (a) (b) (c) (d) Fg. 13. Expermental waveforms of the proposed converter n buck mode. (a) voltage and current of swtch. (b) voltage and current of swtch. (c)voltage and current of swtch. (d) voltage and current of swtch. 1781

7 Fg. 14. Measured effcency. Boost Mode Buck Mode 1k 2k 3k 4k 5k The proposed converter can acheve ZS turn on of all swtches and ZCS turn of some swtches n both boost and buck operatons. An optmzed swtchng sequence s presented along wth an ntermedate swtchng pattern to carry out seamless mode change. A 5kW prototype of the proposed converter has been bult and tested to verfy the valy of the proposed operaton. A nomnal duty cycle of 0.64 was used to acheve voltage gan of 5.5 n the both buck and boost modes of operaton. REFERENCES [1] [2] P. Das, S.A. Mousav, G. Moschopoulos, Analyss and Desgn of a Nonsolated Bdrectonal ZS-PWM DC DC Converter Wth Coupled nductors, EEE Trans. Power Electron., vol. 25, no. 10, pp , Oct [3] B.L. Narasmharaju, S.P. Dubey, S.P. Sngh, Desgn and analyss of coupled nductor bdrectonal DC-DC convertor for hgh-voltage dversty applcatons," ET. Power Electron., vol. 5, no. 7, pp , Aug [4] R.J. Wa, R.Y. Duan, Hgh-Effcency Bdrectonal Converter for Power Sources Wth Great oltage Dversty, EEE Trans. Power Electron., vol. 22, no. 5, pp , Spet [5] L.S. Yang, T.J. Lang, Analyss and mplementaton of a Novel Bdrectonal DC DC Converter, EEE Trans. nd. Electron., vol. 59, no. 1, pp , Jan [6] F.L. Luo, H. Ye, M.H. Rashd, Swtched capactor four-quadrant DC/DC Luo-converter, EEE AS. nd. Appl. Conf., 1999, vol. 3, pp [7] F.H. Khan, L.M. Tolbert, W.E. Webb, Hybrd Electrc ehcle Power Management Solutons Based on solated and Nonsolated Confguratons of Multlevel Modular Capactor-Clamped Converter, EEE Trans. nd. Electron., vol. 56, no. 8, pp , Aug [8] We Qan, Dong Cao, J.G. Cntron-Rvera, M. Gebben, D. Wey, Fang Zheng Peng, A Swtched-Capactor DC DC Converter Wth Hgh oltage Gan and Reduced Component Ratng and Count, EEE Trans. nd. Appl., vol. 48, no.4, pp , July-Aug [9] P. Das, B. an, S.A. Mousav, G. Moschopoulos, A Nonsolated Bdrectonal ZS-PWM Actve Clamped DC DC Converter, EEE Trans. Power Electron., vol. 24, no. 2, pp , Fed [10] Y. Tsuruta, Y. to, A. Kawamura, Snubber-Asssted Zero-oltage and Zero-Current Transton Blateral Buck and Boost Chopper for E Drve Applcaton and Test Evaluaton at 25 kw, EEE Trans. nd. Electron., vol. 56, no. 1, pp. 4 11, Jan [11] S. Park, S. Cho, Soft-Swtched CCM Boost Converters Wth Hgh oltage Gan for Hgh-Power Applcatons, EEE Trans. Power Electron., vol. 25, no. 5, pp , May [12] S. Park, Y. Park, S. Cho, W. Cho, K. Lee, Soft-Swtched nterleaved Boost Converters for Hgh Step-Up and Hgh-Power Applcatons, EEE Trans. Power Electron., vol. 26, no. 10, pp , Oct