An improved dc capacitor voltage detection technology and its FPGA implementation in the CHB-based STATCOM

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1 An mproved dc capactor voltage detecton technology and ts FPGA mplementaton n the CHB-based STATCOM Xngwu Yang, Janfe Zhao, Janguo Jang Department of Electrcal Engneerng Shangha Jao Tong Unversty Shangha P.R.CHINA yxw790930@sjtu.edu.cn Abstract: - In ths paper, an mproved sngle multple-voltage (SMV) detecton technology based on cascaded H-brdge(CHB) multlevel nverter-based statc synchronous compensator (STATCOM) s ntroduced and t s realzed usng a Fled Programmable Gate Array(FPGA) by delay technology. The advantage of the mproved SMV detector s that, t could save a lot of voltage sensors by usng the nverter output voltage to detect the dc capactor voltage of each H-brdge unt, meanwhle, t could get ther mean value more accurately. Take nto account delay tme n detecton crcut and control crcut, n order to transform ths detecton technology nto practce, a novel delay technology s studed. Based on delay technology, an mplementaton method of the mproved SMV detector usng a FPGA s also ntroduced. The expermental results prove ts feasblty and practcalty. Key-Words: - CHB nverter, statc synchronous compensator (STATCOM), dc capactor voltage detecton, FPGA, delay technology 1 Introducton Reactve power compensaton s an essental part n a power system, snce t could mprove the energy transmsson capablty, stablze the power system and mantan the supply voltage and so on[1]-[3]. Recent advances n hgh power electronc swtches have enabled the development of new controllable fast reactve power compensators such as statcsynchronous compensator (STATCOM) [4]. Conventonally, STATCOM s composed of one nverter wth energy storng capactor on ts dc sde, nductances and a couplng transformer on ts ac sde, whch s connected n parallel wth the system at the pont of common couplng (PCC), as shown n Fg.1, the fundamental prncple of STATCOM s the generaton of a controllable ac voltage source by a voltage source nverter(vsi). The ac voltage source appears behnd the transformer leakage reactance. So the actve and reactve power transfer s caused by the voltage dfference across ths reactance[5]. In recent years, multlevel voltage source nverter has ganed much attenton. The nverter can use a number of technques to construct hgh-qualty ac waveforms from several swtched dc sources, so t s possble to acheve hgh-voltage low-dstorton ac waveforms, whch result n lower harmonc generaton[4], smaller reactor sze[6], and elmnatng bulky and costly transformer [7][8]. There are three well-establshed topologes of multlevel nverter: neutral pont clamped[9], flyng capactor[10] and CHB converter confguraton[11]- [13]. Ths paper deals wth the CHB nverter whch s deemed as one of the most promsng topologes for STATCOM applcaton[6][11]. A seven level sngle phase CHB multlevel converter s llustrated n Fg.2. One of the man dsadvantages of the CHB-based STATCOM s the voltage mbalance between the multple floatng dc capactors, unequal conductng and swtchng losses produced by power swtchng devces, as well as resoluton ssues nherent n the control crcut, may brng voltage mbalance to the dc capactors. Several lterature studed the problem and proposed dfferent control strateges, such as usng lowfrequency modulaton technques[12] or takng adequate control strategy to change the actve power absorbed by each H-brdge unt [8][13][14]. No matter what methods, n order to realze dc capactor voltage balancng control, dc capactor voltage of each unt has to be detected. It means that M-level CHB-based STATCOM need 3( M 1) / 2 voltage sensors. In order to reduce voltage sensors, lterature[15] proposed a sngle multple-voltage (SMV) detector to detect all dc capactor voltages through detectng the output phase voltage of CHB ISSN: Issue 1, Volume 9, January 2010

2 V pcc system has excellent steady-state and dynamc performance. I c V c Fg.1- STATCOM basc structure 2 System confguraton and control scheme As s shown n Fg.3, The CHB nverter s connected to the PCC at the ac system through a flter wth nductance L c, and the PCC s suppled power from the ac source. The objectve of the STATCOM s to generate a proper output voltage to get a leadng or laggng reactve current, thus, t can compensate reactve power generated by the load. S 11 S 13 v dc1 v dc2 v dc3 S 12 S 21 S 22 S 31 S 14 S 23 S 24 S Confguraton of CHB-based STATCOM Fg.3 shows the system confguraton of the CHB nverter based STATCOM, where us s the source voltage, s s the source current, L s the load current, c s the current drawn by the STATCOM, cd, cd cq, cq s the reactve current and ts reference, s the actve current and ts reference, v s the dc capactor voltage reference of each H-brdge, and θ s the phase angle of the publc pont of voltage. dc S 32 S 34 Fg.2- A seven level sngle phase CHB multlevel converter nverter. Where, SMV detecton method s tested based on the dspace prototypng system, but t doesn t fnsh a depth-analyss of some ssues whch need to be pad attenton n practcal applcaton. In ths paper, an mproved SMV detector based on the CHB-based STATCOM s proposed, whch can get more accuracy value of the dc mean capactor voltage, n addton, an mplementaton method wth a feld programmable gate array (FPGA) s presented. Because the accuracy of SMV detector s affected by many factors, such as the detecton crcut, the samplng frequency and so on, a novel delay technology s studed. The man factors whch determne the delay tme such as detecton crcut, cascade number n each phase and swtchng frequency are analyzed emphatcally. Ths strategy s expermentally valdated. The proposed dc capactor voltage detecton method s combned wth the carrer phase shft SPWM(CPS-SPWM) modulaton strategy and ndvdual balancng control technology, so the balancng control of dc capactor voltages s easy to be mplemented. Expermental results shows that the STATCOM 2.2 Control Scheme The STATCOM control scheme contans output current control and voltage balancng control. In order to control actve current and reactve currents ndependently and get good dynamc performance, output current control adopts decoupled current control strategy[1][3]. In order to ensure that STATCOM s stable, voltage balancng control comprses dc capactor voltage control and an ndvdual balancng control as shown n Fg Decoupled Currents Control Strategy In d-q synchronous reference frame, the mathematcal expresson of the STATCOM s shown as follows: d cd vsd vcd cq Lc = + ω Lc dt cq vsq vcq cd (1) In order to generate the desred actve and reactve current components cd and cq for the STATCOM, the references of the STATCOM output voltages u cd and u, should be gven as cq ISSN: Issue 1, Volume 9, January 2010

3 v dc u s v dc Ls cq s v dc cd cd cq v dc v dc v pcc ωl c ωl c vpcc L v sd θ u cd u cq δ v dc δ L L RL c L C1 c C 2 Fg. 3. System confguraton and control block dagram of the CHB-based STATCOM (2) and (3) u u cd cq (4) Where, ndex v = v sd sq + ω Lc c cq cd L L 2 ( ucd ) ( ucq u = + δ = tan 1 ) ( u cd u cq ) 2 c c d dt d dt cd cq u c can be used to obtan modulaton c knv dc MI = u / (5) (k s a constant whose value depends on the modulaton technque scheme used, n s the cascade number. n ths paper, k s 0.5) Based on (3) ~ (5), a decouplng feedforward control s obtaned as shown n Fg.3. In ths fgure, the actve current reference cd s used to regulate the dc voltage, and the reactve current reference cq s gven accordng to dfferent compensaton ams[1] Voltage balancng control STATCOM should consume a small amount of energy due to swtchng losses, copper- and coreloss of reactor, so current controller should supply approprate actve power to compensate the power C loss of STATCOM. The reference of the actve current can be obtaned by dc capactor voltage control as shown n Fg.3, when the actve current n d-axs cd reaches to t s reference, the dc mean capactor voltage has been regulated to ts desred value v dc. However, dc capactor voltage controller can only ensure that the power drawn from each dc sde s equal, due to unequal conductng and swtchng losses, as well as resoluton ssues nherent n the control crcut, t wll result n dc capactor voltages mbalance. Dc capactor voltages mbalance wll affect the character of STATCOM and even damage the swtch devce. So for multlevel nverter based on STATCOM, dc voltage regulaton s essental n normal operaton. In order to compensate the power loss of STATCOM and mantan the dc capactor voltage at desred value, approprate actve power should be absorbed by STATCOM. PI controller s appled to regulate ndvdual dc capactor voltage, the error between dc capactor voltage reference and each actual dc capactor voltage s fed to PI controller. The output s used to regulate the phase of output voltage whch affects actve power absorbed, so dc sde of each unt can absorbed dfferent and approprate actve power to make ndvdual dc capactor voltage balancng. As shown n Fg.3, each phase angle s determned by: δ = δ + δ = 1,2,3... n (6) For 5-level CHB-based STATCOM, the modulaton wave can be obtaned uu1 = MI cos( θ + δ1) uu2 = MI cos( θ + δ 2) uv 1 = MI cos( θ + δ1 120 ) (7) uv 2 = MI cos( θ + δ ) uw1 = MI cos( θ + δ ) uw2 = MI cos( θ + δ ) 3 Dc capactor voltage detecton technque For tradtonal detecton strategy used n CHB-based STATCOM, output voltage of each H-brdge unt need a voltage sensor to detect, n a M-level CHBbased STATCOM, there are 3( M 1) / 2 H-brdge to be detected, that s, 3( M 1) / 2 voltage sensors are requred. Lterature[15] proposed a new detectng technque, all ndvdual dc capactor voltage can be obtaned through a SMV detector based on the nverter output voltages, thus, each phase of the ISSN: Issue 1, Volume 9, January 2010

4 cascaded nverter only need one voltage sensor to detect dc capactor voltage. Tradtonal dc capactor voltage measurement method and SMV detecton method shown n Fg.4. v dc1 v dc2 v dc Voltage sensor Voltage sensor Voltage sensor S 11 S 12 S 21 S 22 S 1 S 2 S 13 S 14 S 23 S 24 S 3 S 4 v c S 11 S 12 S 21 S 22 S 1 S 2 S 13 S 14 S 23 S 24 S 3 S 4 v c Voltage sensor SMV detector v dc1, v dc2, v dc Fg.4- Two dc capactor voltage detecton methods n CHB multlevel nverter. tradtonal method, SMV detecton method. 3.1 Prncple of a new dc capactor voltage detecton For CHB converter, all unts are connected n seres, so the converter nstantaneous total output voltage s equal to the sum of the ndvdual dc capactor voltage, that s = n v c v H = 1 (8) The converter used n STATCOM acts as an nverter, each H-brdge unt can generate three-level output, +Vdc, 0V, -Vdc by connectng dc voltage to ac sde through dfferent states of the four swtches. Defne a condton as follows: one H-brdge unt n one phase, such as H generates output voltage +Vdc or -Vdc, other unts generate output voltage 0V. So the nverter phase voltage equals to the output voltage of unt H. v c = vh = ± vdc (9) Therefore, the dc capactor voltage of H-brdge unt H can be obtaned from the nverter phase voltage as follows: v dc = v c. (10) The prme of vdc denotes that the dc capactor voltage s obtaned by dc voltage detecton method nstead of measurng from the voltage sensor. 3.1 Improved sngle multple-voltage detector Accordng to the prncple of dc capactor voltage detecton above, a SMV detector can be desgned. Owng to dc mean capactor voltage v s also used n STATCOM control scheme, n order to mprove the accuracy of v dc, an mproved SMV detector s proposed. Here, we take a seven-level nverter as an example, and the prncple can be explaned wth the ad of Fg.5. Waveforms n Fg.5 shows that a sngle modulatng sne wave s compared wth sx phase shfted trangular carrer to decde the swtchng nstants. Fg.5-(d) are three H-brdge unts output voltages and Fg.5(e)-(f) are all the nverter phase output voltage, Fg.5(e) s to show the prncple of mproved SMV detecton strategy and another s to show the prncple of tradtonal SMV detecton strategy. Assumng each dc capactor has the same dc voltage, defned to be E, t s clear that the output voltage of three H-brdge unts cascaded nverter contans seven dfferent level outputs (-3E, -2E, -1E, 0V, 1E, 2E, 3E). When vc s one level voltage pulse, t corresponds to the output voltage of a certan H-brdge unt. For tradtonal SMV detector as s shown n Fg.5(f), when the output voltage of u-phase v cu s dcu1 dcu2 more than one level, v, v and v dcu3 keep nvarant, so the dc mean capactor voltage n u- phase v dcu obtaned by the followng equaton also keeps nvarant. v dcu = ( vdcu1+ vdcu2+ vdcu3) /3 (11) In order to mprove the accuracy of v, t also needs to update v dcu when the output phase voltage of nverter s the max level, as t s clear that dc dcu v cu ISSN: Issue 1, Volume 9, January 2010

5 S 11 S 13 S 11 S 13 S 12 S 14 S 12 S 14 S 21 S 23 S 21 S 23 v H1 π v dcu2 S 22 S 24 v cu v dcu2 S 22 S 24 v cu v H2 v H3 v c v c π π π vh2 vh 3v H1 3 H vh2 v H 3v H 1 = 1 vh2 v H 3v H1 π vh2 v H 3v H1 Fg.5- schematc dagram of mproved SMV and tradtonal SMV detecton strategy. Table 1-Value assgnment method n u-phase for mproved SMV detector v dcu 1 = vcu v dcu 3 v dcu 2 v dcu 2 = vcu v dcu 3 v dcu 3 = vcu v dcu 2 v dcu 1 dcu 3 v dcu = vdcu / 3 v v = / 3 dcu 3 dcu v cu v v = / 3 v dcu 2 v dcu 3 dcu v cu v dcu v dcu3 S 31 S 32 S 33 S 34 v dcu3 Fg.6- Two swtchng combnaton when vcu s one and max level. corresponds to the sum of dc capactor voltages of u-phase drectly as s shown n Fg.5. v dcu = v cu /3 (12) The dc mean capactor voltage of three-phase system v s gven by dc v dc = ( vdcu+ vdcv+ vdcw) /3 (13) Table 1 shows value assgnment method of dc capactor voltage and dc mean capactor voltage. When the nverter output voltage s one level, the dc capactor voltage of one H-brdge unt H can be obtaned from the nverter voltage of u-phase v cu, so the detected dc capactor voltage vdcu s updated wth the nverter output voltage v cu, at the same tme the other dc capactor voltage need to keeps the prevous value. take one swtchng combnaton for example, S11=1, S13=0, S21=0, S23=0, S31=0, and S33=0, as s shown n Fg.6. The output voltage vcu s just the dc capactor voltage of H1 unt, so the value of vcu can be used to update the value of dcu1 v. take another example, S11=1, S13=0, S21=1, S23=0, S31=1, and S33=0, as s shown n Fg.6. The output voltage vcu s the sum of dc capactor voltages of H 1, H 2 and H3 unt. In ths way, as dcu1 v can be also updated when the output voltage s max level, ts detecton accuracy could be mproved. S 31 S 32 S 33 S 34 4 FPGA mplementaton of Improved SMV detector The mproved SMV detector s based on the swtchng state, so t s easly mplemented f a ISSN: Issue 1, Volume 9, January 2010

6 FPGA s used. Logc relatonshp of swtchng states for mproved SMV detector s shown n Table 2. (where & denotes logc of AND, ^ denotes logc of XOR, ^~ denotes logc of XNOR, and! denotes logc of NOT). Table 1 combned wth Table 2 llustrates the mplementaton method of mproved SMV detecton strategy usng FPGA. Accordng to states of the swtches, as shown n Table 2, the mproved SMV detector can acheve the detecton of each of dc capactor voltage and dc mean capactor voltage by detectng the output voltages of the CHB-based STATCOM. However, there are some factors that may affect the accuracy of SMV detector such as the response tme of the sensors and amplfer n voltage detecton crcut, etc. So, t s necessary to take effectve measures to ensure that SMV detector works well n actual applcaton. Ths paper proposes a novel delay technology durng the assgnment processes of SMV detecton. Delay tme wll be dscussed n detal below. In general, delay tme ncludes three parts. The frst part s caused by the detecton crcut, the reason s that sensor and operatonal amplfer n detecton crcut have a response tme. Voltage detecton crcut, n ths paper, uses voltage sensors LV28-p, and the sensor s response tme s determned by the parameter t r = 40µ s (90% V P max ), so, for a M level CHB nverter, response tme of the sensor between two adjacent levels can be expressed as follows(for CPS-SPWM, the output voltage level only jump a level once tme) : tr t1 = (14) M Table 2-Logc relatonshp of swtchng states used for mproved SMV detector 100V dv 1V dv Fg.7- waveform of output voltage of nverter and ts detected voltage. 100V dv 0.75V dv Fg.8- Closeup waveform of Fg.7. As the response tme of operatonal amplfer s always smaller than the sensor s, sensor s response tme could represent the entre response tme of detecton crcut. Waveforms of output voltage of 5-level cascade nverter and ts detected voltage are shown n Fg.7. Top of Fg.7 s the waveform of output voltage of the CHB nverter, and bottom s waveform of output voltage of detecton crcut. To make t clear, the closeup of Fg.7 s shown n Fg.8. It can be seen that the tested delay tme s consstent wth the analyss n equaton (14) whch s about 10 mcroseconds. The second part s caused by the process of dealng wth A/D samplng results n DSP and FPGA. Frstly, DSP sends ts AD converson results to FPGA, and then FPGA return the operaton results of SMV. Ths process wll produce a delay tme t 2, whch s about 20µ s n ths paper (If an external A/D chp combned wth FPGA to complete samplng and operaton of SMV, the second part of the delay tme could be gnored). The thrd part s a samplng perod t s. When the output voltage level of the detecton crcut s stable, the value of output voltage of the CHB nverter just ISSN: Issue 1, Volume 9, January 2010

7 can be used to update dc capactor voltage values after a samplng perod. At that tme, the updated s 0 s s 2 3 s4 s1 Fg.9- Detaled legend descrpton of the thrd part of delay tme. value s really n steady state, that s, f the update s done at the begnnng of the steady state, the updated value may be the last samplng value, whch s not n stable as shown n Fg.9. The dots n Fg.9 denote samplng ponts. At tme, updated value s s 1 whch s not n steady state. After a samplng tme, at tme, updated value s s 2 just n steady state. The overall delay tme can be assgned by the followng expresson: t t + t + delay = 1 2 (15) For output voltage of the CHB nverter, maxmum tme one level voltage sustaned s determned by the number of level and the carrer frequency f c (usng of carrer phase shft unpolar SPWM modulaton strategy). 1 tmax < ( M 1) f c (16) It s clear that the delay tme must be less than the maxmum tme one level voltage sustaned. Introduce a parameter k as margn, and k s more than one, so tmax tdelay k (17) Equaton (15) ~ (17) can be used to determne the lmtaton of the samplng frequency(recprocal of t s ), when the cascade number and the swtchng frequency are all fxed. 1 tr ts < t2 k( M 1) fc M (18) We can also obtan the lmtaton of cascade number n when the carrer frequency and samplng frequency are fxed t s 1 tr t2 ts > 0 k( M 1) fc M (19) as M s 5,7, even more f SMV could be used, n order to facltate the calculaton, equaton (19) could be expressed as: 1 tr t2 ts > 0 kmfc M (20) After substtute M = 2 n+ 1nto (20), restrcton on n can be obtaned 1 kfc ( tr + t2 + ts ) n< 2kfc ( t2 + ts ) (21) 5 Expermental setup In order to confrm the valdty of the mproved SMV detector and the performance of the CHBbased STATCOM, a 3kVA expermental prototype s bult and tested. The block dagram s shown n Fg.10. The man parameters are gven n table 3. The prototype model shown n ths paper s a fvelevel CHB nverter wth two seres H-brdge connected to the grd through a LC flter. Each H- brdge unt conssts of FAIRCHILD G80N60 IGBT and a drvng crcut. TMS320F2812 and XC3S50AN FPGA based system are employed as the controller, where FPGA s used to realze the mproved SMV detector as well as perform modulaton strategy. u s Ls s c L c vpcc Fg.10- Expermental setup for a prototype CHB-based STATCOM Table 3-Crcut parameters of the expermental setup C c L MI δ L L RL ISSN: Issue 1, Volume 9, January 2010

8 V s Q L s L c C c v dc C V kva µh mh µf V µf µs khz Based on the prevously mentoned prototype system, an experment has been carred out. We tested the performance of mproved SMV detector, n addton, the performance of the CHB-based STATCOM was tested smultaneously. 6.1 Performance of mproved SMV detector Fg shows the waveforms n Code Composer Studo (CCS) durng the system operatng. Owng to 20k samplng frequency and 2k carrer frequency used n fve-level STATCOM n ths paper, the range of overall delay tme s determned. It s tested XILINX 30MHz CLK DCM_CONV 150MHz CK GEN_DTIME PWM sgnal CK GEN_PWM CK SMV Modulaton functon DSP Address Data Bus DSP AC voltage of nverter Dc voltages Fg.11- block dagram of modulaton strategy and SMV detector mplemented n FPGA About FPGA, four man blocks are presented: Clock management block, PWM generaton block, Dead tme generaton block and SMV detector block, as shown n Fg.11. The functonal blocks presented n Fg.11 are fully mplemented n ths relatvely nexpensve ntegrated crcut. All programmng s done n verlog HDL crcut descrpton language, and each functonal block s an entty n verlog HDL. The functonal block operate as follows: Internal DCM_CONV block converts 30MHz clock to 150MHz to match the clock of DSP. GEN_PWM block generates phase shfted carrer sgnals whch compared wth a 16- b bnary number sequence transmtted from DSP as defnng a reference snusodal sgnal to generate swtchng state sgnals. GEN_DTIME block produces drvng sgnals wth deadtme. SMV block receves output voltage values of nverter transmtted from DSP to realze mproved SMV detector accordng to dfferent swtchng combnaton. 6 Expermental results (c) Fg.12- test results of the dc capactor voltage of H 1 n u-phase. actual dc capactor voltage. detected dc capactor voltage. (c) error between detected value and actual value. Fg.13- tested result of dc mean capactor voltage. by tradtonal SMV detector by mproved SMV detector ISSN: Issue 1, Volume 9, January 2010

9 n the case of delay tme chosen 90µ s. Waveform of actual dc capactor voltage s shown n Fg.12. The detected dc capactor voltage vdcu1 by mproved SMV detector s shown n Fg.12. The error between them s shown n Fg.12(c). Fg.13 shows the waveform of detected dc mean capactor voltage by tradtonal SMV detector and mproved SMV detector separately. When the system samplng frequency and carrer frequency are fxed, delay tme determnes the accuracy of SMV detector. Delay tme could be nether too long nor too short. In order to descrbe the accuracy of detecton, we ntroduce an ndex average voltage error rate as v dc vdc / vdc. Fg.14 demonstrates the relatonshp between the average voltage error rate and the delay tme about. Fg.14 shows comparson of the average voltage error rate test results of v usng tradtonal SMV and mproved SMV. It s observed from Fg.14 that the mproved SMV detector gets more accuracy value than tradtonal SMV detector. dc 6.2 Performance of the CHB-based STATCOM Steady state System operaton n steady state s tested, and some of the results are shown n Fg.15. Fg.15 shows that the system current su and voltage v su are almost n same phase when STATCOM absorbs reactve power from the system.fg.15 shows STATCOM u-phase output current. v Su v Cu Su Average dc capactor voltage erro rate (%) The delay tme (us) v Su cu Average dc capactor voltage error rate (%) The delay tme (us) SMV mproved SMV Fg.14- average error rate of detected voltage average dc capactor voltage error rate of comparson of the average voltage error rate test results of mproved SMV vdc usng tradtonal SMV and Fg.15- Expermental waveforms n steady state. source voltage(lne-neutral) v, nverter output voltage (lne-neutral) v Cu source voltage(lne-neutral) output current Cu. Su, and the source current Su. and STATCOM vsu Dynamc state Fg.16 shows expermental results of dynamc response when STATCOM was started. It can be seen that, t has an excellent dynamc response wth a step change from zero to 1800VA. Fg.17 shows the dynamc response of the CHBbased STATCOM wth a step change of the command from capactve to nductve and vce ISSN: Issue 1, Volume 9, January 2010

10 versa. Fg.18 shows varaton of dc capactor voltages (four dc capactor voltages n u-phase and v-phase) when ndvdual balancng control s enabled. Intally, the dc capactor voltages are unbalanced due to the dfferent power losses of H-brdge unts, but when the ndvdual balancng control s actvated, the voltage balance s acheved n 0.2s. cu v Su s proposed. For the CHB-based STATCOM, wth the mproved SMV detecton technology, dc capactor voltage detecton only need three voltage sensors, all ndvdual H-brdge dc capactor voltage can be detected accurately, at the same tme, more accurate dc mean capactor voltage can be got In addton, the mplement method s ntroduced, take nto account delay tme n detecton crcut and control crcut, the delay tme may produce a bad effect on the accuracy of detected value, the author propose a delay technology, whch play an mportant role n promotng practcal applcaton of SMV detecton technology. The valdty of the mproved SMV detector s proved by the expermental results, and excellent performance of the CHB-based STATCOM are obtaned wth decoupled current control and voltage balancng control strateges. Fg.16- Expermental waveforms when STATCOM was started cu v Su Fg.17- dynamc response for a step change n the command from capactve to nductve Fg.18- The varaton of dc capactor voltages when ndvdual balancng control was enabled 7 Concluson In ths paper, an mproved sngle multlevel voltage (SMV) detector based on CHB-based STATCOM Acknowledgements Ths work was supported by 973 project n Chna (2005CB221505) References: [1] F. Z. Peng, J-S La, Dynamc performance and control of a statc var generator usng cascade multlevel nverters, IEEE Trans. Ind. Appl., Vol.33, No.3, 1997, pp [2] Chen. B.-S and Yuan-Yh Hsu, An Analytcal Approach to Harmonc Analyss and Controller Desgn of a STATCOM, IEEE Trans. Power Del., Vol.22, No.1, 2007, pp [3] C.Schauder, H. Mehta, Vector analyss and control of advanced statc VAR compensators, Proc. Inst. Elect. Eng. C, 1993 pp [4] Sternberger.R and Jovcc.D, Theoretcal Framework for Mnmzng Converter Losses and Harmoncs n a Multlevel STATCOM, IEEE Trans. Power Del., Vol.23, No.4, 2008 pp [5] N.C. Sahoo, B.K. Pangrah, P.K. Dashb, G. Panda, Multvarable nonlnear control of STATCOM for synchronous generator stablzaton, Electr. Power Energy Syst., 26, 2004, pp [6] Y. Lang, and N. C.O, A new type of STATCOM based on cascadng voltage-source nverters wth phase-shfted unpolar SPWM IEEE Trans. Ind. Appl., Vol.35, No.5, 1999, pp [7] F. Z. Peng, J-S La, J.W. McKeever. and J. VanCoeverng, A multlevel voltage-source nverter wth separate DC sources for statc var ISSN: Issue 1, Volume 9, January 2010

11 generaton, IEEE Trans. Ind. Appl., Vol.32, No.5, 1996, pp [8] Xangyun Fu, Janze Wang and Yanchao J, A Novel STATCOM Based on Cascaded Threephases Voltage Source Inverter, Proc. IEEE.32th.Annu. Ind. Electron.Spec.Conf, 2006, pp [9] J. Rodrguez, S. Bernet, B. Wu, J. Pontt, and S. Kouro, Multlevel voltage-source-converter topologes for ndustral medum-voltage drves, IEEE Trans. Ind. Electron., Vol.54, No.6, 2007, pp [10] McGrath, B.P, Holmes, D.G, Analytcal Modellng of Voltage Balance Dynamcs for a Flyng Capactor Multlevel Converter, IEEE Trans. Power Electron., Vol.23, No.2, 2008, pp [11] F. Z. Peng, J.W. McKeever, and D.J. Adams, A power lne condtoner usng cascade multlevel nverters for dstrbuton systems, IEEE Trans. Ind. Appl., Vol.34, No.6, 1998, pp [12] L.M.Tolbert, J.N.Chasson, and F.Z.Peng, Modulaton ndex regulaton of a multlevel nverter for statc var compensaton, Proc. Power Eng. Soc, 2003, pp [13] Barrena J.A, Marroyo.L, Vdal M.A.R, and Apraz J.R.T, Indvdual voltage balancng strategy for PWM cascaded H-Brdge converter-based STATCOM, IEEE Trans. Ind. Electron., Vol.55, No.1, 2008, pp [14] H. Akag, S. Inoue, and T. Yosh, Control and performance of a transformerless cascade pwm STATCOM wth star confguraton IEEE Trans. Ind. Appl., Vol.43, No.4, 2007, pp [15] Y. L and B. Wu, A novel DC Voltage Detecton Technque n the CHB Inverter- Based STATCOM, IEEE Trans. Power Del., Vol.23, No.3, 2008, pp ISSN: Issue 1, Volume 9, January 2010