A method to reduce DC-link voltage fluctuation of PMSM drive system with reduced DC-link capacitor

Transcription

1 Internatonal Conference on Advanced Electronc Scence and Technology (AEST 2016) A method to reduce DClnk voltage fluctuaton of PMSM drve system wth reduced DClnk capactor a Ke L, Y Wang, Hong Wang and Danyang Bao Power Electroncs and Electrcal Drves Research Center, Harbn Insttute of Technology Shenzhen Graduate School, Shenzhen, Chna Abstract. The reducton of the dclnk capactance n the motor drve makes t possble to mprove the system power densty and lower the system cost. However, ths can lead to relatvely hgh dclnk voltage fluctuaton, especally the sxth harmonc component. To serve the purpose of enhancng the dclnk voltage qualty, a parameternsenstve control method was proposed n ths paper. The proposed method shapes the sxth harmonc component of the dclnk current n phase wth that of the nductor current by the HF power njecton technology. Snce ths practce can reduce the dfference between these two sxth harmonc components, the sxth harmonc component of the dclnk voltage can be reduced as well. The smulaton results show that the proposed method not only mproves the rpple characterstc of dclnk voltage, but also acheves the am of PMSM speed regulaton. Keywords: DClnk capactor; permanent magnet synchronous motor (PMSM); power njecton; voltage fluctuaton; voltage source nverter (VSI). 1 Introducton Permanent magnet synchronous motors (PMSMs) have attractve advantages, such as hgh effcency, hgh precson, hgh torque to nerta rato, and hgh power densty, ganng wdespread acceptance n varous applcatons [12]. In conventonal motor drve, large electrolytc capactors are usually nstalled to mantan constant dclnk voltage, whch occupy consderable space and ncrease the system cost. Gven these ssues, a lot of efforts have been spent to reduce or mnmze the dclnk capactance. In [34], the dclnk capactance was reduced to a very small value, and both the motor speed regulaton and the nput power factor mprovement were acheved by controllng the nverter output power. In [5], a new current njecton crcut together wth a current control method were proposed for the motor drve system wth small dclnk capactor, and such practce makes t possble to meet the standard of nput harmonc current for motor drve. It s worth notng that the sgnfcant reducton of dclnk capactance can result n the nstablty problem, a dclnk voltage stablty method based on actve dampng was presented n [6] accordngly, ncreasng the system stablty. Actually, under the precondton of stable system, the dclnk voltage fluctuaton caused by the reducton of dclnk capactance s stll relatvely hgh, whch s worth nvestgatng as well. Therefore, BonGwan Gu proposed a control method to lmt the dclnk voltage varaton n a converternverter system wth a Correspondng author : wangy_htsz@163.com, lke_htsz@163.com The authors Publshed by Atlants Press 918

2 reduced dclnk capactor [7], whch was based on the drectly control of dclnk capactor current. Snce ths method requres a controllable frontend rectfer, t cannot be appled to the doderectferbased system. Unlke the practce n [7], the dclnk voltage fluctuaton was suppressed by only regulatng the motor reactvely power n [8]. Such prncple can be used for reference n the doderectferbased system. However, ths method looks somewhat complex and depends on the knowledge of motor parameters. Ths study focuses on the dclnk voltage fluctuaton problem of the topology whch conssts of a threephase dode rectfer, an LC flter wth reduced capactor, and a voltage source nverter (VSI). Then, a novel control method, whch s ndependent of motor parameters, s proposed. Usng the proposed method, the dfference between the sxth harmonc component of ndctor current and that of the dclnk current s reduced. Also, the dclnk voltage fluctuaton s reduced accordngly. Smulaton results are provded to confrm the feasblty and effectveness of the presented method. 2 Drve system confguraton and problem descrpton 2.1 Drve system confguraton The PMSM drve system wth reduced dclnk capactor s shown n Fg. 1, whch s equpped wth a sxpulse dode rectfer, an LC flter wth reduced capactor, and a VSI. In such system, the combnaton of the VSI and the PMSM can be smply consdered as an equvalent load of the frontend crcut [6, 9]. In order to understand the characterstcs of the equvalent load, the model of the PMSM should be establshed frst. For smplcty, the PMSM s commonly modelled n the dq reference frame, and the correspondng equatons are gven by u q u d dt d d = Rd + Ld ωelqq (1) dq = Rq + Lq + ω eldd + ωeψ f (2) dt 3 p e = ( udd + uqq ) (3) 2 Where u d and u q are the d and qaxes stator voltages, d and q are the d and qaxes stator currents, R s the stator resstance, L d and L q are the d and qaxes stator nductances, ω e s the electrcal angular speed, ψ f s the permanent magnet flux lnkage, and p e s the electrc power of the PMSM, respectvely. Under conventonal feldorented control, the steadystate stator currents ( d and q ) as well as the electrcal angular speed can be regarded as constant. Then, t follows from (1) to (3) that the electrc power of the PMSM, p e, can also be regarded as constant. Further, neglectng the power loss of the VSI, the nput power of the VSI and the electrc power of the PMSM can be consdered equvalent, and hence, the aforementoned equvalent load can be modelled as a constant power load [9]. In ths case, the PMSM drve system n Fg. 1 usng conventonal feldorented control can be smplfed accordngly, as shown n Fg

3 L dc L C Reduced capactor + u dc PMSM Fgure 1. PMSM drve system wth reduced dclnk capactor. L dc L C Reduced capactor + u dc Constant power Load (p e ) Fgure 2. Smplfed model for system wth reduced dclnk capactor under conventonal feldorented control. 2.2 Problem descrpton Typcally, the dodes n the sxpulse rectfer are alternately turned on and off. Therefore, the dclnk voltage u dc can suffer some harmoncs, especally the harmonc wth sx tmes the grd frequency. In ths paper, the dclnk capactor s reduced, whch can save the space and the cost of the drve system. However, t makes the cutoff frequency of the LC flter hgher than sx tmes the grd frequency. In other words, provded that the dclnk capactor s reduced, the sxth harmonc problem of the dclnk voltage wll become more sgnfcant. To clearly demonstrate the relatonshp between the dclnk voltage and the dclnk capactance, Fg. 3 shows the dclnk voltages under the same constant power load (p e =2kW) wth dfferent dclnk capactances. It can be seen that the smaller the capactance, the hgher the voltage rpple s. Ths means that, the voltage fluctuaton n the drve system wth reduced dclnk capactor s relatvely hgh. Furthermore, snce the voltage rpple s the man factor causng the temperature rse of the capactor, t should be suppressed n the drve system wth reduced dclnk capactor. Fgure 3. DClnk voltages wth dfferent dclnk capactances. 920

4 3 Proposed control method for reducng voltage fluctuaton 3.1 Prncpe of reducng voltage fluctuaton In the PMSM derve system, the dclnk capactor current c, whch lead to a dclnk voltage fluctuaton, can be expressed by the nductor current L and the dclnk current dc, namely, du C dt dc c = = L dc (4) It mples that to deal wth the dclnk voltage fluctuaton problem the dfference between L and dc should be reduced. Furthermore, because the domnant harmonc component of dclnk voltage s sxth harmonc component, the sxth harmonc current dfference between L and dc wll be only concerned n ths paper. Neglectng the power loss of the VSI, p e can also be descrbed as p = u (5) e dc dc Therefore, the sxth harmonc component of dc can be controlled by njectng hgh frequency (HF) components nto p e. In ths case, smlar to the smplfcaton shown n Fg. 2, the PMSM and the VSI can also be modeled as an equvalent load whose power s p e. However, due to the HF power njecton, the motor electrc power p e s no longer constant, and some HF components are nvolved n t. Then, the equvalent load can be consdered as a combnaton of the constant power load and adjustable HF power load, as demonstrated n Fg. 4. Fgure 4. Smplfed model for system wth reduced dclnk capactor under HF power njecton. Furthermore, t follows from (3) that the HF power njecton for p e (.e., the adjustable HF power load n Fg. 4) can be mplemented by adjustng the qaxs stator current of PMSM. Hence, no addtonal crcut s requred for ths power njecton. In the studed drve system, the reduced dclnk capactor stll have relatvely strong energy decouplng effect, the adjustment to sxth harmonc component of dc has lttle nfluence on that of L. In ths case, the purpose of reducng the sxth harmonc current dfference between L and dc can be served by shapng the sxth harmonc component of dc n phase wth that of L. Further, the sxth harmonc voltage wll be reduced accordngly. As the shapng of the sxth harmonc component of dc depends on the HF components of motor electrc power, the nput power requrement of VSI to shape the sxth harmonc component of dc wll be analyzed n the followng sectons. 3.2 Input power requrement of VSI The dclnk current dc after shapng can be expressed as (6), whch s composed of the DC component dc0 and the shaped sxth harmonc component dc6. 921

5 = + (6) dc dc0 Moreover, as aforementoned analyss, dc6 should be shaped n phase wth the sxth harmonc component of L to reduce the related harmonc component of dclnk voltage. Namely, dc6 can be gven by dc6 L6 dc6 = k (7) Where k (0<k<1) s the correspondng gan coeffcent, L6 s the sxth harmonc component of L. Then, equaton (6) can be rewrtten as dc = + k (8) dc0 Further, substtutng (8) nto (5), the power of the equvalent load n Fg. 4 can be descrbed as e dc dc0 L6 p = u ( + k ) 6 (9) Based on (9) and the domnant harmonc component of u dc, t can be deduced that sxth harmonc power and twelfth harmonc power are manly contaned n the HF components of the desred p e. As the twelfth harmonc power s relatvely small compared to the sxth harmonc power, t s reasonable to consder only the sxth harmonc power durng the power control. L 3.3 Confguraton of the proposed control scheme Accordng to the PMSM mathematcal model and the prevous dscusson, a control scheme for reducng dclnk voltage fluctuaton s proposed n ths paper, whch takes nto account two purposes: the PMSM speed regulaton and the reducton of dclnk voltage harmonc component. The detaled confguraton of the presented control scheme s shown n Fg. 5. L ω m + ω m BPF L 6 PI k dc0 dc + + p e + u dc dc6 NR PI p = 1.5( u + u ) e d d q q d + + q Current vector control u q u d dq αβ u β u α L SVPWM + u dc dc NR: 2krωcs 2 s + 2ω s + ω c 2 6 d q dq αβ θ e α β αβ abc a b PMSM Fgure 5. PMSM drve system wth proposed control scheme. In the proposed control scheme, due to the relatvely hgh njected frequency of the motor electrc power and the smoothng effect of mechancal nerta, the mpact of the HF power njecton on the motor speed ω m can be neglected. Ths means that the HF components are almost not contaned n the speed error, and hence, the output of speed regulator s desgned as a DC form dc0,.e., the command of dc0. Based on prevous dscusson, the reducton of dclnk voltage fluctuaton can be acheved by shapng the sxth harmonc component of dc n phase wth that of L. Consequently, the command of 922

6 dclnk current sxth harmonc component dc6 s determned by a gan coeffcent and L6 generated from the bandpass flterng of L. Then, combnng the sxth harmonc component command dc6 and the DC component command dc0, the dclnk current command that meet condton (8) s obtaned. Further, asssted by the nformaton of u dc, the power command p e for the reducton of dclnk voltage fluctuaton s obtaned as well. After ths, the power, whch manly contans DC component and sxth harmonc component, s regulated by the power controller. In detal, the DC power component s regulated accordng to the proportonal plus ntegral (PI) controller, whle the sxth harmonc power component s regulated accordng to the nondeal resonant (NR) controller [10] whose resonant frequency s desgned as ω 6 (.e., sx tmes the grd frequency). From such power regulaton, the qaxs current command q s generated. Then, the correspondng voltage commands are provded by the closedloop control of current vectors. Fnally, based on the coordnate transformaton and space vector pulse wth modulaton (SVPWM), the desred duty cycles of the VSI are gven. In a word, wth the ad of the closedloop control of motor speed and reasonable HF power njecton, the purposes of speed regulaton as well as the reducton of dclnk harmonc voltage can be attaned. It can be observed from Fg. 5 that the presented method can be realzed wthout the support of motor parameters, and thus, t s nsenstve to motor parameters. Moreover, t s worth mentonng that the dea of reducng voltage fluctuaton n the proposed control scheme can provde reference for other smlar systems wth reduced dclnk capactor. 4 Smulaton results To verfy the performance of the proposed control method for reducng dclnk voltage fluctuaton, a smulaton model of the PMSM drve system wth reduced dclnk capactor was bult n MATLAB/Smulnk, usng the parameters lsted n Table 1. Based on the establshed model, a seres of smulaton tests were performed. Table 1. Smulaton model parameters Parameter Grd phase voltage/frequency DC sde nductance L Value 220 V (rms)/50 Hz 0.35 mh DClnk capactance C 235 µf Motor pole pars 4 Motor stator resstance R Motor nductances (L d /L q ) Motor permanent magnet flux lnkage 0.6 Ω 5.1 mh/14.3 mh 0.17 V.s Fg. 6 shows the motor speed response wth 8 N.m load torque when the speed command 2000 r/mn s gven, and the correspondng motor electrc power s shown n Fg. 7. The speed response ndcates that the proposed method has well capablty of regulatng motor speed. Moreover, accordng to the steadystate motor electrc power and motor speed, t can be known that the HF njecton for the motor electrc power does not cause obvous HF speed rpples. Therefore, the PMSM speed control performance s guaranteed, although the system dclnk capactor s reduced. 923

7 Fgure 6. Motor speed waveform for the proposed method wth 8 N.m load torque. Fgure 7. PMSM electrc power for the proposed method at 2000 r/mn wth 8 N.m load torque. Fgure 8. Sxth harmonc current dfference comparson under p e =2.0 kw. Fgure 9. DClnk voltage comparson under p e =2.0 kw. 924

8 In order to demonstrate that the proposed scheme can reduce the voltage fluctuaton of the motor drve system wth reduced dclnk capactor, the conventonal feldorented control method (hereafter referred to as conventonal method) and the proposed method were performed under the same condton (.e., p e =2.0 kw), respectvely, and the results were shown n Fg. 8 and Fg. 9. It can be seen from these curves that, under the control of conventonal method, the dfference between L6 and dc6 s 7.2 A (ampltude), and the dclnk voltage rpple s 39.3 V; under the control of proposed method, the dfference between L6 and dc6 s reduced to 4.2 A (ampltude), and the dclnk voltage rpple s reduced to 27.9 V, accordngly. Ths confrms that the reasonable shapng of dclnk current by power regulaton can reduce the dclnk voltage fluctuaton. In other words, the method n ths paper s feasble. In addton, to further demonstrate the performance of the proposed method, the dclnk voltage rpples of the conventonal PMSM control method and the proposed method are summarzed n Fg. 10. From ths comparson, t can be seen that the voltage rpple of the proposed method s lower than that of the conventonal method regardless the DC component of motor electrc power. Ths also ndcates that the system wth reduced dclnk capactor s stable. Fgure 10. DClnk voltage rpples comparson between conventonal method and the proposed method. In short, these smulaton tests confrm that the proposed control scheme can not only regulate the motor speed but also mprove the rpple characterstc of the dclnk voltage. 5 Conclusons In ths paper, the dclnk voltage fluctuaton problem n a PMSM drve system wth reduced dclnk capactor has been nvestgated, and the VSI power condton of reducng ths voltage fluctuaton has been analyzed accordngly. Based on the deduced power condton, a novel control method to reduce the dclnk voltage rpple has been proposed. The proposed method s ndependent of motor parameters. Smulaton results confrm that the presented approach can meet the requrements of both the PMSM speed regulaton and the reducton of dclnk voltage fluctuaton. Acknowledgments Ths work was supported by the Shenzhen Scence and Technology Plan Project under Grant JCYJ

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