Characteristics of New Single Phase Voltage Doubler Rectifier Circuit using the Partial Switching Strategy

Transcription

1 IEEE PEDS 217, Honolulu, USA December 217 Characterstcs of New gle Phase Voltage Doubler Rectfer Crcut usng the Partal Swtchng Strategy Kenj Ame Akto Kumaga Takahsa Ohj Kyohe Kyota Masaak Saku Unersty of Toyama, JAPAN Abstract- In ths paper, the new partal swtchng sngle phase oltage doubler rectfer crcut whch can mproe effcency drastcally s proposed. The partal swtchng crcut s crcut to realze boost and harmonc reducton, hgh effcency n a good balance. The proposed crcut s dfferent from conentonal crcut [1] n the pont that component of the partal swtchng s connected to DC sde. Because current flowed through the dfferent dode n partal swtchng and commutaton n conentonal crcut, the effcency dropped. Because current flows through the same dode wth both stuatons n proposed crcut, the effcency s mproed. Wth dsposton to the DC sde of the component of the partal swtchng, the dode whch preented the short crcut of the capactor was necessary. But, the drop of the effcency was suppressed at the mnmum by operatng two MOS-FET as synchronous rectfcaton. The operatng characterstc was nspected n experment, and t was ealuated boost, harmonc current and effcency. Whle equal performance about boost and harmonc current s mantaned, 2-3% of effcency was mproed n comparson wth conentonal crcut [1]. In ths paper, crcut confguraton and a prncple of operaton, expermental results are reported. I. INTRODUCTION Inerter crcut s used to realze a conenent functon and superor performance n recent household electrc applance. Because nerter crcut s the crcut whch conerts DC oltage nto AC oltage, a rectfer crcut to conert nto DC oltage from oltage of the commercal power supply s necessary. The conentonal rectfer crcut was manly passe crcut composed of only some dodes. Howeer, ths crcut exhausted much harmonc current and had harmful effect on an electrc power system. Therefore the acte method whch controlled current n the shape of a snusodal wae by usng hgh-frequency swtchng was proposed. Ths acte method soled a harmonc problem, but much swtchng losses occurred, and effcency lowered. As a result, partal swtchng strategy hang the mddle performance of a passe method and the acte method was proposed. Features of ths method s to be able to realze harmonc suppresson and boost, reducton of the loss only wth lttle swtchng number of tmes. Therefore t was adopted to products such as ar condtoner or the refrgerator wdely. The bdrectonal swtch s connected to the AC sde n the conentonal partal swtchng rectfer crcut [1]. When the bdrecton swtch s turned on, nput oltage s shunted through an nductor, and nput current rses up early. As a result, harmonc current s suppressed. Howeer, effcency dropped because current flowed through the seeral dfferent dodes at the tme of short crcut of the nductor and the charge of the capactor. In ths paper, the new partal swtchng rectfer crcut whch greatly mproes effcency s proposed. Ths crcut s composed of a rectfer crcut and a partal swtchng crcut, but the partal swtchng crcut s connected to DC sde [2]. The current flowng at the tme of short crcut of the nductor and the charge of the capactor flows through the same dode. The loss to occur wth a dode hereby was greatly reduced. Two dodes for preenton of short crcut of the capactor were necessary, but they were replaced wth two MOS- FETs, and the loss whch occurred wth the dodes were reduced by synchronous rectfcaton. The operatng characterstc of ths crcut was nspected by experment. Here, crcut confguraton and the prncple of operaton, the expermental results are reported. II. MAIN CIRCUIT CONFIGURATION AND CONTRO PRINCIPE <2.1> Man crcut confguraton Fg.1 shows confguraton of the man crcut to propose. Ths crcut s composed of oltage doubler rectfer crcut and a partal swtchng crcut. The 1 Fg.1 Man crcut confgulaton of the proposed crcut R out /17/$ IEEE 1,17

2 Input oltage Pulse duraton t * mono mult mono mult dead tme Fg.2 Control block dagram oltage doubler rectfer crcut s composed by dode D p, D n and DC capactor C p, C n. A partal swtchng crcut s composed by two MOS-FET S p, S n and nductance. Two MOS-FET S p1, S n1 are used for synchronous rectfcaton and preenton of short crcut of capactor C p, C n. <2.2> Control block dagram Fg.2 shows control block dagram. Ths block dagram s composed of mnmum component to nspect an operatng characterstc of the crcut of Fg.1. At frst nput oltage s detected by PT connected wth n AC sde, and t s conerted nto the rectangular wae of duty 5% by a zero cross comparator. At the tme of poste half cycle of the nput oltage, the rsng edge of the rectangular wae s sent to monostable multbrator, and a pulse of the pulse duraton of t* s output. and * (* means nerson and s the same as an upper bar ( ) ) of the gate pulse of two MOS-FETs S p and S p1 n poste sde are output through dead tme crcut. At the tme of negate half cycle of the nput oltage, the fallng edge of the rectangular wae s sent to monostable multbrator, and a pulse of the pulse duraton of t* s output. and * of the gate pulse of two MOS- FETs S n and S n1 n negate sde are output through dead tme crcut. The pulse duraton of poste sde and negate sde must be equal, because a DC component does not occur n nput AC current. In addton, the pulse duraton of t* can be set by a potentometer optonally. <2.3>Four modes of operaton Ths crcut has four modes of operaton shown below. (1)Mode 1: Input oltage >, s charged. Then S p and S n1 are on, and S p1 and S n are off. The current flow s shown n Fg 3.1, when the nput oltage s poste and S p s turned on. The power supply s shunted through, and the nput current ncreases n gradent of 1/. The current flows from C p and C n connected n seres through load R. (2) Mode 2: Input oltage >, s dscharged Then S p1 and S n1 are on, and S p and S n are off. The current flow s shown n Fg 3.2, when nput oltage s poste and S p s turned off. Magnetc energy charged by s charged through S p1 to C p. The nput current decreases n gradent of 1/. The current flowng through S p1 flows backward not a bult-n dode of S p1 by synchronous 1 Fg.3.1 Current flow of Mode 1 1 Fg.3.2 Current flow of Mode 2 1 Fg.3.3 Current flow of Mode 3 S p1 D p S p C p D n S n C n S n1 Fg.3.4 Current flow of Mode 4 R R R R R R R R 1,18

3 rectfcaton n MOS-FET. The current flows from C p and C n connected n seres through load R. (3) Mode 3: Input oltage <, s charged. Then S p1 and S n are on, and S p and S n1 are off. The current flow s shown n Fg 3.3, when the nput oltage s negate and S n s turned on. The power supply s shunted through, and the nput current decreases n gradent of 1/. The current flows from C p and C n connected n seres through load R. (4) Mode 4: Input oltage <, s dscharged. Then S p1 and S n are on, and S p and S n1 are off. The current flow s shown n Fg 3.4, when the nput oltage s negate and S n s turned off. Magnetc energy charged by s charged through S n1 to C n. The nput current ncreases n gradent of 1/. The current flowng through S n1 flows backward not a bult-n dode of S n1 by synchronous rectfcaton n MOS-FET. The current flows from C p and C n connected n seres through load R. III. SIMUATION RESUT Fg 4 shows result of the smulaton. These waeforms are nput oltage, nput current, output oltage out, gate pulse,, *, * (* means nerson and s the same as an upper bar ( ) ) from the top. Input oltage s 1Vrms. And, reactor s 7mH, both capactor C p, C n s 2,μF. Input oltage 1-1 Input current 2-2 Output oltage out Gate pulse, On Off Gate pulse, On Off 2 4 tme t [ms] Fg.4 Smulaton Result (t*=2.6ms, R =5Ω) and of the gate pulse turn nto on from the zero cross pont of the nput oltage. And they contnue on-state between reference alue t* of the pulse duraton. *, * are the waeforms whch reersed, each. Pulse duraton t* of ths tme s 2.6ms, and resstance of the loads s 5 Ω. In addton, between and *, and *, dead tme s nserted not to be turned on at the same tme. It was confrmed that nput current began to flow mmedately from the moment when and of the gate pulse were turned on. When and swtch to off from on, the ncrease of the current stops and decreases slowly. Output oltage out changes from 27V to 29V wth a change of the current. Output power of ths tme was 1.6kW, and 98.% of effcency and 98.4% of power factors were obsered. IV. EXPERIMENTA RESUT The experment was carred out usng proposed crcut shown n Fg. 5. ecfcaton of ths crcut s shown n Table 1. In the experment, waeform of the nput oltage, output oltage out and nput current were obsered n condton same as smulaton of Fg. 4. The obsered waeform s shown n Fg. 6. Commercal oltage of 1V s used as electrc source and ncludes few dstortons. The nput current s a waeform n synchronzaton wth oltage waeform. It s confrmed that nput current begns to flow from the zero cross pont of the oltage. The output oltage waeform fluctuates n the range of 28V~29V. W 1 P.F. Input Comp. oltage Pulse duraton t * 74HC123 74HC123 Mono. Mult. 1 Dead Tme W 2 Fg.5 Man crcut confguraton for experment R out Table 1 ecfcatons of the element Element Symbol Type ecfcaton Dode, 6RI75G 12V 75A MOSFET, 1,, TK16W 6V 1A 15mΩ Reactor 7mH, 3A Capactor, 22μF, 45V Input oltage 1Vrms Input frequency f 6Hz oad resstance R 5Ω ~ 1,19

4 Output power of ths tme was 1.41kW, and 97.3% of effcency and 98.8% of power factors were obsered..7% of effcency and.4% of power factors decreased n comparson wth smulaton. When pulse duraton t* of S p and S n changed from to 3.ms, the characterstcs of the output oltage, the power factor, the effcency wth the change of the load resstance was obsered. Output oltage characterstcs s shown n Fg. 7. The output oltage tends to gradually decrease wth ncrease of the output power. In addton, t was confrmed that output oltage rose when pulse duraton was ncreased. Therefore, when pulse duraton s regulated to a change of the electrc power, the output oltage can be mantaned n the range of approxmately 25V - 3V. Fg. 8 shows power-factor characterstc. The power factors tend to ncrease wth ncrease of the output power. In addton, t was confrmed that a power factor decreased n low power output when pulse duraton was ncreased. When pulse duraton s gradually regulated to a change of the electrc power, hgh power factors more than 98% were proded for loads more than.9kw. Fg. 9 shows effcency characterstcs. Effcency [V] [A] out [V] Input oltage [V] 1-1 Input current [A] 2-2 out Output oltage out [V] decreased wth ncrease of the output power, but hgh effcency more than 97% was confrmed n rated 1.5kW by choosng optmum pulse duraton to follow an enelope. Ths s hgh effcency to exceed 2-3% of conentonal partal swtchng sngle phase oltage Power factor PF[pu] Effcency η [%] ms 2.4ms2.6ms 3.ms Output power W 2 [W] Fg.8 Power-factor characterstc 2.ms 2.4ms 2.6ms 3.ms Fg.6 Input oltage, current and output oltage waeform 4 Output Voltage V out [V] ms 2.4ms 2.ms 3.ms Output power W 2 [W] Fg.7 Output oltage characterstcs Harmonc current alue Ih[A] Output power W [W] 2 Fg.9 Effcency characterstcs #3 #5 #7 #9 #11 #13 #15 #17 #19 #21 #23 #25 Harmonc order (W 2 =1.5kW) Fg.1 Harmonc alue of nput current (W 2=1.5kW) 1,11

5 doubler rectfer crcut [1]. Fg. 1 shows harmonc content of the nput current. Power consumpton of the loads of ths tme s 1.5kW. Harmonc content from the 3rd to the 25th when pulse duraton t* changed from to 3.ms s expressed n bar graphs. The most snstral graph of each order expresses stated harmoncs regulaton alue n "Gudelne to reduce harmonc emsson caused by electrcal and electronc equpment for household and general use" [4]. The rght bar graph expresses a change of the harmonc content for the ncrease of the pulse duraton from there. It s confrmed that all order s suppressed by less than regulaton alue. V. CONCUSION New crcut confguraton of the partal swtchng sngle phase oltage doubler rectfer crcut was proposed. The operatng characterstcs were nspected by experment. The loss whch occurred n dodes was reduced by a partal swtchng crcut connected to DC sde. In addton, two dodes for preenton of short crcut was replaced wth a MOS-FET, and hgh effcency more than 97% was realzed by operatng t as synchronous rectfcaton. It s nestgated deraton method of optmum pulse duraton to realze boost, reducton of the harmonc current, hgh effcency n a good balance n future [3]. REFERENCES [1] M. Uesug, H. kkanazawa, A. Hruma, H. Myazak, and T. kanbe, gle-phase Twce oltage PFC Conerter for ar condtoner, Trans. IEE Japan, ol. 119-D, No.5, pp (1999) [2] I. Suga, M. Kmata, R. Uchda, A Smple Swtchng Method for A Improed Power Factor Type gle Phase Conerter, Trans. IEE Japan, ol. 116-D, No.4, pp (1996) [3] M. Saku, H. Yong, K. Ame, T. Ohj, A Method of 2 Pulse Swtchng for gle-phase Voltage-Double PFC Conerter wth Partal Swtchng Crcut, IEEJ Trans. Ind. Appl., ol. 131, No.6, pp (211) [4] IEC SC77A Japanese Natonal Commttee, Gudelne to reduce harmonc emsson caused by electrcal and electronc equpment for household and general use, Japanese erson (21) 1,111