IEE Electronics Letters, vol 34, no 17, August 1998, pp ESTIMATING STARTING POINT OF CONDUCTION OF CMOS GATES

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1 IEE Electroncs Letters, vol 34, no 17, August 1998, pp ESTIMATING STARTING POINT OF CONDUCTION OF CMOS GATES A. Chatzgeorgou, S. Nkolads 1 and I. Tsoukalas Computer Scence Department, 1 Department of Physcs Arstotle Unversty of Thessalonk Thessalonk, Greece Indexng terms: Modellng, CMOS gates, tmng smulaton Abstract In order to model effectvely the output waveform and the propagaton delay of a CMOS gate, the knowledge of the tme pont when t starts conductng s essental. An effcent method for calculatng analytcally ths pont takng nto account the structure of the gate and the nput waveform s ntroduced. Such a method can be easly ntegrated n a tmng analyss system. I. Introducton Realstc smulaton of dgtal crcuts requres the estmaton of the tme pont when the output node of a gate starts chargng/dschargng. CMOS gates consst of parallel and seral transstor structures. For the analyss of complex gates, technques are used for mappng them to equvalent NAND/NOR structures and performng the analyss at ths level or they proceed further and reduce the resulted structures to an equvalent nverter [1]. In addton to ths transstor structure manpulaton, all possble nputs to a gate have to be mapped to an

2 effectve sngle equvalent ramp [2]. Consequently, n order to develop accurate models of the gate behavor, t s vtal to calculate accurately the exact tme pont when parallel or seral connected transstors, whch receve the same nput, start conductng. Parallel transstor structures are trval to handle, snce the startng pont of conducton of the parallel group s the same to that of a sngle transstor (tme pont when the nput becomes equal to the threshold voltage). However, the calculaton of the startng pont for the seral transstor structure (transstor chan) s more complcated and depends, apart from the nput slope and threshold voltage, on the number of the transstors, the parastc couplng and node capactances, the body effect, the transstor's drvablty and the supply voltage. The effect of all these factors has to be captured by a closed mathematcal expresson that can be ncorporated n exstng gate models. II. Analyss In a transstor chan wth ntally dscharged nternal nodes and the same nput ramp (wth transton tme ô) appled to the gates of all transstors (Fg. 1a), the closer to the output transstors start conductng later because of a gradual ncrease n ther source and threshold voltage. Let us consder the example of a sx nmos transstor chan through whch the output load s dscharged. The analyss for a pmos transstor chan s symmetrcal. Fg. 2b shows a smplfed representaton of the actual dran voltages of the fve lower transstors shown n Fg. 2a. Because of couplng capactance between transstor gates and the dran/source nodes, dran voltages tend to follow the nput ramp untl all lower transstors start conductng. Intally the transstors are n the cut-off regon and the couplng 2

3 capactance, C M, s calculated as the sum of the gate-to-source and gate-to-dran overlap capactance of the upper and lower transstor respectvely, at each node. Untl the tme when the transstor below the -th node starts conductng, the voltage waveform at that node, V [t], as t s solated between two cut-off transstors, s derved by equatng the current due to the couplng capactance of the node, I CM, wth the chargng current of the parastc node capactance I C : C M dv dv n dt C dv C = V t = dt C C V t n + M [] [] M (1) ( t s ) After the tme at whch all transstors below the -th node start conductng and untl the tme at whch the complete chan starts to conduct (t on ), ths node s subject to two opposte trends. One tends to pull the voltage of the node hgh and s due to the couplng capactance between nput and the node and s ntense for fast nputs and hgh couplng to node capactance rato. The other tends to pull ts voltage down because of the dschargng currents through all lower transstors and s more ntense for nodes closer to the ground. When a transstor starts to conduct, e.g. transstor #, t operates ntally n saturaton. Therefore, snce ts gate-to-dran couplng capactance s very small, the second (except for the case of very fast nputs where, however, the requrement for accuracy s relaxed snce the value of t on remans small) from the above mentoned trends domnates after tme t s decreases (Fg. 2). Ths contnues untl tme t s+1 and the voltage at node when transstor #+1 starts conductng and enters saturaton. Transstor #, snce ts V GS contnues to ncrease after tme t s whle ts V DS decreases, wll enter the lnear regon close to t s+1. From ths pont on, the gate-to-source couplng capactance of transstor #+1 3

4 ncreases by ( 2/ 3) C WL and the gate-to-dran couplng capactance of transstor ox # ncreases by ( 12 / ) C WL. Because of ths ncreased couplng capactance at ox node #, the two prevously mentoned trends are counterbalanced and for smplcty the node voltage s consdered constant and equal to ts value at t s+1. Ths observaton has also been verfed by SPICE smulatons (Fg. 2a). The node voltages start to rse agan when the complete chan starts conductng at tme t on. Addtonally, the slope of the voltage waveform durng [ t s, t +1 ] s consdered the same for each node and the voltage expresson of node 1 durng ths perod can be calculated by solvng the dfferental equaton whch results from the applcaton of Krchhoff's current law at node 1 (Fg. 1b) : a dv dv n = k ( V V ) = C n1 C C s n TO M M dt dt 1 s C dv 1 (2) 1 dt where the transconductance k s s measured on the I-V DS characterstcs and V TO s the zero bas threshold voltage. For smplcty the velocty saturaton ndex á whch s mposed by the á-power law model [3], s consdered one, whch s a reasonable approxmaton for submcron devces. Snce t = VTO ô s1 s known and V V 1 [ t s 1 ] DD V 1 [t] durng [ ts t 1 s2] s gven by eq. (1), the expresson of, s derved and can be used n order to calculate the tme, t s2, when the next transstor further up n the chan starts conductng, by solvng [ ] [ ] V t V t GS2 s2 TN2 s2 waveform durng [ t = 0. Consequently, the average slope r of each node voltage s, t +1 ] can be obtaned. In order to ncorporate the body s 4

5 effect n the analyss the threshold voltage s approxmated by a frst order Taylor seres around V SB =1V as è+ äv SB, where V SB s the source to substrate voltage. Fnally, the tme pont at whch transstor # n the chan starts conductng can be found by solvng : [ ] [ ] [ ] è ( ä) V - [ ] V t V t = V t 1+ t = 0 (3) GS s TN s n s 1 s C M where V [ t ] V [ t ] r ( t t = 1 s n s s s ) C M + C whch results n the recursve expresson : t s = ( 1 ä) è+ + C CM V ô DD M 1 + C ( 1 ä) V ô DD + + r + r t s, 2 (4) From the above expresson, the tme at whch the chan starts conductng, t on = t, can be easly obtaned. Accordng to the prevous analyss, the startng s n pont of conducton can be calculated wth very good accuracy for a wde range of nput transton tmes as shown n Fg. 3 whch s a comparson between the calculated and the actual tme t on obtaned from SPICE smulatons for a 0.5 mcron technology. 5

6 REFERENCES [1] J.-T. Kong, S.Z. Hussan and D. Overhauser, "Performance Estmaton of Complex MOS Gates", IEEE Trans. on Crcuts and Systems - I: Fundamental Theory and Applcatons, 1997, vol. 44, no. 9, pp [2] A. Chatzgeorgou and S. Nkolads, "Input Mappng Algorthm for Modellng of CMOS Crcuts", IEE Electroncs Letters, 1998, vol. 34, no. 12, pp [3] T. Sakura and A. R. Newton, "Alpha-Power Law MOSFET Model and ts Applcatons to CMOS Inverter Delay and Other Formulas", IEEE J. Sold- State Crcuts, 1990, vol. 25, no. 2, pp

7 LIST OF CAPTIONS Fg. 1: (a) nmos Transstor chan and (b) Currents at node # of the transstor chan durng [ t, t s s +1 ] Fg. 2: (a) Actual ntermedate node voltage waveforms and (b) smplfed representaton Fg. 3: Comparson between smulated and calculated startng pont of conducton for (a) 4-transstor chan (W=4ìm) and (b) 6-transstor chan (W=9ìm) 7

8 (a) (b) Fg. 1: (a) nmos Transstor chan and (b) Currents at node # of the transstor chan durng [ t, t s s +1 ] Vn V5 V oltage V4 V3 0.2 V2 V Tme (ns) (a) (b) Fg. 2: (a) Actual ntermedate node voltage waveforms and (b) smplfed representaton 8

9 2.5 Sm ulated ton Calculated ton Startng pont of conducton (ton) n ns b a Input transton tme (ns) Fg. 3: Comparson between smulated and calculated startng pont of conducton for (a) 4-transstor chan (W=4ìm) and (b) 6-transstor chan (W=9ìm) 9