High Speed, Low Power And Area Efficient Carry-Select Adder

Transcription

1 Internatonal Journal of Scence, Engneerng and Technology Research (IJSETR), Volume 5, Issue 3, March 2016 Hgh Speed, Low Power And Area Effcent Carry-Select Adder Nelant Harsh M.tech.VLSI Desgn Electroncs and Communcaton Department SRM unversty, Chenna Taml Nadu Mrs.V.Sarada Asst.prof (Sr.grade) Electroncs and Communcaton Department SRM unversty, Chenna Taml Nadu Abstract- Low power, area effcent and hgh performance VLSI system are used n portable and moble devces, wreless recevers, and bomedcal nstrumentaton An adder s the man component of an arthmetc unt. A complex dgtal sgnal processng (DSP) system nvolves several adders. An effcent adder desgn essentally mproves the performance of a complex DSP system. general types of adder are RCA,Conventonal CSLA, BEC-Based CSLA. Carry Select Adder (CSLA) s one of the fastest adders used n many data-processng processors to perform fast arthmetc functons. From the structure of the CSLA, t s clear that there s scope for reducng the area and power consumpton n the CSLA. Ths work uses a smple and effcent gate-level modfcaton to sgnfcantly reduce the area and power of the CSLA. the logc operaton nvolved n conventonal carry select adder (CSLA) and bnary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to dentfy redundant logc operatons. We have elmnated all the redundant logc operatons present n the conventonal CSLA and proposed a new logc formulaton for CSLA. In ths method we use dfferent sub modules half sum generaton,carry generaton-0,carry generaton-1,carry selecton and full sum generaton and the carry select (CS) operaton s scheduled before the calculaton of fnal-sum, due to ths crcut wll generate small delay, less power and less area. Index Terms- Adders, Bnary Excess Converter (BEC), Carry Select Adder (CSLA), Logc gates. I. Introducton Desgn of area- and power-effcent hgh-speed data path logc systems are one of the most substantal areas of research n VLSI system desgn. Concatenatng the N full adders forms N bt Rpple carry adder. In ths carry out of prevous full adder becomes the nput carry for the next full adder. It calculates sum and carry accordng to the followng equatons. As carry rpples from one full adder to the other, t traverses longest crtcal path and exhbts worstcase delay. S C 1 A B where = 0, 1,, n-1 A B C A B FIG:1 Rpple carry adder C RCA s the slowest n all adders (O (n) tme) but t s very compact n sze (O (n) area). If the rpple carry adder s mplemented by concatenatng N full adders, the delay of such an adder s 2N gate delays from Cn to Cout. The delay of adder ncreases lnearly wth ncrease n number of bts. Block dagram of RCA s shown n fgure 1. In dgtal adders, the speed of addton s lmted by the tme requred to propagate All Rghts Reserved 2016 IJSETR 806

2 Internatonal Journal of Scence, Engneerng and Technology Research (IJSETR), Volume 5, Issue 3, March 2016 a carry through the adder. The sum for each bt poston n an elementary adder s generated sequentally only after the prevous bt poston has been summed and a carry propagated nto the next poston. The CSLA s used n many computatonal systems to allevate the problem of carry propagaton delay by ndependently generatng multple carres and then select a carry to generate the sum [1]. However, the CSLA s not area effcent because t uses multple pars of Rpple Carry Adders (RCA) to generate partal sum and carry by consderng carry nput Cn=0 and Cn=1 then the fnal sum and carry are selected by the multplexers (mux). The basc dea of ths work s to use Bnary to Excess-1 Converter (BEC) nstead of RCA wth Cn=1 n the regular CSLA to acheve lower area and power consumpton [2] [4]. The man advantage of ths BEC logc comes from the lesser number of logc gates than the n-bt Full Adder (FA) structure. proposed a square-root (SQRT)-CSLA to mplement large bt-wdth adders wth less delay. In a SQRT CSLA, wth ncreasng sze are connected n a cascadng structure. The man objectve of SQRT- CSLA desgn s to provde a parallel path for carry propagaton that helps to reduce the overall adder delay. Ramkumar and Kttur [6] suggested a bnary to BEC-based CSLA. The BEC-based CSLA nvolves less logc resources than the conventonal CSLA, but t has margnally hgher delay. A CSLA based on common Boolean logc (CBL) s also proposed n [7] and [8]. The CBL-based CSLA of [7] nvolves sgnfcantly less logc resource than the conventonal CSLA but t has longer CPD, whch s almost equal to that of the RCA. To overcome ths problem, a SQRT-CSLA based on CBL was proposed n [8]. However, the CBL-based SQRTCSLA desgn of [8] requres more logc resource and delay than the BEC-based SQRT-CSLA of [6]. We observe that logc optmzaton largely depends on avalablty of redundant operatons n the formulaton, whereas adder delay manly depends on data dependence. In the exstng desgns, logc s optmzed wthout gvng any consderaton to the data dependence. In ths bref, we made an analyss on logc operatons nvolved n conventonal and BEC-based CSLAs to study the data dependence and to dentfy redundant logc operatons. Based on ths analyss, we have proposed a logc formulaton for the CSLA. The man contrbuton n ths bref are logc formulaton based on data dependence and optmzed carry generator (CG) and CS desgn. Based on the proposed logc formulaton, we have derved an effcent logc Fg:2 conventonal CSLA II. Exstng System To reduce the area and power consumpton Bnary Excess-1 converter nstead of RCA wth Cn = 1. To reduce delay compared to regular SQRT CSLA. To replace the n-bt RCA, an n+1 bt BEC s requred. A structured and the functon table of a 4-b BEC are shown n fg 3, respectvely. Fg 4 llustrates how the basc functon of the CSLA s obtaned by usng the 4-bt BEC together wth the mux. One nput of the 8:4 mux gets as t nput (B3,B2,B1,and B0) and another nput of the mux s the BEC output. Ths produces the two possble partal results n parallel and the mux s used to select ether the BEC output or the drect nputs accordng to the control sgnal cn. The Boolean expressons of the 4-bt BEC s lsted as[5] 0 ~ B 0 B 1 0 B1 2 B B & B B B3 B0 & B1 & FIG:3 BEC-1(Bnary to exces-one convertor) crcut 2 All Rghts Reserved 2016 IJSETR 807

3 Internatonal Journal of Scence, Engneerng and Technology Research (IJSETR), Volume 5, Issue 3, March 2016 FIG:4 Block Dagram of BEC-1 Based CSLA FIG: 5 Block dagram of SQRT CSLA III. PROPOSED ADDER DESIGN Desgn conssts of one HSG unt, one FSG unt, one CG unt, and one CS unt. The CG unt s composed of two CGs (CG0and CG1) correspondng to nput-carry 0 and 1. The HSG receves two n- bt operands (A and B) and generate half-sum and half-carryword c 0 of wdth n-bts each. Both CG0 and CG1 receve s 0 and c 0 from the HSG unt and generate two n-bt full-carry words c0 1 and c1 1 correspondng to nput-carry 0 and 1, respectvely. The logc dagram of the HSG unt s shown n Fg. 5. The logc crcuts of CG0and CG1are optmzed to take advantage of the fxed nput-carry bts. The optmzed desgns of CG0and CG1are shown n Fg. 6 and 7, respectvely.of s0(i )and c0(),for0 n 1. Ths feature s used for logc optmzaton of the CS unt. The optmzed desgn of the CS unt s shown n Fg.8, whch s composed of n AND OR gates. The fnal carry word c s obtaned from the CS unt. The MSB of c s sent to output as Cout, and (n 1) LSBs are OR wth(n 1)MSBs of half-sum(s0)n the FSG [shown n Fg.9] to obtan(n 1)MSBs of fnalsum(s).thelsbofs0sored wth Cn to obtan the LSB of s.[1] Fg:6 Sub Modules of Proposed CSLA All Rghts Reserved 2016 IJSETR 808

4 Internatonal Journal of Scence, Engneerng and Technology Research (IJSETR), Volume 5, Issue 3, March 2016 Fg:7 half sum generaton Fg:10 carry selecton Unt Fg:8 carry generaton-0 Fg:11 full sum generaton Fg:9 carry generaton -1 Fg:12 Smulated result of SQRT CSLA All Rghts Reserved 2016 IJSETR 809

5 Internatonal Journal of Scence, Engneerng and Technology Research (IJSETR), Volume 5, Issue 3, March 2016 Fg:13 synthesze result of SQRT CSLA s used for logc optmzaton of the CS unt. Fxed nput bts of the CG unt are also used for logc optmzaton. Based on ths, an optmzed desgn for CS and CG unts are obtaned. Usng these optmzed logc unts, an effcent desgn s obtaned for the CSLA. A smple approach s to reduce the area and power of CSLA archtecture. The reduced number of gates of ths work offers the great advantage n the reducton of area and also the power. The modfed CSLA archtecture s, low area, low power, smple and effcent for VLSI hardware mplementaton. IV. Performance Comparson We have coded the SQRT-CSLA n VHDL usng the proposed CSLA desgn and the exstng CSLA desgns of [6] and [7] for bt-wdths 16. All the desgns are syntheszed n the xlnx tool. TABLE 1 Comparson of BEC-based CSLA and SQRT-CSLA Parameter BEC-based CSLA(16-bt) SQRT-CSLA (16-bt) Delay(ns) 5.99(ns) 5.73(ns) No of Slce LUT's used Total slce LUT'S present Number of bonded I/O's used Total Number of bonded I/O's present Power(mW) 82.16(mW) 77.23(mW) Concluson the logc operatons nvolved n the conventonal and BEC-based CSLAs to study the data dependence and to dentfy redundant logc operatons. We have elmnated all the redundant logc operatons of the conventonal CSLA and proposed a new logc formulaton for the CSLA. In the proposed scheme, the CS operaton s scheduled before the calculaton of fnal-sum, whch s dfferent from the conventonal approach. Carry words correspondng to nput-carry 0 and 1 generated by the CSLA based on the proposed scheme follow a specfc bt pattern, whch References [1] Basant Kumar Mohanty, Senor Member, IEEE, and Sujt Kumar Patel "Area Delay Power Effcent Carry-Select Adder" IEEE Transactons On Crcuts And Systems I: Express Brefs, Vol. 61, No. 6, June 2014 [2] K.K.Parh,VLSI Dgtal Sgnal Processng. New York, NY, USA: Wley,1998. [3] A. P. Chandrakasan, N. Verma, and D. C. Daly, Ultralow-power electroncs for bomedcal applcatons, Annu. Rev. Bomed. Eng., vol. 10, pp , Aug [4] O. J. Bedrj, Carry-select adder, IRE Trans. Electron. Comput.,vol. EC-11, no. 3, pp , Jun [5] Y. Km and L.-S. Km, 64-bt carry-select adder wth reduced area, Electron. Lett., vol. 37, no. 10, pp , May [6] Y. He, C. H. Chang, and J. Gu, An area-effcent 64-bt square root carry select adder for low power applcaton, nproc. IEEE Int. Symp. Crcuts Syst., 2005, vol. 4, pp [7] B. Ramkumar and H. M. Kttur, Low-power and area-effcent carry-select adder, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp , Feb [8] I.-C. Wey, C.-C. Ho, Y.-S. Ln, and C. C. Peng, An area-effcent carry select adder desgn by sharng the common Boolean logc term, nproc. IMECS, 2012, pp [9] S. Manju and V. Sornagopal, An effcent SQRT archtecture of carry select adder desgn by common Boolean logc, nproc. VLSI ICEVENT, 2013, pp [10] B. Parham, Computer Arthmetc: Algorthms and Hardware Desgns, 2nd ed. New York, NY, USA: Oxford Unv. Press, All Rghts Reserved 2016 IJSETR 810