POWER constraints are a well-known challenge in advanced

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1 A Smple Yet Effcent Accuracy Confgurable Adder Desgn Wenbn Xu, Student Member, IEEE, Sachn S. Sapatnekar, Fellow, IEEE, and Jang Hu, Fellow, IEEE Abstract Approxmate computng s a promsng approach for low power IC desgn and has recently receved consderable research attenton. To accommodate dynamc levels of approxmaton, a few accuracy confgurable adder desgns have been developed n the past. However, these desgns tend to ncur large area overheads as they rely on ether redundant computng or complcated carry predcton. Some of these desgns nclude error detecton and correcton crcutry, whch further ncreases area. In ths work, we nvestgate a smple accuracy confgurable adder desgn that contans no redundancy or error detecton/correcton crcutry and uses very smple carry predcton. Smulaton results show that our desgn domnates the latest prevous work on accuracy-delay-power tradeoff whle usng 9% lower area. In the best case the so-delay power of our desgn s only 6% of accurate adder regardless of degradaton n accuracy. One varant of ths desgn provdes fner-graned and larger tunablty than the prevous works. Moreover, we propose a delay-adaptve self-confguraton technque to further mprove accuracy-delaypower tradeoff. The advantages of our method are confrmed by the applcatons n multplcaton and DCT computng. Index Terms Approxmate computng, accuracy confgurable adder, delay-adaptve reconfguraton, low power desgn. I. INTRODUCTION POWER constrants are a well-known challenge n advanced VLSI technologes. Low power technques for the conventonal exact computng paradgm have been already extensvely studed. A comparatvely new drecton s approxmate computng, where errors are ntentonally allowed n exchange for power reducton. In many applcatons, such as audo, vdeo, haptc processng and machne learnng, occasonal small errors are ndeed acceptable. Such error-tolerant applcatons are found n abundance n emergng applcatons and technologes. A great deal of approxmate computng research has been concentrated on arthmetc crcuts, whch are essental buldng blocks for most of computng hardware. In partcular, several approxmate adder desgns have been developed [] []. One such desgn [] acheves 6% power reducton for DCT (Dscrete Cosne Transform) computaton wthout makng any dscernble dfference to the mages beng processed. In realstc practce, accuracy requrements may vary for dfferent applcatons. In moble computng devces, dfferent Ths work was partally supported by NSF (CCF-559, CCF-5579 and CCF-5595). W. Xu and J. Hu are wth the Department of Electrcal and Computer Engneerng, Texas A&M Unversty, College Staton, TX, 778 USA (emal: wbxu@tamu.edu; janghu@tamu.edu). S. S. Sapatnekar s wth the Department of Electrcal and Computer Engneerng, Unversty of Mnnesota, Mnneapols, MN, 5555 USA (emal: sachn@umn.edu). power modes may ental dfferent accuracy constrants even for the same applcaton. Specfcally, arthmetc accuracy can be adjusted at runtme usng methods such as dynamc voltage and frequency scalng (DVFS) to obtan the best accuracypower tradeoff. The beneft of runtme accuracy adjustment s demonstrated n [], but ther approxmaton s realzed by voltage over-scalng, where errors mostly occur at the tmngcrtcal path assocated wth the most sgnfcant bts,.e., errors are often large. To reduce the overall error, a few approxmate desgns have been developed by ntentonally allowng errors n lower bts wth shorter carry chan n addton operaton. In [], a desgn that consders only the prevous k nputs nstead of all nput bts can approxmate the result wth the beneft n half of the logarthmc delay. Relable varable latency carry select adder (VLCSA) shows a speculaton technque whch ntroduces carry chan truncaton and carry select addton as a bass [7]. A seres of Error Tolerant Adders (ETAI, ETAII, ETAIIM), whch truncate the carry propagaton chan by dvdng the adder nto several segments, have been proposed [8] []. Correlaton-aware speculatve adder (CASA) n [] reles on the correlaton between MSBs of nput data and carry-n values. Another approxmate adder that explots the generate sgnals for carry speculaton s presented []. These desgns focus on statc approxmaton whch pursues almost correct results at the requred accuracy. However, n some applcatons such as mage processng or audo/vdeo compresson, the requred accuracy mght vary durng runtme. To meet the need of runtme accuracy adjustment, a seres of desgns are developed to mplement accuracy confgurable approxmaton whch could be reconfgured onlne to save more power. A few accuracy confgurable adder desgns that use approxmaton schemes other than voltage over-scalng have been proposed. An early work [5], called ACA, starts wth an approxmate adder and augments t wth an error detecton and correcton crcut, whch can be confgured to delver varyng approxmaton levels or accurate computng. Its baselne approxmate adder contans sgnfcant redundancy and the error detecton/correcton crcut further ncreases area overhead. The ACA desgn [5] s generalzed to a flexble framework GeAr n [6]. In both ACA and GeAr, the error correcton must start from the least sgnfcant bts and hence accuracy mproves slowly n the progresson of confguratons. The work of Accurus [7] modfes ACA/GeAr to overcome ths drawback and acheves graceful degradaton. However, n ACA, GeAr as well as Accurus, the error correcton crcut s ppelned, mplyng that the computaton n accurate mode takes multple clock cycles and causes data stalls.

2 An alternatve drecton of accuracy confgurable adder desgn s represented by [8] and RAP- [9]. These methods start wth an accurate adder and use carry predcton for optonal approxmaton. As such, they no longer need error detecton/correcton and do not ncur any data stall. In addton, they ntrnscally support graceful degradaton. The desgn [8] s composed by accurate (Carry Rpple Adder) and extra confgurable carry predcton crcutry, smlar as the carry look-ahead part of (Carry Look-ahead Adder). Thus, ts area s generally qute large. RAP- [9] s based on accurate desgn and reuses a porton of the carry look-ahead crcut as carry predcton. Ths leads to an overall area that s less than but greater than. In [9], the carry-predcton-based approach s shown to be superor to error-correcton-based desgn [6]. In ths paper, we propose a new carry-predcton-based accuracy confgurable adder desgn: SARA (Smple Accuracy Reconfgurable Adder). It s a smple desgn wth sgnfcantly less area than, whch, to the best of our knowledge, has not been acheved n the past n accuracy confgurable adders. SARA nherts the advantages of all prevous carry-predctonbased approaches: no error correcton overhead, no data stall and allowng graceful degradaton. Compared to [8], SARA ncurs 5% less PDP (Power Delay Product) and can reach the same PSNR (Peak Sgnal-to-Nose Rato). Moreover, SARA demonstrates remarkably better accuracy-power-delay tradeoff than the latest, and arguably the best, prevous work RAP- [9]. A delay-adaptve reconfguraton technque s developed to further mprove the accuracy-power-delay tradeoff. The proposed desgns are also valdated by multplcaton and DCT computaton n mage processng. II. PRIOR WORKS AND RATIONALE OF OUR DESIGN We revew a few representatve works on accuracy confgurable adder desgn and show the relaton wth our method. These desgns can be generally categorzed nto two groups: error-correcton-based confguratons [5] [7] and carrypredcton-based confguratons [8], [9]. a[:] b[:] a[9:] b[9:] a[7:] b[7:] Approxmate Adder Sub adder Sub adder Sub adder s[:] s[9:8] s[7:] Ppelne Stage Error Correcton Approxmate result Fg.. Error-correcton-based confgurable adder. Ppelne Stage Error Correcton Accurate result The man dea of an error-correcton-based approach [5] [7] s shown n Fgure. The scheme starts wth an approxmate adder (the dashed box), where the carry chan s shortened by usng separated sub-adders wth truncated carry-n. In order to reduce the truncaton error, the bt-wdth n some sub-adders contans redundancy. For example, subadder calculates the sum for only bt 8 and 9, but t s an 8-bt adder usng bt [9 : ] of the addends, 6 bts of whch are redundant. Even wth the redundancy, there s stll resdual error whch s detected and corrected by addtonal crcuts. In Fgure, the errors of sub-adder must be corrected by error-correcton before the errors of sub-adder are rectfed by error-correcton. As such, the confguraton progresson always starts wth small accuracy mprovements. The redundancy and error detecton/correcton ncur large area overhead. Snce the error correcton crcuts are usually ppelned, an accurate computaton may take multple clock cycles and could stall entre datapath, dependng on the addend values. c s[:] Confg Confg s[7:] Confg Confg s[:8] Carry predct Carry predct Sub-adder Sub-adder c c7 a[:] b[:] Mux a[7:] b[7:] Fg.. Carry-predcton-based confgurable adder. Mux Sub-adder a[:8] b[:8] The framework of carry-predcton-based methods [8], [9] s shown n Fgure. These schemes start wth an accurate adder desgn, whch s formed by channg a set of subadders. Each sub-adder comes wth a fast but approxmated carry predcton crcut. By selectng between the carry-out from sub-adder or carry predcton, the overall accuracy can be confgured to dfferent levels. Such an approach does not need error detecton/correcton crcutry. Moreover, the confguraton of hgher bts s ndependent of lower bts. Ths leads to fast convergence or graceful degradaton n the progresson of confguratons. In [8], the sub-adders are desgns whle the carry-predcton crcut s smlar to the carry look-ahead part of. Further, ts carry predcton can be confgured to dfferent accuracy levels. However, the complcated carry predcton nduces large area overhead. The RAP- scheme [9] uses for ts baselne where the carry-ahead of each bt s computed drectly from the addends of all of ts lower bts. Its carry predcton reuses a part of the look-ahead crcut rather than buldng extra dedcated predcton crcutry, and hence s more area-effcent than. But ts baselne s much more expensve than. TABLE I COMPARISON OF CHARACTERISTICS FOR DIFFERENT TECHNIQUES. Baselne Error Graceful Carry Method sub-adder correcton degradaton predcton ACA [5] Redundant Yes No No GeAr [6] Redundant Yes No No Accurus [7] Redundant Yes Yes No [8] No Yes Stand-alone RAP- [9] No Yes Reuse SARA (ours) No Yes Reuse Our desgn s a carry-predcton-based approach. Its subadders are nstead of expensve as n RAP-. Its carry predcton also reuses part of the sub-adders rather c

3 MUX MUX than havng dedcated predcton crcutry. As such, t avods the dsadvantages of both and RAP-. A comparson among the characterstcs of these dfferent technques s provded n Table I. III. SIMPLE ACCURACY RECONFIGURABLE ADDER A. Prelmnares An N-bt adder operates on two addends A = (a N, a N,, a,, a ) and B = (b N, b N,, b,, b ). For bt, ts carry-n s c and ts carry-out s c. Defnng the carry generate bt g = a b, propagate bt p = a b and kll bt k = ā b, the conventonal full adder computes the sum s and carry c accordng to s = p c, () c = g + p c. () A gate level schematc of conventonal full adder s provded n Fgure (a). A s used to chan N bts of conventonal full adders together. c p s a g b c c p s a g b prdt c c ˆ c c a (a) (b) (c) Fg.. (a) Conventonal full adder; (b) Our carry-out selectable full adder; (c) Our carry-n confgurable full adder. By applyng Equaton () recursvely, one can get c = g + p g g p k + c p k. () k= p s k= Ths equaton mples that c can be computed drectly from g and p of all bts, wthout watng for the c of ts lower bts to be computed. Ths observaton s the bass for adder. g b B. SARA: Smple Accuracy Reconfgurable Adder Desgn In SARA, an N-bt adder s composed by K segments of L-bt sub-adders, where K = N/L (see Fgure ). Each sub-adder s almost the same as except that the MSB (Most Sgnfcant Bt) of a sub-adder, whch s bt, provdes a carry predcton as c prdt = g () For the LSB (Least Sgnfcant Bt) of the hgher-bt sub-adder, whch s bt +, ts carry-out c + can be computed usng one of two optons: ether by the conventonal c + = g + + p + c, or by usng the carry predcton as c + = g + + p + c prdt = g + + p + g (5) c The selecton between the two optons s realzed usng MUXes as n Fgure and the MUX selecton result s denoted as ĉ. Comparng Equaton (5) wth (), we can see that the carry predcton s a truncaton-based approxmaton to carry computaton. Therefore, ĉ can be confgured to ether accurate mode or approxmaton mode,.e., ĉ { c prdt, f approxmaton mode c, f accurate mode. It should be noted that the carry predcton c prdt reuses g n an exstng full adder nstead of ntroducng an addtonal dedcated crcut as n [8] or Fgure. Ths predcton scheme makes a very smple modfcaton to the conventonal full adder, as shown n Fgure (b). One can connect ĉ to ts hgher bt + to compute both carry c + and sum s +, as n [8] and RAP- [9]. We suggest an mprovement over ths approach by another smple change as n Fgure (c), where s + s based on c nstead of ĉ. Such approach can help reduce the error rate n outputs when an ncorrect carry s propagated. Because the sum keeps accurate and the carry wll not be propagated when addends are exactly the same. Moreover, out of all four confguratons of sum/carry calculaton by approxmate/accurate carry-n, the most meanngful way s to have sum bt calculated by accurate carry and make carry bt confgurable. So sum s + s calculated drectly by accurate carry c wthout the opton of c prdt. Applyng ths n SARA as n Fgure, n the approxmaton mode, computng s j+ from c j can stll lmt the crtcal path to be between c prdt and s j+, but has hgher accuracy than computng s j+ from ĉ j. Compared to sum computaton n and RAP-, ths technque mproves accuracy wth almost no addtonal overhead. Compared to, the overhead of SARA s merely the MUXes, whch s almost the mnmum possble for confgurable adders. LSB prdt c cˆ a ~ j b ~ prdt c j c c j Sub-adder Sub-adder Sub-adder s ~ j Fg.. Desgn of SARA. j ĉ j MSB Although s j+ s calculated by accurate carry c j, ts delay can stll be reduced by approxmate carry n lower sub-adder. In a mult-bt adder, the delay of sum bt depends on the carry chan propagated from ts lower bts. In our SARA structure, even when accurate carry c j s propagated at bt j, the carry chan mght be truncated by approxmate carry n other lower bts. In Fgure, when c prdt s propagated, the delay of s j+ s reduced as ts path s shorten to be between bt and A smlar approxmaton s used n statc approxmate adder desgn []. (6)

4 MUX MUX j +. We can take the -bt adder n Fgure 5 as an example. For -bt SARA workng n approxmate mode, the sum s 9 uses the accurate carry c 8 from a lower sub-adder (bt 5 to 8). But c 8 s propagated from approxmate carry c prdt of another sub-adder (bt to ). As shown n the fgure, the delay of s 9 n SARA s about 6 stages. Compared wth the same bt n, the delay of sum bt s 9 n SARA s reduced by stages. Smlar delay reducton can be observed n other sum bts (bt 6 to ). For sums at bt to 5, ther delay s the same as because they are usng an accurate carry c from LSB. As a result, the maxmum delay n -bt SARA s reduced, snce for a mult-bt adder ts maxmum delay depends on the longest crtcal path. LSB s c c c 8 s s s 5 prdt c s s6 s7 s8 s9 s s s (a) prdt c 8 MSB c c c 8 s s s s s 5 s6 s7 s8 s9 s s s (b) SARA Fg. 5. Implementaton of -bt adder n (a) and (b) SARA. C. Usage of SARA When ĉ s confgured to be c for all K sub-adders, SARA operates very much lke the, where the crtcal path s along N-bt full adders. If all ĉ are selected to be c prdt, the crtcal path s shortened to roughly L-bt full adders. Ths large delay reducton can be translated to power reducton by supply voltage scalng. Voltage scalng (reducng supply voltage) on dgtal crcuts wll lead to ncrease n delay. So we can reduce the supply voltage on SARA to make ts crtcal delay same as that of under normal voltage. As the supply voltage decreases, the power consumpton could be reduced. There can be K dfferent confguratons. For two confguratons wth the same crtcal path length, obvously we only need the one wth hgher accuracy. Therefore, there are K effectve confguratons, wth crtcal path length of L- bt, L-bt,, K L N-bt full adders. The delay of such confgurable desgn vares accordng to confgured accuracy, whch results n dfferent power reducton by voltage scalng. IV. SARA ERROR ANALYSIS In ths secton, we gve a theoretcal analyss on the expected error of our SARA desgn and valdate the results by numercal experments. To make t easer for readers to follow the analyss, we lst the parameters used n ths secton as Table II. For any bt n carry-out selectable full adder as n Fgure (b), an error n approxmate carry-out occurs when c prdt TABLE II DEFINITION OF PARAMETERS FOR ERROR ANALYSIS Parameter Defnton p propagate bt at bt g generate bt at bt k kll bt at bt c accurate carry-out bt at bt c prdt approxmate carry-out bt at bt ĉ carry-n bt at bt + ER prdt error rate of c prdt ÊR error rate of ĉ c. There s only one stuaton where ths error may happen: when c =, p =, c prdt = and c =. Then the error rate, or probablty of such error, s gven by ER prdt = P (c prdt c ) = P (c prdt =, c = ) = P (c =, p = ) = P (c = )P (p = ) where P ndcates probablty and the last part assumes that c and p are ndependent of each other. Then, f the approxmate/accurate carry-out can be selected by a MUX gate, the error rate of MUX output ĉ s { ER prdt, f ĉ c prdt ÊR = P (ĉ c ) = (8), f ĉ c. Let s consder a confguraton of SARA n Fgure, whch has both bt j and bt n approxmate mode. For the sub-adder whch calculates addends from bt to bt j, ts LSB (bt ) s usng carry-n confgurable full adder, whle ts MSB (bt j) s n carry-out selectable full adder. Accordng to Equaton (7) and (8), the error rate of ĉ j s determned by the probabltes of c j = and p j =. (7) ÊR j = P (c j = )P (p j = ) (9) Accordng to the logc of addton, the carry-out bt s calculated by the carry-n and addends. There are two cases whch can result n c j = : generate bt g j should be n case of carry-n c j = ; or kll bt k j must be when carry-n comes wth c j =. Then, the probablty of c j = can be computed by the probablty of c j = as P (c j = ) = P (c j =, g j = ) + P (c j =, k j = ) = P (c j = )P (g j = ) + P (c j = )P (k j = ) = [ P (c j = )]P (g j = ) + P (c j = )P (k j = ). () Smlarly, the probablty of c j =, c j =,..., c + = can be calculated usng the same formula. For the probablty of c =, t s a lttle dfferent because the carry-out c n our carry-n confgurable full adder s based on predcted carry-n ĉ nstead of c. Consderng that bt s confgured n approxmate mode, we have P (ĉ = ) = P (c prdt = ) = P (g = ). () Then, the probablty of c = can be expressed as P (c = ) =[ P (g = )]P (g = ) + P (g = )P (k = ). ()

5 5 TABLE III ERROR RATE OF SUB-ADDER WITH DIFFERENT WIDTH Sub-adder length L Calculated error rate Smulated error rate /8 =.5.57 /6 = / = /6 = /8 = /56 = By expandng Equaton () recursvely tll bt, the probablty of c j = can be calculated by a functon of generate bt and kll bt from bt to bt j. P (c j = ) = f{p (g = ),..., P (g j = ), P (k = ),..., P (k j = )}. () Assumng that the nputs for adder are unformly dstrbuted random numbers, we have P (g = ) = /, P (k = ) = /. As the length of sub-adders vares from to 6, the error rates of ĉ j calculated by Equaton (9) are lsted n the second column of Table III. Correspondng data from numercal smulaton n Matlab are also presented n the last column. The error rates calculated by our method match well wth experment results, whch demonstrates the correctness of our mathematcal analyss. We can also observe that as the length of sub-adder ncreases the error rate s bounded by.5. That s because when the length of sub-adder comes to nfnte the probablty of c = wll become.5 as the normal carry n accurate adder. Theorem. If I s the set of bts wth MUX at output, the expected error of SARA for unsgned ntegers s ÊR P (p + = ) +. I Proof. The overall expected error of SARA can be calculated by summng respectve error ntroduced by every approxmate bt from LSBs to MSBs. But the propagaton of naccurate carry bt may cause error n hgher bt whch also be counted n the calculaton of lower bt. So we need to exclude those errors to avod over-calculaton n the total error. Let s consder the SARA desgn n Fgure whch have approxmate confguraton at both bt and bt j. Assumng that bt s the lowest bt confgured n approxmate mode, we know that all sum bts s k (k [, ]) as well as carry bt c are accurate. c = c acc () Then the probablty that carry predcton at MUX output ĉ msmatches wth accurate carry c acc should be the same as the error rate of max ouput ĉ. P (ĉ c acc ) = P (ĉ c ) = ÊR (5) Accordng to the structure of carry-n confgurable full adder (Fgure (c)), sum bt s calculated from c s always accurate; however, the carry-out bt c becomes condtonally accurate whch depends on both carry-n bt and propagate bt. As shown n Equaton (6), the scenaro of accurate carry-out can be attrbuted to two condtons: when the carry-n s not accurate, the carry-out bt becomes accurate as the propagate bt s false; otherwse, t must be accurate no matter what knd of addends are gven. P (c = c acc ) = P (ĉ = c acc ) + P (ĉ c acc )P (p = ) (6) Its complementary part, the probablty of naccurate carry c, can be expressed as P (c c acc ) = P (ĉ c acc )P (p = ) = P (ĉ c )P (p = ) = ÊR P (p = ). (7) As a result, the approxmaton at bt would cause an naccurate carry-n c at bt +, whch ntroduces the magntude of to the overall error n fnal result. Then the expected error ntroduced by approxmaton at bt can be estmated by E[e ] = P (c c acc ) = ÊR P (p = ). (8) Next, we consder the expected error ntroduced by approxmaton at bt j. As bt j s not the lowest bt n approxmate mode, there s a chance that the propagaton of naccurate carry from bt nduces error at bt j whle t has be taken nto account n the error calculaton of bt. Then the problem s whether the carry c j s accurate when there s a msmatch between ĉ j and c j. If not, we need to exclude the mpact from lower bt when estmatng the error at bt j. Let s answer ths queston n the followng cases. Case : If any propagate bt n sub-adder (bt to j) equals, the error propagaton by naccurate carry wll be paused. In another word, the error carred by naccurate carry bt cannot be propagated to hgher bt any more, because the carry-out s ndependent of carry-n when propagate bt s false. In ths case, the carry c j should be always accurate regardless of the confguraton at bt j. Case : If all propagate bts of sub-adder equal, the value of naccurate carry ĉ ( nstead of ) wll be propagated to c j. In ths stuaton, the actual value of c j propagated from bt must be, whle the accurate value should be. Assumng that ĉ j msmatches wth c j, we can state that the value of ĉ j must be. However, t conflcts wth the generaton of c j, because carry c j s the logcal conjuncton of ĉ j and p j c j. So there should be no msmatch between ĉ j and c j n ths case. In concluson, when there s a msmatch between ĉ j and c j, the value of carry c j must be accurate. We can further conclude that the contrbutons of every approxmate bt to the total error are ndependent to each other. Smlar to bt, the expected error at bt j can be estmated by E[e j ] = ÊR j P (p j+ = ) j+. (9) Thus, the total error can be obtaned by summng up the errors respectvely ntroduced by every approxmate bt. E = I E[e ] = I ÊR P (p + = ) + ()

6 MUX MUX 6 If nput addends are random varables followng unform dstrbuton, the expected error of SARA s gven by E = I ÊR. () a potentally long carry chan s detected. Compared to the constantly-approxmate confguraton, some errors for actual short carry chans are avoded, the actual long carry chan s cut shorter, and delay/power reducton can be stll obtaned. Detector Average Error Estmated Value Expermental Value LSB prdt c l c p ~ ĉ (a) a ~ b ~ Detecton wndow Detector a ~ l p ~ b ~ MSB 5 6 Number of Approxmate Bt Fg. 6. Average error of 9-bt SARA n dfferent confguraton. We can verfy Equaton () by numercal smulaton of a 9-bt SARA desgn. In our experment, SARA conssts of 9 sub-adders whose wdth s bt. The results are from K run of Monte Carlo smulaton wth unform dstrbuted numbers as nput. As shown n Fgure 6, there are sets of data for comparson, expermental data are obtaned drectly n experments and estmated data are calculated by Equaton (). The average errors from experment are almost the same as the estmated values. Accordng to the analyss above, we can estmate the average error of SARA n any confguraton, gven the dstrbuton of nput numbers. Snce I = K, the error of the worst case approxmaton mode ncreases wth the number of sub-adders, K. In addton, area overhead ncreases wth K. On the other hand, a large K mples smaller L, and thus often facltates shorter crtcal path and more power reductons. Therefore, K sgnfcantly affects the tradeoff among accuracy, power, delay and area. V. DELAY-ADAPTIVE RECONFIGURATION OF SARA Almost all prevous works on accuracy confgurable adder [5] [9] reasonably assume that accuracy confguraton s decded by archtecture/system level applcatons. We propose a self-confguraton technque for the scenaros where archtecture/system level choce s ether unclear or dffcult. Smulaton results show that SARA wth the self-confguraton outperforms several prevous statc approxmate adder desgns. The man dea of self-confguraton s based on the observaton that the actual worst case path delay depends on addend values. Specfcally, the actual path delay s large only when a carry s propagated through several consecutve bts. Any false propagate bt from the addends results n a shorter carry propagaton chan. When the actual carry propagaton chan s short, there s no need to use approxmaton confguraton, whch s ntended to cut carry chan shorter. We propose a Delay Adaptve Reconfguraton (DAR) technque: the output of a MUX n SARA s set to approxmaton mode only when 7 8 LSB prdt c c ĉ (b) Detecton wndow MSB Fg. 7. Desgn and operaton of delay-adaptve reconfguraton for SARA. The long carry chan detecton and SARA-DAR desgn are shown n Fgure 7(a). When MUX s swtched to accurate mode by any false propagate bt n detecton wndow, the actual carry chan s retaned by the poston of false propagate bt. To obtan a shorter carry chan n accurate mode, the detecton wndow for MUX at bt n MSB should start from bt +. In the example of Fgure 7, we use a detecton wndow of bts (p + and p + ) to tell f there s a carry propagaton across two sub-adders, and confgure the MUX accordng to ĉ { c prdt, f p + p + s true c, otherwse. () In approxmaton mode, the effectve carry chan s represented by the blue lne n Fgure 7(a) and ts length s no greater than L + bts. When the MUX s set to accurate mode, the carry chan s ndcated by the red lnes n Fgure 7(b) and ther lengths can be restraned to wthn L + bts. Snce the propagate bts only depend on local prmary nputs, we can reuse propagate bts n hgher bts to save cost. Note that n ths case the detecton overhead here s almost the mnmum possble,.e., only one NAND gate for confgurng each MUX. In Fgure 7, we use -bt detecton wndow, whch can be generalzed to W -bt. Then, the error rate for MUX at bt becomes ÊR dar = ER prdt W P (p +j = ) () j= The detecton wndow sze W decdes the tradeoff between accuracy and the effectve carry chan length n accurate mode, whch s L + W. When W ncreases, the error rate decreases whle the crtcal path length n accurate mode ncreases.

7 7 VI. EXPERIMENTAL RESULTS A. Experment Setup and Evaluaton Our SARA, SARA-DAR and several prevous desgns are syntheszed to -bt adders by Synopsys Desgn Compler usng the Nangate 5nm Open Cell Lbrary. The syntheszed crcuts are placed and routed by Cadence Encounter. The default supply voltage level s.5v. To make far comparsons across archtectures, we descrbe all desgns by structural modelng n Verlog to reduce the mpact of synthess and optmzaton. For comparson, we synthesze the accurate adder n behavoral modelng whch s descrbed by expressonal operator n Verlog. The netlst of such accurate adder should be automatcally optmzed by syntheszer n Desgn Compler, whch s dfferent from any man-craft gate-level desgn. In addton, we set the same supply voltage and no delay constrant on all desgns for the same reason. The evaluaton of accuracy confgurable adder desgns can be subtle and therefore s worth some dscusson. ) Area: In the lterature, the area sometmes refers to the part of the crcut workng n a certan mode, e.g., the crcut for the accurate part s not ncluded n area estmaton when evaluatng approxmaton mode. We report the routed layout area of each entre desgn. ) Delay: Some confgurable adders, such as ACA [5] and GeAr [6], mplement error correcton wth ppelnng, whch sometmes takes multple clock cycles to determne the complete result. The delay or performance evaluaton of such desgns s much more complcated than unppelned desgns. Our work s focused on unppelned mplementaton, although t can be ppelned. Thus, the reported delay s the maxmum combnatonal logc path delay obtaned from Synopsys PrmeTme wth consderaton of wre delay. ) Power: The power dsspaton s estmated by Synopsys PrmeTme consderng both statc and dynamc power. ) Accuracy: We use PSNR (Peak Sgnal-to-Nose Rato), where errors are treated as nose, as a composte accuracy metrc for consderng both error magntude and error rate. In addton, the worst case error, whch s equvalent to the maxmum error magntude [], and error rate are also reported. Each error result s from K-run Matlab-based Monte Carlo smulaton assumng unform dstrbuton of addends. 5) Tunablty: Ths means the range and granularty of runtme accuracy confguratons. Sometmes, ths can be confused wth desgn-tme flexblty. 6) Tradeoff: The tradeoff among the above factors s complex and s dffcult to capture n a smple pcture. To ths end, we use composte metrcs ncludng powerdelay product (PDP), energy-delay product (EDP) and so-delay power. B. Results of Tradeoff for Dfferent Confguratons In ths part, we manly compare the followng accuracy confgurable adder desgns: [8]: We use the same desgn as n [8], where each sub-adder has bts. Ths desgn can be confgured by choosng accurate or predcted carry-out for each subadder. The carry predcton at each segment can also be confgured to dfferent accuracy levels by usng dfferent number of lower-bt addends. RAP- [9]: We mplement four dfferent desgns wth carry predcton bt-wdth from bt to bts, whch s reflected n the name. For example, RAP- means each of ts carry predcton s from ts lower bts. As n [9], each desgn can be confgured to ether only one approxmaton mode or accurate mode. SARA: Ths s our proposed desgn and we evaluate subadder bt-wdth of bt, bts and 8 bts, referred to as SARA, and, respectvely. PSNR (db) 8 6 SARA 8 RAP- 6 RAP- RAP- RAP- 5 Power-Delay Product (ns*w) -5 Fg. 8. SARA: PSNR versus power-delay product. Average Error SARA RAP- RAP- RAP- RAP- 5 Power-Delay Product (ns*w) -5 Fg. 9. SARA: Average error versus power-delay product. The man result s shown n Fgure 8, where each pont s from one confguraton of one desgn. The computaton accuracy s evaluated by PSNR whle the conventonal desgn objectves are characterzed by PDP. A desgn and confguraton s deal f t has large PSNR but low PDP,.e., northwest n the fgure. PDPs of two classc accurate desgns, and, are ndcated by the two vertcal lnes as ther PSNR s near nfnty. The result of SARA workng n completely accurate mode s unable to be presented n the fgure, because ts nfnte PSNR cannot be dsplayed as a sngle dot n the plot. Evdently, the best solutons are from and

8 8 Worst Case Error 8 6 SARA RAP- RAP- RAP- RAP- 5 Power-Delay Product (ns*w) -5 PSNR (db) 8 6 SARA 8 RAP- 6 RAP- RAP- RAP- 5 6 Energy-Delay Product (ns*nj) -5 Fg.. SARA: The worst case error versus power-delay product. Fg.. SARA: PSNR versus energy-delay product.. At db PSNR, the PDP of and s about a half of or. The solutons from RAP-, the latest prevous work, are also largely domnated by SARA n PSNR-PDP tradeoff. An nterestng case s SARA. Its tradeoff s smlar as and not as good as or. However, ts runtme tunablty s superor to all the other desgns. It has the largest tunng range, the fnest tunng granularty and very smooth tradeoff. Fgure 9 and show the tradeoff between error magntude and power-delay product. Ideally a better desgn or confguraton has smaller average error or worst case error wth lower PDP, whch can be marked n the lower left corner of the fgure. In Fgure 9, and domnate other desgns n average error-pdp tradeoff. For each confguraton, and have almost the lowest average error at a certan PDP level. Although SARA cannot acheve superor average error and PDP tradeoff to, t shows fne-grant tunablty n a large range same as PSNR-PDP tradeoff. Fgures depcts the worst case error versus PDP and confrms the trend observed n the PSNR-PDP tradeoff. All SARA desgns even for SARA have lower worst case error than prevous work at the same PDP level. In addton, the result of SARA workng n accurate mode cannot be found n the plot. That s because the y-axs s n Logarthmc scale and zero error wll be converted nto nfnte whch cannot be dsplayed as a sngle dot. EDP s another metrc to effcently evaluate tradeoffs between crcut level power savng technques for dgtal desgns. Fgure to llustrate accuracy versus EDP, whch have smlar trend n accuracy-pdp tradeoff. Most confguratons of and have lower EDP than accurate adder and. At a certan EDP level, and stll domnate and RAP- wth larger PSNR, smaller average error or worst case error. SARA n dfferent confguratons cover the range from lowest to hghest EDP, whch provdes fnest tunablty n accuracy-energy tradeoff among dfferent archtectures. C. Results of Tradeoff for Delay-Adaptve Reconfguraton Ths part s to evaluate the SARA-DAR desgn, where the confguraton decson has already been made. Hence, t makes Average Error SARA RAP- RAP- RAP- RAP- 5 6 Energy-Delay Product (ns*nj) -5 Fg.. SARA: Average error versus energy-delay product. Worst Case Error 8 6 SARA RAP- RAP- RAP- RAP- 5 6 Energy-Delay Product (ns*nj) -5 Fg.. SARA: The worst case error versus energy-delay product. sense to addtonally compare wth statc approxmate adders, where no confguraton s needed. Statc approxmate adder desgns ncludng ETAII [8], FICTS [] and AFICTS [] are mplemented n the experment. In addton, -based approxmate desgns -trunc mplemented by gnorng lowest bts n addends are presented, whch s a smple but good baselne for comparson. Seven -DAR desgns are obtaned based on seven confguratons of wth detecton wndow of bts, whle three -DAR are

9 9 Error Rate (%) -DAR 9 -DAR 8 ETAII FICTS 7 AFICTS RAP- RAP- 6 RAP- 5 RAP- -trunc -trunc8 -trunc -trunc Power-Delay Product (ns*w) -5 Fg.. SARA-DAR: Error rate versus power-delay product. Error Rate (%) -DAR 9 -DAR 8 ETAII FICTS AFICTS 7 RAP- 6 RAP- RAP- 5 RAP- -trunc -trunc8 -trunc -trunc Energy-Delay Product (ns*nj) -5 Fg. 6. SARA-DAR: Error rate versus energy-delay product. PSNR (db) DAR -DAR ETAII FICTS AFICTS -trunc -trunc8 -trunc -trunc Power-Delay Product (ns*w) -5 Fg. 5. SARA-DAR: PSNR versus power-delay product. PSNR (db) DAR -DAR ETAII FICTS AFICTS -trunc -trunc8 -trunc -trunc6.5.5 Energy-Delay Product (ns*nj) -5 Fg. 7. SARA-DAR: PSNR versus energy-delay product. based on dfferent confguratons of. That s, f a MUX at bt s confgured to accurate carry n /, bt of correspondng SARA-DAR s hard-wred to accurate carry wthout usng MUX. When bt j n / s n approxmaton mode, bt j of correspondng SARA-DAR uses the delay-adaptve reconfguraton. Fgure shows the error rate versus PDP tradeoff. The dot of -DAR labeled wth represents the counterpart of when all the MUXes are controlled by delayadaptve reconfguraton. When we remove the MUX at the hghest bt to propagate accurate carry and keep others n delay-adaptve reconfguraton, another -DAR desgn could be obtaned (another dot labeled wth n the fgure). If we go on to remove more MUXes n MSB, a seres of -DAR desgns shown as dots wth label to 7 can be obtaned. Three -DAR desgns are created n the same way. Accordng to the fgure, the error rate of SARA s mostly lower than RAP-. By usng delayadaptve reconfguraton, SARA-DAR often has less error rate and PDP than SARA. SARA-DAR also greatly outperforms the statc approxmate adders n both error rate and PDP. Moreover, n Fgure we can observe those dots rght on the x-axs whch represent and workng n accurate mode. Both of them acheve zero error rate. PDP of accurate s about 5 ns W, whle PDP of accurate s almost. 5 ns W. In Fgure 5, SARA-DAR also demonstrates better PSNR-PDP tradeoff than other desgns, except for comparng wth -trunc at some low-psnr levels. However, -trunc has almost % error rate snce t dsmss lower bts n addends, whch s the worst among all statc approxmate adders. Fgure 6 and 7 show tradeoff between accuracy and EDP. At a certan EDP level, SARA-DAR has almost the same PSNR as -trunc, whch s the best among all statc approxmate adders. D. Impact of Detecton Wndow n Delay-Adaptve Reconfguraton Ths part shows the mpact of detecton wndow n the tradeoff for delay-adaptve reconfguraton. Accordng to Equaton (), the error rate of MUX output can be reduced by delay-adaptve reconfguraton. As the length of detecton wndow ncreases, the error rate would decrease because there are less probablty that MUX s confgured n approxmate mode. As a result, the overall error rate vares wth the sze of detecton wndow. Fgure 8 and 9 show the changes of error rate and PSNR of -DAR wth dfferent detecton wndow. As the sze of detecton wndow ncreases from to, the error rate decreases compared to ts SARA counterpart. However, we can observe that the gap of error rate between -DAR and -DAR vares wth

10 Error Rate (%) DAR -DAR -DAR Power-Delay Product (ns*w) -5 Power (W) SARA -DAR PSNR: RAP Fg. 8. Error rate of -DAR wth dfferent detecton wndow. Fg.. Iso-delay power comparson. The numbers are PSNR. PSNR (db) DAR 6 -DAR -DAR Power-Delay Product (ns*w) -5 Fg. 9. PSNR of -DAR wth dfferent detecton wndow. Normalzed Area RAP- -DAR dfferent confguraton. Although the change n error rate for ndvdual MUX of SARA-DAR s proportonal to the sze of detecton wndow (as shown n Equaton ()), the overall error rate n output results mght not show lnear change. When the sze of detecton wndow ncreases by, PSNR of -DAR ncreases by about db on average. We can also fnd that the PDP gap between -DAR and - DAR vares wth dfferent confguratons n both fgures. The change of PDP between -DAR and - DAR n most confguratons s very small, whle t s larger n the frst confguraton (whch s presented as the frst dot of -DAR n the left of the fgures). It s manly attrbuted to unproportoned change n delay between dfferent confguratons. E. Results of Iso-delay Power and Area Although power-delay product results have been shown n Sectons VI-B and VI-C, the tradeoff between power and delay s stll unclear. The power-delay tradeoff can be obtaned by dfferent accuracy confguratons or varyng supply voltages. Dfferent combnatons of confguratons and voltages may lead to overwhelmng volume of results, whch are dffcult to nterpret, especally when mplcaton to accuracy s nvolved at the same tme. Thus, we ndcate the tradeoff by nvestgatng the so-delay power, whch s the power of each Fg.. Area comparson. crcut tuned to the same crtcal path delay (.8ns) by voltage scalng. The results are shown n Fgure. In general,, and -DAR can acheve much lower power than. Although and RAP- seem to provde low power, ther PSNR s much less than our desgns. Compared at the same so-delay power level, SARA has more than db ncrease n PSNR than RAP-, whle has more than 7dB decrease than SARA desgns. SARA shows a large range of so-power tunng whch could reach the lowest and hghest power among all adders. We do not have so-delay power for approxmate adders workng n accurate mode, because the delay of such case s larger than due to nducton of MUXes whch cannot provde suffcent room for reducng supply voltage. Last but not the least, we compare area of these desgns n Fgure. Same as our expectaton, and RAP- have greater area than whle area of or s sgnfcantly smaller than. SARA has almost the same area as due to MUXes n every bt whch ad the accuracy confguraton. On average, the area of SARA s 9% smaller than that of RAP- and 5% smaller than that of.

11 Fg.. Basc structure of multpler. A. Extenson to Multpler VII. APPLICATIONS k stages fnal stage In complcated datapath system, multpler s consdered as a much bgger component n power consumpton. Our carrypredcton-based approxmaton uses generate bt to predct the carry from lower segments. The crtcal delay can be restraned to a smaller value wth shorter crtcal path n carry propagaton. Further extenson of our technque to multpler depends on the multplcaton structure used n hardware mplementaton. There s a varety of hardware desgns for multplcaton, accordng to the structures of reducton tree. In ths secton, we apply our technque on three knds of multplcaton structures ncludng array multpler, Wallace multpler and Dadda multpler. As shown n Fgure, the basc structure of multpler employs a three-step process to multply two ntegers. Step : Generate all partal products by usng an AND gate array. Step : Combne the partal products n k stages by layers of half/full adder untl the matrx heght s reduced to two. Dfferent types of structures depend on the reducton tree used to reduce the number of partal products n ths step. Step : Sum the resultng numbers n the fnal stage by a conventonal adder. In array multpler the carry bts n one stage are propagated dagonally downwards, whch follows the basc shft-and-add multplcaton algorthm. Wallace multpler based on Wallace tree combnes the partal products as early as possble, whch makes t faster than array multpler []. Dadda s strategy s to make the combnaton take place as late as possble, whch leads to smpler reducton tree and wder adder n fnal stage []. Thus, we can desgn approxmate multplers by usng our SARA desgn nstead of n the fnal stage. Three types of 6 6 multplers (array multpler, Wallace multpler and Dadda multpler) as well as behavoral multpler are syntheszed and mplemented by usng Nangate 5nm Open Cell Lbrary. Ther error data are obtaned from K-run Monte Carlo smulaton wth unform dstrbuton of operands. In approxmate multpler the fnal stage uses whch conssts of sub-adders wth bt-wdth of bts, whle the accurate one uses. Fgure and present the tradeoff between error and PDP. Most of approxmate multplers confgured n approxmate mode have better PDP compared wth the accurate multplers. The varance of error between dfferent approxmate mode n approxmate multpler has smlar trend as SARA. Total error ncreases as more bts are confgured n approxmate mode. Approxmate array multpler shows larger error than approxmate Wallace/Dadda multpler at the same PDP level. It s because array multpler has larger crtcal delay from nternal stages n step than Wallace/Dadda multpler. PSNR (db) Array Mult + SARA Wallace Mult + SARA Dadda Mult + SARA Array Mult Wallace Mult Dadda Mult Mult Power-Delay Product (ns*w) - Fg.. Multpler: PSNR versus power-delay product. Worst Case Error 8 6 ArrayMult + SARA Wallace Mult + SARA Dadda Mult + SARA Array Mult Wallace Mult Dadda Mult Mult Power-Delay Product (ns*w) - Fg.. Multpler: The worst case error versus power-delay product. Fgure 5 and 6 show the error versus EDP for both accurate and approxmate multplers. As more MUXes are set to propagate approxmate carry, the average error n output ncreases to about 7, whch as well acheves best EDP. The worst-case error rate of approxmate Dadda multpler s about %, whle t comes to about 7% for approxmate array multpler and Wallace multpler. As shown n Fgure 6, when approxmate multplers are workng n completely accurate mode (error rate equals ), EDP s larger than that of ther accurate counterpart. In summary, The expermental results show that our technque can be successfully extended to hgh speed multpler desgns. And due to the smple but effectve structure of SARA t provdes an easy way for us to convert conventonal multpler nto approxmate desgn. B. DCT Computaton n Image Processng The dscrete cosne transform (DCT) has been recognzed as the basc n many transform codng methods for mage and

12 Average Error 8 6 Array Mult + SARA Wallace Mult + SARA Dadda Mult + SARA Array Mult Wallace Mult Dadda Mult Mult - Energy-Delay Product (ns*nj) - Fg. 5. Multpler: Average error versus energy-delay product. Error Rate (%) Array Mult + SARA Wallace Mult + SARA Dadda Mult + SARA Array Mult Wallace Mult Dadda Mult Mult Energy-Delay Product (ns*nj) - Fg. 6. Multpler: Error rate versus energy-delay product. vdeo sgnal processng. It s used to transform the pxel data of mage or vdeo nto correspondng coeffcents n frequency doman. Snce human vsual system s more senstve to the changes n low frequency, the lost of accuracy n hghfrequency components does not heavly degrade the qualty of mage processed by DCT. In addton, those components n dfferent frequency have dfferent tolerances to the degradaton n orgnal data. It s a good example to show the reconfgurablty of our desgn by applyng them n VLSI mplementaton of DCT computng n JPEG mage compresson. The two-dmensonal DCT s mplemented by the rowcolumn decomposton technque, whch contans two stages of -D DCT [] []. The -D DCT of sze N N could be defned as Z = C t XC () where C s a normalzed Nth-order matrx and X s the data matrx. Generally the mage s dvded nto several N N blocks and each block s transformed by -D DCT nto frequency doman components. The VLSI mplementaton of DCT computng contans a set of ROM and Accumulator Components (RACs) whch can be mplemented by multplers and adders [] []. In ths applcaton we use approxmate adders to replace those accurate ones n RCAs to mplement an mprecse but low power crcut for mage processng whch contans DCT computng. TABLE IV IMAGE QUALITY COMPARISON IN PSNR lenna cameraman kel house AVERAGE Accurate DAR RAP We replace the adders n crcuts wth dfferent confguratons of SARA, SARA-DAR, as well as RAP-. The results are obtaned by numercal smulaton n Matlab. As we know, after DCT process data n dfferent frequency doman have dfferent level of error tolerance. As shown n Fgure, matrx components n the upper-left corner correspond to lower frequency coeffcents whch are senstve to human vson, whle those components n lower-rght corner mght allow more errors. To utlze ths feature for better energy-accuracy tradeoff, we make followng confguraton for dfferent desgns. ) : wth,,, consecutve segments workng n accurate mode are used to compute components n S, S, S and S respectvely. ) : wth segments n accurate mode are used to compute components n S, S, whle another confguraton wth all segments n approxmate mode are for S, S. ) -DAR: DAR counterpart of wth detecton wndow of bts. ) :,,,,,,, (same notaton as [8]) are used to compute components n S, S, S and S respectvely. 5) RAP-: snce RAP- can work n one approxmate mode, we use RAP- wth wndow sze of, 6,, 8 to compute components n S, S, S and S. The mage processng results are shown n Table IV. PSNR n the table s defned va the mean squared error (MSE). Gven an m n mage I and ts restored mage K, MSE and PSNR are defned as MSE = mn m = j= n [I(, j) K(, j)] (5) P SNR = log(max I ) log(mse), (6) where MAX I s the maxmum pxel value of the mage. -DAR has the hghest PSNR for every mage among all confgurable adders, whch s close to the qualty of accurate adder. Comparng wth, they have smlar PSNR and smlar delay, but has less power consumpton accordng to the analyss n the prevous secton. -DAR acheves better mage qualty than, but mght result n more power due to addtonal logcs for self-confguraton. The mage qualty for dfferent adders n DCT computng can also be demonstrated n Fgure 7 to. Accordng to human vson, SARA and ts DAR counterpart show better mage qualty than and RAP- n JPEG compresson processng.

13 (a) (b) (d) (c) (e) (f) Fg. 7. Comparson of mage lenna: (a) accurate adder; (b) ; (c) ; (d) -DAR; (e) ; (f) RAP-. (a) (b) (d) (c) (e) (f) Fg. 8. Comparson of mage cameraman: (a) accurate adder; (b) ; (c) ; (d) -DAR; (e) ; (f) RAP-. (a) (b) (d) (c) (e) (f) Fg. 9. Comparson of mage kel: (a) accurate adder; (b) ; (c) ; (d) -DAR; (e) ; (f) RAP-. (a) (b) (d) (c) (e) (f) Fg.. Comparson of mage house: (a) accurate adder; (b) ; (c) ; (d) -DAR; (e) ; (f) RAP-. S S S S S S S X Y=CtX S Z=CtXC Fg.. dmensonal descrete cosne transform. VIII. C ONCLUSION In ths paper, we propse a smple accuracy reconfgurable adder (SARA) desgn. It has sgnfcantly lower power/energydelay product than the latest prevous work when comparng at the same accuracy level. In addton, SARA has consderable lower area overhead than almost all the prevous works. The accuracy-power-delay effcency s further mproved by a delay-adaptve reconfguraton technque. We demonstrate the effcency of our adder n the applcatons of multplcaton crcuts and DCT computng crcuts for mage processng. ACKNOWLEDGMENT The authors would lke to thank Dr. Duncan M. Walker from Texas A&M Unversty for helpful dscussons. R EFERENCES [] J. Han and M. Orshansky, Approxmate computng: An emergng paradgm for energy-effcent desgn, n IEEE European Test Symposum, pp. 6,.

14 [] V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, Low-power dgtal sgnal processng usng approxmate adders, IEEE Transactons on Computer-Aded Desgn of Integrated Crcuts and Systems, vol., no., pp. 7,. [] V. Chppa, A. Raghunathan, K. Roy, and S. Chakradhar, Dynamc effort scalng: Managng the qualty-effcency tradeoff, n Desgn Automaton Conference (DAC), pp. 6 68,. [] S.-L. Lu, Speedng up processng wth approxmaton crcuts, Computer, vol. 7, no., pp. 67 7,. [5] S. Venkataraman, K. Roy, and A. Raghunathan, Substtute-andsmplfy: A unfed desgn paradgm for approxmate and qualty confgurable crcuts, n Conference on Desgn, Automaton and Test n Europe (DATE), pp. 67 7,. [6] K. Du, P. Varman, and K. Mohanram, Hgh performance relable varable latency carry select addton, n Conference on Desgn, Automaton and Test n Europe (DATE), pp. 57 6,. [7] A. K. Verma, P. Brsk, and P. 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Cao, New cost-effectve VLSI mplementaton of a -d dscrete cosne transform and ts nverse, IEEE Transactons on Crcuts and Systems for Vdeo Technology, vol., no., pp Wenbn Xu receved the B.S. and M.S. degree n electronc engneerng from Shangha Jao Tong Unversty, Shangha, Chna, n 8 and respectvely. He s now workng toward the Ph.D. degree n computer engneerng at Texas A&M Unversty, College Staton, TX. He s currently a Research Assstant n the Department of Electrcal and Computer Engneerng, Texas A&M Unversty. Hs research nterests nclude computer-aded desgn, approxmate computng and hardware securty. Sachn Sapatnekar (S 86, M 9, F ) receved the B. Tech. degree from the Indan Insttute of Technology, Bombay, the M.S. degree from Syracuse Unversty, and the Ph.D. degree from the Unversty of Illnos. He taught at Iowa State Unversty from 99 to 997 and has been at the Unversty of Mnnesota snce 997, where he holds the Dstngushed McKnght Unversty Professorshp and the Robert and Marjore Henle Char. He has receved seven conference Paper awards, a Poster Award, two ICCAD -year Retrospectve Most Influental Paper Awards, the SRC Techncal Excellence award and the SIA Unversty Researcher Award. He s a Fellow of the ACM and the IEEE. Jang Hu (F 6) receved the B.S. degree n optcal engneerng from Zhejang Unversty (Chna) n 99, the M.S. degree n physcs n 997 and the Ph.D. degree n electrcal engneerng from the Unversty of Mnnesota n. He worked wth IBM Mcroelectroncs from January to June. In, he joned the electrcal engneerng faculty at Texas A&M Unversty. Hs research nterest s n optmzaton for large scale computng systems, especally VLSI crcut optmzaton, adaptve desgn, hardware securty, resource allocaton and power management n computng systems. Dr. Hu receved the Paper Award at the ACM/IEEE Desgn Automaton Conference n, an IBM Inventon Achevement Award n, and the Paper Award from the IEEE/ACM Internatonal Conference on Computer-Aded Desgn n. He has served as a techncal program commttee member for DAC, ICCAD, ISPD, ISQED, ICCD, DATE, ISCAS, ASP-DAC and ISLPED. He s general char for the ACM Internatonal Symposum on Physcal Desgn, and an assocate edtor of IEEE transactons on CAD 6-. Currently he s an assocate edtor for the ACM transactons on Desgn Automaton of Electronc Systems. He receved a Humboldt research fellowshp n.