COMPARISON OF VARIOUS RIPPLE CARRY ADDERS: A REVIEW
|
|
- Marcia Dalton
- 5 years ago
- Views:
Transcription
1 RPN Journal of Engneerng and ppled Scences san Research Publshng Network (RPN). ll rghts reserved. COMPRISON OF VRIOUS RIPPLE CRRY DDERS: REVIEW Jmn Cheon School of Electronc Engneerng, Kumoh Natonal Insttute of Technology, 61 Daehak-ro, Gum, Korea E-Mal: BSTRCT s portable multmeda and communcatons applcatons emerge, the need for low power, small area, and low delay tme dgtal crcuts becomes more promnent. ddton process s the most used operaton n any DSP because addton s nvolved n all other mathematcal operatons. Therefore, adders desgn s consdered crtcal because t nfluences the performance of the system n terms of power and delay. In ths paper, we ntroduce varous rpple carry adder n terms of statc CMOS logc, dynamc CMOS logc, and others. Keywords: rpple carry adder, statc CMOS logc, dynamc CMOS logc, normal process complementary pass transstor logc (NPCPL). INTRODUCTION Low power, small area, and fast logc desgn became sgnfcant due to the spread of wreless communcaton and portable computng systems. dders construct a major block n any DSP snce all the arthmetc operatons (subtracton, multplcaton and dvson) rely on addton. There are many knds of adder structure, but rpple carry adder (RC) s the most low power, and small area desgn among them. However, even f same RC, there are lots of desgn logcs whch have dfferent performances. In ths paper, we analyze varous RC n terms of statc CMOS logc, dynamc CMOS logc, and others. Ths paper organzed as follows. Secton II ntroduces operaton and characterstc of smple basc RC. Secton III descrbes varous knd of the RC n terms of statc CMOS logc, dynamc CMOS logc, and others and also compares and analyzes performance of each RC. Secton IV concludes the paper. BSIC NLYSIS OF RC Basc unt of RC The basc unt of a RC s a full adder (F). n F adds two bnary numbers wth a carry-n. The Structure representaton of the conventonal CMOS F appears n Fgure-1. There are a total of three nputs for the F, two for the nput numbers and B, and one for the carry-n, C n. The outputs are the Sum and carry-out C out [1]. The logc functons correspondng to termnals Sum and C out are as follows: Basc theory and operaton The basc unt of a RC s an F. It can be extended ndefntely to any number by connectng the carry -out of the prevous 1-bt F to the carry-n of the next 1- bt F. n n-bt RC consstng of n sngle-bt Fs s descrbed n Fgure-2. The fgure clearly shows that the carry bt rpples through the chan of the cascaded Fs, from a lower bt to the next hgher order F [2, 3]. B C n Fgure-1. Structure of an F. 0 B0 n-1 Bn-1 Full dder Full dder... Full dder Sum C out Cn = C1 C2 Cn S 0 S 1 S n-1 Fgure-2. Structure of an RC. Table-1. Comparson between dfferent adders [3]. Sum B (1) C n C out ( B) C B (2) n 10530
2 RPN Journal of Engneerng and ppled Scences san Research Publshng Network (RPN). ll rghts reserved. Comparson between dfferent type adders In order to compare the performance of the dfferent adders, a 16 bt adder was used as a test vehcle for each type n [3]. The desgns are mplemented usng standard CMOS cells n 0.5-μm technology. ll the desgns are optmzed for power-delay product. Table 1 shows the comparson results between the RC, carry look ahead adder (CL adder), condtonal sum adder, and carry skp adder n terms of power, delay and area. The comparson result shows that RC has the smallest power and area [3]. dvantage and dsadvantage RC occupes the smallest area and dsspates the lowest power. lso t offers good performance for random nput data [4]. In ths case, average energy consumed by the B Sum C out Fgure-3. Transmsson functon full adder (TF). C n RC s E avg = O(W) where W s the word-length of the operands. For word-length W 16, the error n the theoretcal estmates s around 15% [5]. Nonetheless, ts delay characterstcs depend heavly on the length of the carry propagaton path, thus makng t a relatvely unfavorable choce for crcuts wth nonrandom nput operands. The worst case delay ncreases lnearly wth the length of the carry propagaton path, whch depends on the number of bts processed by the operands, n. lso, the area of the adder s proportonal to n [3]. Therefore, n stuatons when hgh speed performance s crucal and the mnmum amount of hardware s underperformng, usng an RC n the arthmetc operaton would be detrmental. VRIOUS KIND OF RCs Changng an F structure s necessary to mprove performance of an RC. There are lots of F structures, but t can classfy statc CMOS logc, dynamc CMOS logc, and others. Statc CMOS Logc The smple structure of conventonal F cell s based on statc CMOS logc. One F cells desgn usng a total of 32 transstors [6]. Therefore, the conventonal structure has not only large power but also long delay tme. F can be desgned to use multplexers and XORs. Whle ths s mpractcal n a complementary CMOS mplementaton, t becomes attractve when the multplexers and XORs are mplemented as transmsson gates [7]. B C n ~C out Sum Fgure transstor full adder (10-T F). Table-2. Comparson between the two F cells. Fgure-5. Delay tme versus power supply voltage
3 RPN Journal of Engneerng and ppled Scences san Research Publshng Network (RPN). ll rghts reserved. Fgure-7. 1 bt dynamc F. Fgure-6. Power dsspaton versus power supply voltage. One of the Fs based on ths approach s shown n Fgure- 3, the transmsson functon F (TF). The TF conssts of 16 transstors and dsspates less power than conventonal CMOS Fs [8]. Ths structure has meanng of CMOS F desgned by transmsson functon theory. better performance of F structure s Fgure-4, the 10-transstor low power hgh speed F (10-T F) cell [9]. The crtcal path conssts of an XOR gate; an nverter and one pass transstor. In a n-bt adder crcut, the new adder cell wll gve alternate polarty for the carryout n the odd and even postons. The nverters n the structure of the 10-T F cell act as drvers. Therefore, each stage wll not suffer from degradaton n ts dervng capabltes. The saves power, area and tme. Table-2 shows 10-T F has much better performance than TF. Two prototypes of 32-bts rpple carry adder are constructed. One prototype uses a TF, whereas the other prototype, whch uses a 10-T F, s constructed wth a two-transstor nverter drver. Fgure 5 shows the delay tme and Fgure 6 shows power dsspaton of 32-bt RC of each prototype. t a power supply voltage of 2.8 V, the crtcal path delay tme for a 32-bt RC that uses the TF prototype s 7.2 ns, whle t s observed to be 4.1 ns for the 10-T F prototype, thereby exhbtng a speed mprovement of 44 percent over the former. Cleary, the 10-T F prototype outperforms the TF prototype throughout the entre operatng range. For the power consumpton consderaton, t s observed that the 10-T F prototype dsspates 2.1 mw, whch s 81 percent less than the 11 mw dsspated by the TF prototype. Both of the 32-bt RCs were smulated at a supply voltage of 2.8 V and a clock Fgure bt DRC usng DCVS logc. Fgure-9. DCVS DRC components (a) carry generate and propagate (GP) block (b) carry bypass (CB) block and (c) EXOR block. frequency of 125 MHz. It s clear that the 10-transstor prototype dsplays enhanced power dsspaton over the TF for the operatng range of 2.8 V to 5 V. It can operate satsfactorly at frequency up to 350 MHz at a supply voltage of 5 V. Ths means that large archtectures can be bult to operate at very hgh frequences wthout compromsng the small-area and low-power characterstcs, whch are the man crtera for today s evolvng technology
4 RPN Journal of Engneerng and ppled Scences san Research Publshng Network (RPN). ll rghts reserved. Dynamc CMOS logc Dynamc logc s an alternatve logc style whch obtans a smlar result to statc logc, whle avodng statc power consumpton. Wth the addton of a clock nput, t uses a sequence of precharge and condtonal evaluaton phases [7]. Dynamc CMOS logc contans lower number of transstors and faster speed than statc CMOS logc. lso t only consumes dynamc power, but overall power dsspaton can be sgnfcantly hgher compared wth a statc logc gate. Therefore, usng dynamc logc can have mert of area, and delay tme than statc logc on specal condton. Fgure 7 shows 1-bt dynamc full adder. Fgure-8 shows the 16-bt dynamc RC (DRC) usng dfferental cascode swtch voltage (DCVS). DCVS logc s a dfferental logc style derved from domno logc made up of two complementary NMOS logc trees. Ths logc requres true and complementary nput sgnals to swtch the two outputs to dfferent logc states. In selftmed crcuts, ts dual-ral property can be used to generate completon sgnals for combnatonal logc n a general way [4]. The mathematcal formulaton of DCVS logc of DRC s gven below [10]. Let and B be the th bts of the nput data and C -1 the carry-n for stage. Then we have C G PC (3) 1 problems by ncludng 4 transstors. It has not only low delay tme but also small number of transstors than DCVS DRC. Fgure-11 s savng the area by replacng as many as PMOS transstor n NP CMOS DRC wth the NMOS transstors. The resultant structure s called ll-n DRC. Note than an nverter s requred between the carry logc and sum logc. Fgure-12 ntends to elmnate the need of negatve nputs. To acheve ths, however t s necessary to have a all-pmos composton of the sum logc. s wll be seen n smulaton results part, the all-pmos structure has made the desgn slowest among these several DRCs [10]. In order to mantan the advantage of postve nputs of the all-pmos logc (Fgure-12), t needs to replace the statc nverter of all-pmos logc wth a dynamc one (Fgure-13). The fast response tme of the dynamc nverter compensates the speed lost n the all- PMOS sum logc and makes the desgn the fastest among all the proposed DRCs. ~ S C B C P 1 1 (4) ~ P B (5) G B (6) ~ where P s the carry propagate sgnal and G s the carry generate sgnal. In adaptng (3) and (6) to dfferental logc, t s necessary to defne ther complements, whch are expressed as C B PC (7) 1 ~ S C 1 P (8) ~ Fgure-9 shows the each slce of 1-bt s made up of a carry generate and propagate block (GP) whch computes the sgnals P and P n parallel, a carry bypass block (CB), and an EXOR output stage. Ths structure has low delay tme but greatest power and area penalty. Fgure-10 shows DRC usng race-free NP CMOS logc [10]. Conventonal NP CMOS DRC has nherent race problems, but ths logc elmnates race ~ Fgure-10. Race-Free NP CMOS DRC
5 RPN Journal of Engneerng and ppled Scences san Research Publshng Network (RPN). ll rghts reserved. ~ C n ~C n ~ S0 C n ~ ~ C 0 B 0 ~ C n B0 0 B0 B0 0 B0 B0 ~ ~B 0 ~Cn ~B 1 Cn ~ S0 ~ ~ 1 ~C1 C1 ~ ~ ~C 0 S 1 ~C1 ~ 1 B 1 B 1 C1 C 0 ~ 1 ~ S1 ~ ~ ~ ~ Next stage Fgure-11. ll-n (N) dynamc CMOS logc of DRC. Table-3 shows the transstor count, the total transstor wdth, the worst-case delay of 16-bt DRCs usng dfferent cells, as well as those of the statc RC (SRC). The power dsspaton s measured for each crcut wth the worst-case delay. The DCVS DRC, though much faster than the SRC, as the worst delay among all DRCs. Further, t has the greatest power and area penalty. The Fgure-13. Usng dynamc nverter n Fgure 12 s logc. Table-3. Features of varous 16-bt RC [10]. ~ C n 0 B0 B0 B 0 ~ C n ~ B0 Cn ~ S0 dynamc nverter (DI) DRC s the fastest among all RCs. It s 2.3 tmes faster than the SRC and 1.46 tmes faster than the DCVS DRC. The N DRC has the lowest power and area penalty among all DRCs. It s even smaller than the SRC. lthough t consumes more power than the SRC, ts power-delay product (PDP) s superor to that of the SRC [10]. ~C1 1 C 1 B 1 ~ S1 In1 In2 In3 In4 g1 g2 g3 g4 two stage Fgure-12. Prmary nput of DRC becomes postve logc. out ~out Fgure-14. New basc NPCPL cell
6 RPN Journal of Engneerng and ppled Scences san Research Publshng Network (RPN). ll rghts reserved. CKNOWLEDGEMENT Ths paper was supported by Research Fund, Kumoh Natonal Insttute of Technology. REFERENCES [1] K. S. Yeo and K. Roy Low-Voltage Low- Power VLSI Subsystems, Mc Graw Hll. Fgure bt F and 2 bts F usng NPCPL cell. Table-4. New nput combnaton. Others Wave ppelnng s a very effcent way to desgn hgh-throughput RC, but t requres accurate delay control. Hence, CMOS normal process complementary pass transstor logc (NPCPL) has been used n place of statc CMOS logc whch suffers delay varaton dependng on nput combnatons. The most mportant advantage of usng NPCPL s that all knds of gates can be mplemented wth the same basc structure, hence the delays of all knds of gates can be kept the same. However, conventonal NPCPL has two major problems for hgh speed wave ppelned desgn. One s the nsuffcent drvng capablty, and the other s the unbalanced loadng. In [11], new basc NPCPL cell solve the two problems of conventonal NPCPL cell. The load unbalancng problem has been solved by a new nput combnaton and the problem of nsuffcent drvng capablty has been overcome by a two-stage buffer. Table 4 shows new nput combnaton and Fgure 14 shows new basc NPCPL cell whch contans two stage buffers. In [11], expermental results obtaned from 16-bt RC usng new NPCPL cell n 0.8-μm technology shows 900 MHz throughput. CONCLUSIONS In ths paper, we analyze and compare varous RCs n terms of statc CMOS logc, dynamc CMOS logc, and others. s we analyzed above, statc CMOS logc can operate n low power dsspaton, whereas dynamc CMOS logc can operate much less delay tme. By usng NPCPL cell, 16-bt RC provdes throughput of 900MHz whch s the fastest among ntroduced RCs. [2] I. Koren Computer rthmetc lgorthms, Englewood Clffs, New Jersey: Prentce Hall. [3] M. W. llam and M.I. Elmasry Low-power mplementaton of fast addton algorthms. IEEE Canadan Conf. Electrcal and Computer Engneerng. pp [4] G.. Ruz Evaluaton of three 32-bt CMOS adders n DCVS logc for self-tmed crcuts. IEEE J. Sold-State Crcuts. 13(4): [5] L. Montalvo and K.K. Parh Estmaton of verage Energy Consumpton of Rpple-Carry dder Based on verage Length Carry Chans. In: proc. 11 th Desgn of Integrated Crcuts and Systems Conference (DCIS 96), Barcelona, Span. [6] N.H.E Weste and K. Eshraghan Prncples of CMOS VLSI desgn: Systems Perspectve, Readng, Massachusetts: ddson-wesley. [7] J. Rabaey Dgtal Integrated Crcuts: Desgn Perspectve, Englewood Clffs, NJ: Prentce Hall. [8] N. Zhaung and H. Wu New Desgn of the CMOS Full dder. IEEE J. Sold-State Crcuts. 27(5): [9] H.. Mahmoud and M.. Bayoum transstor low-power hgh-speed full adder cel. In: IEEE Int. Symp. Crcut and Systems, pp [10] C.J. Fang, C.H. Huang, J.S. Wang, C.W. Yeh Fast and compact dynamc rpple carry adder desgn. In: Proc. IEEE sa-pacfc Conference. pp [11] H. Cho, S.H. Hwang Desgn of waveppelned 900MHz 16b rpple-carry adder usng modfed NPCPL. In: IEEE Int. Symp. Crcut and Systems. pp
High Speed, Low Power And Area Efficient Carry-Select Adder
Internatonal Journal of Scence, Engneerng and Technology Research (IJSETR), Volume 5, Issue 3, March 2016 Hgh Speed, Low Power And Area Effcent Carry-Select Adder Nelant Harsh M.tech.VLSI Desgn Electroncs
More informationA High-Speed Multiplication Algorithm Using Modified Partial Product Reduction Tree
World Academy of Scence, Engneerng and Technology Internatonal Journal of Electrcal and Computer Engneerng Vol:4, No:, 200 A Hgh-Speed Multplcaton Algorthm Usng Modfed Partal Product educton Tree P Asadee
More informationHIGH PERFORMANCE ADDER USING VARIABLE THRESHOLD MOSFET IN 45NM TECHNOLOGY
Internatonal Journal of Electrcal, Electroncs and Computer Systems, (IJEECS) HIGH PERFORMANCE ADDER USING VARIABLE THRESHOLD MOSFET IN 45NM TECHNOLOGY 1 Supryo Srman, 2 Dptendu Ku. Kundu, 3 Saradndu Panda,
More informationPERFORMANCE EVALUATION OF BOOTH AND WALLACE MULTIPLIER USING FIR FILTER. Chirala Engineering College, Chirala.
PERFORMANCE EVALUATION OF BOOTH AND WALLACE MULTIPLIER USING FIR FILTER 1 H. RAGHUNATHA RAO, T. ASHOK KUMAR & 3 N.SURESH BABU 1,&3 Department of Electroncs and Communcaton Engneerng, Chrala Engneerng College,
More informationDigital Transmission
Dgtal Transmsson Most modern communcaton systems are dgtal, meanng that the transmtted normaton sgnal carres bts and symbols rather than an analog sgnal. The eect o C/N rato ncrease or decrease on dgtal
More informationFigure.1. Basic model of an impedance source converter JCHPS Special Issue 12: August Page 13
A Hgh Gan DC - DC Converter wth Soft Swtchng and Power actor Correcton for Renewable Energy Applcaton T. Selvakumaran* and. Svachdambaranathan Department of EEE, Sathyabama Unversty, Chenna, Inda. *Correspondng
More informationantenna antenna (4.139)
.6.6 The Lmts of Usable Input Levels for LNAs The sgnal voltage level delvered to the nput of an LNA from the antenna may vary n a very wde nterval, from very weak sgnals comparable to the nose level,
More informationHigh Speed ADC Sampling Transients
Hgh Speed ADC Samplng Transents Doug Stuetzle Hgh speed analog to dgtal converters (ADCs) are, at the analog sgnal nterface, track and hold devces. As such, they nclude samplng capactors and samplng swtches.
More informationA study of turbo codes for multilevel modulations in Gaussian and mobile channels
A study of turbo codes for multlevel modulatons n Gaussan and moble channels Lamne Sylla and Paul Forter (sylla, forter)@gel.ulaval.ca Department of Electrcal and Computer Engneerng Laval Unversty, Ste-Foy,
More informationEfficient Large Integers Arithmetic by Adopting Squaring and Complement Recoding Techniques
The th Worshop on Combnatoral Mathematcs and Computaton Theory Effcent Large Integers Arthmetc by Adoptng Squarng and Complement Recodng Technques Cha-Long Wu*, Der-Chyuan Lou, and Te-Jen Chang *Department
More informationIEE Electronics Letters, vol 34, no 17, August 1998, pp ESTIMATING STARTING POINT OF CONDUCTION OF CMOS GATES
IEE Electroncs Letters, vol 34, no 17, August 1998, pp. 1622-1624. ESTIMATING STARTING POINT OF CONDUCTION OF CMOS GATES A. Chatzgeorgou, S. Nkolads 1 and I. Tsoukalas Computer Scence Department, 1 Department
More informationTECHNICAL NOTE TERMINATION FOR POINT- TO-POINT SYSTEMS TN TERMINATON FOR POINT-TO-POINT SYSTEMS. Zo = L C. ω - angular frequency = 2πf
TECHNICAL NOTE TERMINATION FOR POINT- TO-POINT SYSTEMS INTRODUCTION Because dgtal sgnal rates n computng systems are ncreasng at an astonshng rate, sgnal ntegrty ssues have become far more mportant to
More informationPRACTICAL, COMPUTATION EFFICIENT HIGH-ORDER NEURAL NETWORK FOR ROTATION AND SHIFT INVARIANT PATTERN RECOGNITION. Evgeny Artyomov and Orly Yadid-Pecht
68 Internatonal Journal "Informaton Theores & Applcatons" Vol.11 PRACTICAL, COMPUTATION EFFICIENT HIGH-ORDER NEURAL NETWORK FOR ROTATION AND SHIFT INVARIANT PATTERN RECOGNITION Evgeny Artyomov and Orly
More informationDesign of Practical FIR Filter Using Modified Radix-4 Booth Algorithm
Desgn of Practcal FIR Flter Usng Modfed Radx-4 Booth Algorthm E Srnvasarao M.Tech Scholar, Department of ECE, AITAM. V. Lokesh Raju Assocate Professor, Department of ECE, AITAM. L Rambabu Assstant Professor,
More informationDynamic Optimization. Assignment 1. Sasanka Nagavalli January 29, 2013 Robotics Institute Carnegie Mellon University
Dynamc Optmzaton Assgnment 1 Sasanka Nagavall snagaval@andrew.cmu.edu 16-745 January 29, 213 Robotcs Insttute Carnege Mellon Unversty Table of Contents 1. Problem and Approach... 1 2. Optmzaton wthout
More informationLogical Effort of Carry Propagate Adders
Logcal Effort of Carry Propagate Adders Davd arrs and Ivan Sutherland arvey Mudd College / Sun Mcrosystems Laboratores E. Twelfth St. Claremont, CA Davd_arrs@hmc.edu / Ivan.Sutherland@sun.com Abstract
More informationUncertainty in measurements of power and energy on power networks
Uncertanty n measurements of power and energy on power networks E. Manov, N. Kolev Department of Measurement and Instrumentaton, Techncal Unversty Sofa, bul. Klment Ohrdsk No8, bl., 000 Sofa, Bulgara Tel./fax:
More informationA High-Sensitivity Oversampling Digital Signal Detection Technique for CMOS Image Sensors Using Non-destructive Intermediate High-Speed Readout Mode
A Hgh-Senstvty Oversamplng Dgtal Sgnal Detecton Technque for CMOS Image Sensors Usng Non-destructve Intermedate Hgh-Speed Readout Mode Shoj Kawahto*, Nobuhro Kawa** and Yoshak Tadokoro** *Research Insttute
More informationParameter Free Iterative Decoding Metrics for Non-Coherent Orthogonal Modulation
1 Parameter Free Iteratve Decodng Metrcs for Non-Coherent Orthogonal Modulaton Albert Gullén Fàbregas and Alex Grant Abstract We study decoder metrcs suted for teratve decodng of non-coherently detected
More informationRejection of PSK Interference in DS-SS/PSK System Using Adaptive Transversal Filter with Conditional Response Recalculation
SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol., No., November 23, 3-9 Rejecton of PSK Interference n DS-SS/PSK System Usng Adaptve Transversal Flter wth Condtonal Response Recalculaton Zorca Nkolć, Bojan
More information@IJMTER-2015, All rights Reserved 383
SIL of a Safety Fuzzy Logc Controller 1oo usng Fault Tree Analyss (FAT and realablty Block agram (RB r.-ing Mohammed Bsss 1, Fatma Ezzahra Nadr, Prof. Amam Benassa 3 1,,3 Faculty of Scence and Technology,
More informationECE 2133 Electronic Circuits. Dept. of Electrical and Computer Engineering International Islamic University Malaysia
ECE 2133 Electronc Crcuts Dept. of Electrcal and Computer Engneerng Internatonal Islamc Unversty Malaysa Chapter 12 Feedback and Stablty Introducton to Feedback Introducton to Feedback 1-4 Harold Black,
More informationMismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO., JUNE, 7 ISSN(Prnt) 59-57 https://do.org/.557/jsts.7.7..7 ISSN(Onlne) - Msmatch-tolerant Capactor Array Structure for Juncton-splttng SAR Analog-to-dgtal
More informationA Comparison of Two Equivalent Real Formulations for Complex-Valued Linear Systems Part 2: Results
AMERICAN JOURNAL OF UNDERGRADUATE RESEARCH VOL. 1 NO. () A Comparson of Two Equvalent Real Formulatons for Complex-Valued Lnear Systems Part : Results Abnta Munankarmy and Mchael A. Heroux Department of
More informationMASTER TIMING AND TOF MODULE-
MASTER TMNG AND TOF MODULE- G. Mazaher Stanford Lnear Accelerator Center, Stanford Unversty, Stanford, CA 9409 USA SLAC-PUB-66 November 99 (/E) Abstract n conjuncton wth the development of a Beam Sze Montor
More informationComparative Analysis of Reuse 1 and 3 in Cellular Network Based On SIR Distribution and Rate
Comparatve Analyss of Reuse and 3 n ular Network Based On IR Dstrbuton and Rate Chandra Thapa M.Tech. II, DEC V College of Engneerng & Technology R.V.. Nagar, Chttoor-5727, A.P. Inda Emal: chandra2thapa@gmal.com
More informationLow Switching Frequency Active Harmonic Elimination in Multilevel Converters with Unequal DC Voltages
Low Swtchng Frequency Actve Harmonc Elmnaton n Multlevel Converters wth Unequal DC Voltages Zhong Du,, Leon M. Tolbert, John N. Chasson, Hu L The Unversty of Tennessee Electrcal and Computer Engneerng
More informationControl of Chaos in Positive Output Luo Converter by means of Time Delay Feedback
Control of Chaos n Postve Output Luo Converter by means of Tme Delay Feedback Nagulapat nkran.ped@gmal.com Abstract Faster development n Dc to Dc converter technques are undergong very drastc changes due
More informationImplementation Complexity of Bit Permutation Instructions
Implementaton Complexty of Bt Permutaton Instructons Zhje Jerry Sh and Ruby B. Lee Department of Electrcal Engneerng, Prnceton Unversty, Prnceton, NJ 085 USA {zsh, rblee}@ee.prnceton.edu Abstract- Several
More informationResearch of Dispatching Method in Elevator Group Control System Based on Fuzzy Neural Network. Yufeng Dai a, Yun Du b
2nd Internatonal Conference on Computer Engneerng, Informaton Scence & Applcaton Technology (ICCIA 207) Research of Dspatchng Method n Elevator Group Control System Based on Fuzzy Neural Network Yufeng
More informationCalculation of the received voltage due to the radiation from multiple co-frequency sources
Rec. ITU-R SM.1271-0 1 RECOMMENDATION ITU-R SM.1271-0 * EFFICIENT SPECTRUM UTILIZATION USING PROBABILISTIC METHODS Rec. ITU-R SM.1271 (1997) The ITU Radocommuncaton Assembly, consderng a) that communcatons
More informationA Current Differential Line Protection Using a Synchronous Reference Frame Approach
A Current Dfferental Lne rotecton Usng a Synchronous Reference Frame Approach L. Sousa Martns *, Carlos Fortunato *, and V.Fernão res * * Escola Sup. Tecnologa Setúbal / Inst. oltécnco Setúbal, Setúbal,
More informationECE315 / ECE515 Lecture 5 Date:
Lecture 5 Date: 18.08.2016 Common Source Amplfer MOSFET Amplfer Dstorton Example 1 One Realstc CS Amplfer Crcut: C c1 : Couplng Capactor serves as perfect short crcut at all sgnal frequences whle blockng
More informationA Novel Soft-Switching Two-Switch Flyback Converter with a Wide Operating Range and Regenerative Clamping
77 Journal of ower Electroncs, ol 9, No 5, September 009 JE 9-5- A Novel Soft-Swtchng Two-Swtch Flybac Converter wth a Wde Operatng Range and Regeneratve Clampng Marn-Go Km and Young-Seo Jung * Dvson of
More informationMTBF PREDICTION REPORT
MTBF PREDICTION REPORT PRODUCT NAME: BLE112-A-V2 Issued date: 01-23-2015 Rev:1.0 Copyrght@2015 Bluegga Technologes. All rghts reserved. 1 MTBF PREDICTION REPORT... 1 PRODUCT NAME: BLE112-A-V2... 1 1.0
More informationA Simple Yet Efficient Accuracy Configurable Adder Design
A Smple Yet Effcent Accuracy Confgurable Adder Desgn Wenbn Xu, Sachn S. Sapatnekar and Jang Hu Department of Electrcal and Computer Engneerng, Texas A&M Unversty Department of Electrcal and Computer Engneerng,
More informationModeling and Control of a Cascaded Boost Converter for a Battery Electric Vehicle
Modelng and Control of a Cascaded Boost Converter for a Battery Electrc Vehcle A. Ndtoungou, Ab. Hamad, A. Mssandaand K. Al-Haddad, Fellow member, IEEE EPEC 202 OCTOBER 0-2 Introducton contents Comparson
More informationLatency Insertion Method (LIM) for IR Drop Analysis in Power Grid
Abstract Latency Inserton Method (LIM) for IR Drop Analyss n Power Grd Dmtr Klokotov, and José Schutt-Ané Wth the steadly growng number of transstors on a chp, and constantly tghtenng voltage budgets,
More informationMultiple Error Correction Using Reduced Precision Redundancy Technique
Multple Error Correcton Usng Reduced Precson Redundancy Technque Chthra V 1, Nthka Bhas 2, Janeera D A 3 1,2,3 ECE Department, Dhanalakshm Srnvasan College of Engneerng,Combatore, Tamlnadu, Inda Abstract
More informationA Mathematical Solution to Power Optimal Pipeline Design by Utilizing Soft Edge Flip-Flops
A Mathematcal Soluton to Power Optmal Ppelne Desgn by Utlzng Soft Edge Flp-Flops Mohammad Ghasemazar, Behnam Amelfard and Massoud Pedram Unversty of Southern Calforna Department of Electrcal Engneerng
More informationKeywords LTE, Uplink, Power Control, Fractional Power Control.
Volume 3, Issue 6, June 2013 ISSN: 2277 128X Internatonal Journal of Advanced Research n Computer Scence and Software Engneerng Research Paper Avalable onlne at: www.jarcsse.com Uplnk Power Control Schemes
More informationCMOS Implementation of Lossy Integrator using Current Mirrors Rishu Jain 1, Manveen Singh Chadha 2 1, 2
Proceedngs of Natonal Conference on Recent Advances n Electroncs and Communcaton Engneerng CMOS Implementaton of Lossy Integrator usng Current Mrrors Rshu Jan, Manveen Sngh Chadha 2, 2 Department of Electroncs
More informationTo: Professor Avitabile Date: February 4, 2003 From: Mechanical Student Subject: Experiment #1 Numerical Methods Using Excel
To: Professor Avtable Date: February 4, 3 From: Mechancal Student Subject:.3 Experment # Numercal Methods Usng Excel Introducton Mcrosoft Excel s a spreadsheet program that can be used for data analyss,
More informationSensors for Motion and Position Measurement
Sensors for Moton and Poston Measurement Introducton An ntegrated manufacturng envronment conssts of 5 elements:- - Machne tools - Inspecton devces - Materal handlng devces - Packagng machnes - Area where
More informationWalsh Function Based Synthesis Method of PWM Pattern for Full-Bridge Inverter
Walsh Functon Based Synthess Method of PWM Pattern for Full-Brdge Inverter Sej Kondo and Krt Choesa Nagaoka Unversty of Technology 63-, Kamtomoka-cho, Nagaoka 9-, JAPAN Fax: +8-58-7-95, Phone: +8-58-7-957
More informationRC Filters TEP Related Topics Principle Equipment
RC Flters TEP Related Topcs Hgh-pass, low-pass, Wen-Robnson brdge, parallel-t flters, dfferentatng network, ntegratng network, step response, square wave, transfer functon. Prncple Resstor-Capactor (RC)
More informationImprovement of the Shunt Active Power Filter Dynamic Performance
Improvement of the Shunt Actve Power Flter Dynamc Performance Krzysztof Potr Sozansk Unversty of Zelona Góra, Faculty of Electrcal Engneerng omputer Scence and Telecommuncatons Zelona Góra, Poland Abstract
More informationINSTANTANEOUS TORQUE CONTROL OF MICROSTEPPING BIPOLAR PWM DRIVE OF TWO-PHASE STEPPING MOTOR
The 5 th PSU-UNS Internatonal Conference on Engneerng and 537 Technology (ICET-211), Phuket, May 2-3, 211 Prnce of Songkla Unversty, Faculty of Engneerng Hat Ya, Songkhla, Thaland 9112 INSTANTANEOUS TORQUE
More informationDynamic Power Consumption in Virtex -II FPGA Family
Dynamc Power Consumpton n Vrtex -II FPGA Famly L Shang Prnceton Unversty EE Dept., Prnceton, NJ 08540 lshang@ee.prnceton.edu Alreza S Kavan Xlnx Inc. 2100 Logc Dr., San Jose, CA 95124 alreza.kavan@xlnx.com
More informationPerformance Analysis of Power Line Communication Using DS-CDMA Technique with Adaptive Laguerre Filters
Internatonal Conference on Informaton and Electroncs Engneerng IPCSIT vol.6 ( ( IACSIT Press, Sngapore Performance Analyss of Power Lne Communcaton Usng DS-CDMA Technque wth Adaptve Laguerre Flters S.
More informationNATIONAL RADIO ASTRONOMY OBSERVATORY Green Bank, West Virginia SPECTRAL PROCESSOR MEMO NO. 25. MEMORANDUM February 13, 1985
NATONAL RADO ASTRONOMY OBSERVATORY Green Bank, West Vrgna SPECTRAL PROCESSOR MEMO NO. 25 MEMORANDUM February 13, 1985 To: Spectral Processor Group From: R. Fsher Subj: Some Experments wth an nteger FFT
More informationTopology Control for C-RAN Architecture Based on Complex Network
Topology Control for C-RAN Archtecture Based on Complex Network Zhanun Lu, Yung He, Yunpeng L, Zhaoy L, Ka Dng Chongqng key laboratory of moble communcatons technology Chongqng unversty of post and telecommuncaton
More informationThe Performance Improvement of BASK System for Giga-Bit MODEM Using the Fuzzy System
Int. J. Communcatons, Network and System Scences, 10, 3, 1-5 do:10.36/jcns.10.358 Publshed Onlne May 10 (http://www.scrp.org/journal/jcns/) The Performance Improvement of BASK System for Gga-Bt MODEM Usng
More informationDelay Constrained Fuzzy Rate Control for Video Streaming over DVB-H
Delay Constraned Fuzzy Rate Control for Vdeo Streamng over DVB-H Mehd Rezae, Moncef Gabbouj, 3 med Bouazz,, Tampere Unversty of Technology, 3 Noka Research Center, Tampere, Fnland mehd.rezae@tut.f, moncef.gabbouj@tut.f,
More informationMicroelectronic Circuits
Mcroelectronc Crcuts Slde 1 Introducton Suggested textbook: 1. Adel S. Sedra and Kenneth C. Smth, Mcroelectronc Crcuts Theory and Applcatons, Sxth edton Internatonal Verson, Oxford Unersty Press, 2013.
More informationShunt Active Filters (SAF)
EN-TH05-/004 Martt Tuomanen (9) Shunt Actve Flters (SAF) Operaton prncple of a Shunt Actve Flter. Non-lnear loads lke Varable Speed Drves, Unnterrupted Power Supples and all knd of rectfers draw a non-snusodal
More informationTHE ARCHITECTURE OF THE BROADBAND AMPLIFIERS WITHOUT CLASSICAL STAGES WITH A COMMON BASE AND A COMMON EMITTER
VOL. 0, NO. 8, OCTOBE 205 ISSN 89-6608 2006-205 Asan esearch Publshng Network (APN. All rghts reserved. THE ACHITECTUE OF THE BOADBAND AMPLIFIES WITHOUT CLASSICAL STAGES WITH A COMMON BASE AND A COMMON
More informationPassive Filters. References: Barbow (pp ), Hayes & Horowitz (pp 32-60), Rizzoni (Chap. 6)
Passve Flters eferences: Barbow (pp 6575), Hayes & Horowtz (pp 360), zzon (Chap. 6) Frequencyselectve or flter crcuts pass to the output only those nput sgnals that are n a desred range of frequences (called
More informationA simulation-based optimization of low noise amplifier design using PSO algorithm
IJCSNS Internatonal Journal of Computer Scence and Network Securty, VOL.16 No.5, May 2016 45 A smulaton-based optmzaton of low nose amplfer desgn usng PSO algorthm Roohollah Nakhae, Peyman Almasnejad and
More informationStrain Gauge Measuring Amplifier BA 660
Stran Gauge Measurng Amplfer BA 660 Orgnal of the Manual BA660 / IP20 BA660 / IP66 Table of Contents 1. Safety precautons...2 1.1. Feld of applcaton...2 1.2. Installaton...2 1.3. Mantenance...2 2. Functon...2
More informationPOWER constraints are a well-known challenge in advanced
A Smple Yet Effcent Accuracy Confgurable Adder Desgn Wenbn Xu, Student Member, IEEE, Sachn S. Sapatnekar, Fellow, IEEE, and Jang Hu, Fellow, IEEE Abstract Approxmate computng s a promsng approach for low
More informationPULSEWIDTH-modulated (PWM) voltage-source inverters
674 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 4, JULY 1998 Carrer-Based PWM-VSI Overmodulaton Strateges: Analyss, Comparson, and Desgn Ahmet M. Hava, Student Member, IEEE, Russel J. Kerkman,
More informationFAST ELECTRON IRRADIATION EFFECTS ON MOS TRANSISTOR MICROSCOPIC PARAMETERS EXPERIMENTAL DATA AND THEORETICAL MODELS
Journal of Optoelectroncs and Advanced Materals Vol. 7, No., June 5, p. 69-64 FAST ELECTRON IRRAIATION EFFECTS ON MOS TRANSISTOR MICROSCOPIC PARAMETERS EXPERIMENTAL ATA AN THEORETICAL MOELS G. Stoenescu,
More informationFigure 1. DC-DC Boost Converter
EE46, Power Electroncs, DC-DC Boost Converter Verson Oct. 3, 11 Overvew Boost converters make t possble to effcently convert a DC voltage from a lower level to a hgher level. Theory of Operaton Relaton
More informationPower Factor Correction with AC-DC Buck Converter
Internatonal Journal of Electrcal Engneerng. IN 09742158 Volume 8, Number 1 (2015), pp. 2938 Internatonal Research Publcaton House http://www.rphouse.com Power Factor Correcton wth ACDC Buck Converter
More informationA New Type of Weighted DV-Hop Algorithm Based on Correction Factor in WSNs
Journal of Communcatons Vol. 9, No. 9, September 2014 A New Type of Weghted DV-Hop Algorthm Based on Correcton Factor n WSNs Yng Wang, Zhy Fang, and Ln Chen Department of Computer scence and technology,
More informationScilab/Scicos Modeling, Simulation and PC Based Implementation of Closed Loop Speed Control of VSI Fed Induction Motor Drive
16th NATIONAL POWER SYSTEMS CONFERENCE, 15th-17th DECEMBER, 2010 453 Sclab/Sccos Modelng, Smulaton and PC Based Implementaton of Closed Loop Speed Control of VSI Fed Inducton Motor Dre Vjay Babu Korebona,
More informationSimulation and Closed Loop Control of Multilevel DC-DC Converter for Variable Load and Source Conditions
ISSN(Onlne): 232981 ISSN (Prnt) : 2329798 (An ISO 3297: 27 Certfed Organzaton) Vol. 4, Issue 3, March 216 Smulaton and Closed Loop Control of Multlevel DCDC Converter for Varable Load and Source Condtons
More informationModel Reference Current Control of a Unipolar Induction Motor Drive
IEEE IAS Annual Meetng Page 1 of 7 Chcago, Illnos, September 3 October 4, 21 Model Reference Current Control of a Unpolar Inducton Motor Drve Bran A. Welchko Unversty of Wsconsn Madson 1415 Engneerng Drve
More informationResearch on Controller of Micro-hydro Power System Nan XIE 1,a, Dezhi QI 2,b,Weimin CHEN 2,c, Wei WANG 2,d
Advanced Materals Research Submtted: 2014-05-13 ISSN: 1662-8985, Vols. 986-987, pp 1121-1124 Accepted: 2014-05-19 do:10.4028/www.scentfc.net/amr.986-987.1121 Onlne: 2014-07-18 2014 Trans Tech Publcatons,
More informationHarmonic Balance of Nonlinear RF Circuits
MICROWAE AND RF DESIGN Harmonc Balance of Nonlnear RF Crcuts Presented by Mchael Steer Readng: Chapter 19, Secton 19. Index: HB Based on materal n Mcrowave and RF Desgn: A Systems Approach, nd Edton, by
More informationN- and P-Channel 2.5-V (G-S) MOSFET
S456DY N- and P-Channel.5-V (G-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) (Ω) (A).5 at 7. N-Channel.35 at V GS =.5 V 6. FEATURES Halogen-free Accordng to IEC 649-- Defnton TrenchFET Power MOSFET:.5 Rated
More informationAvailable Transfer Capability (ATC) Under Deregulated Power Systems
Volume-4, Issue-2, Aprl-2, IN : 2-758 Internatonal Journal of Engneerng and Management Research Avalable at: www.emr.net Page Number: 3-8 Avalable Transfer Capablty (ATC) Under Deregulated Power ystems
More informationMicro-grid Inverter Parallel Droop Control Method for Improving Dynamic Properties and the Effect of Power Sharing
2015 AASRI Internatonal Conference on Industral Electroncs and Applcatons (IEA 2015) Mcro-grd Inverter Parallel Droop Control Method for Improvng Dynamc Propertes and the Effect of Power Sharng aohong
More informationFigure 1. DC-DC Boost Converter
EE36L, Power Electroncs, DC-DC Boost Converter Verson Feb. 8, 9 Overvew Boost converters make t possble to effcently convert a DC voltage from a lower level to a hgher level. Theory of Operaton Relaton
More informationFast Algorithm of A 64-bit Decimal Logarithmic Converter
JOURNAL OF OMPUTERS, VOL. 5, NO. 12, DEEMBER 20 1847 Fast Algorthm of A 64-bt Decmal Logarthmc onverter Ramn Tajallpour, Md. Ashraful Islam, and Khan A. Wahd Dept. of Electrcal and omputer Engneerng, Unversty
More informationAFV-P 2U/4U. AC + DC Power Solutions. series. Transient Generation for Disturbance Tests. only. High Performance Programmable AC Power Source
AFV-P seres Hgh Performance Programmable AC Power Source only 2U/4U Intutve Touch Screen HMI Output Frequency up to 15-1000Hz Power Lne Smulatons: Step & Ramp Features Fast Response Tme: 300μs AC Source
More informationChaotic Filter Bank for Computer Cryptography
Chaotc Flter Bank for Computer Cryptography Bngo Wng-uen Lng Telephone: 44 () 784894 Fax: 44 () 784893 Emal: HTwng-kuen.lng@kcl.ac.ukTH Department of Electronc Engneerng, Dvson of Engneerng, ng s College
More informationThe Effect Of Phase-Shifting Transformer On Total Consumers Payments
Australan Journal of Basc and Appled Scences 5(: 854-85 0 ISSN -88 The Effect Of Phase-Shftng Transformer On Total Consumers Payments R. Jahan Mostafa Nck 3 H. Chahkand Nejad Islamc Azad Unversty Brjand
More informationCoverage Maximization in Mobile Wireless Sensor Networks Utilizing Immune Node Deployment Algorithm
CCECE 2014 1569888203 Coverage Maxmzaton n Moble Wreless Sensor Networs Utlzng Immune Node Deployment Algorthm Mohammed Abo-Zahhad, Sabah M. Ahmed and Nabl Sabor Electrcal and Electroncs Engneerng Department
More information熊本大学学術リポジトリ. Kumamoto University Repositor
熊本大学学術リポジトリ Kumamoto Unversty Repostor Ttle Wreless LAN Based Indoor Poston and Its Smulaton Author(s) Ktasuka, Teruak; Nakansh, Tsune CtatonIEEE Pacfc RIM Conference on Comm Computers, and Sgnal Processng
More informationModeling and Simulation of New Encoding Schemes for High-Speed UHF RFID Communication
Modelng and Smulaton of New Encodng Schemes for Hgh-Speed UHF RFID Communcaton Sang-Hyun Mo, J-Hoon Bae, Chan-Won Park, Hyo-Chan Bang, and Hyung Chul Park In ths paper, we present novel hgh-speed transmsson
More informationPerformance Analysis of Multi User MIMO System with Block-Diagonalization Precoding Scheme
Performance Analyss of Mult User MIMO System wth Block-Dagonalzaton Precodng Scheme Yoon Hyun m and Jn Young m, wanwoon Unversty, Department of Electroncs Convergence Engneerng, Wolgye-Dong, Nowon-Gu,
More informationFPGA Implementation of Fuzzy Inference System for Embedded Applications
FPGA Implementaton of Fuzzy Inference System for Embedded Applcatons Dr. Kasm M. Al-Aubdy The Dean, Faculty of Engneerng, Phladelpha Unversty, P O Box 1, Jordan, 19392 E-mal: alaubdy@gmal.com Abstract:-
More informationA Simple, Efficient, and EMI-Optimized Solar Array Inverter
A Smple, Effcent, and EMI-Optmzed Solar Array Inverter K. H. Edelmoser, Insttute of Electrcal Drves and Machnes Techncal nversty Venna Gusshausstr. 27-29, A-14 Wen ASTRIA kedel@pop.tuwen.ac.at F. A. Hmmelstoss
More informationApplications of Modern Optimization Methods for Controlling Parallel Connected DC-DC Buck Converters
IJCSI Internatonal Journal of Computer Scence Issues, Volume 3, Issue 6, November 26 www.ijcsi.org https://do.org/.2943/266.559 5 Applcatons of Modern Optmzaton Methods for Controllng Parallel Connected
More informationc 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media,
c 2009 IEEE. Personal use of ths materal s permtted. Permsson from IEEE must be obtaned for all other uses, n any current or future meda, ncludng reprntng/republshng ths materal for advertsng or promotonal
More informationAdaptive System Control with PID Neural Networks
Adaptve System Control wth PID Neural Networs F. Shahra a, M.A. Fanae b, A.R. Aromandzadeh a a Department of Chemcal Engneerng, Unversty of Sstan and Baluchestan, Zahedan, Iran. b Department of Chemcal
More informationHardware Implementation of Fuzzy Logic Controller for Triple-Lift Luo Converter
Hardware Implementaton of Fuzzy Logc Controller for Trple-Lft Luo Converter N. Dhanasekar, R. Kayalvzh Abstract: Postve output Luo converters are a seres of new DC- DC step-up (boost) converters, whch
More informationTotal Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
21st Internatonal Conference on VLSI Desgn Total Power Mnmzaton n Gltch-Free CMOS Crcuts Consderng Process Varaton Yuanln Lu * Intel Corporaton Folsom, CA 95630, USA yuanln.lu@ntel.com Abstract Compared
More informationTriferential Subtraction in Strain Gage Signal Conditioning. Introduction
Trferental Subtracton n Stran Gage Sgnal Condtonng Karl F. Anderson Vald Measurements 3751 W. Ave. J-14 Lancaster, CA 93536 (661) 722-8255 http://www.vm-usa.com Introducton The general form of NASA's Anderson
More informationLecture 10: Bipolar Junction Transistor Construction. NPN Physical Operation.
Whtes, EE 320 Lecture 10 Page 1 of 9 Lecture 10: Bpolar Juncton Transstor Constructon. NPN Physcal Operaton. For the remander of ths semester we wll be studyng transstors and transstor crcuts. The transstor
More informationMOSFET Physical Operation
March, 007 MOSFET Physcal Operaton Some fgures of ths presentaton were taken from the nstructonal resources of the followng textbooks: B. Razav, Desgn of Analog CMOS Integrated Crcuts. New York, NY: McGraw
More informationSpace Time Equalization-space time codes System Model for STCM
Space Tme Eualzaton-space tme codes System Model for STCM The system under consderaton conssts of ST encoder, fadng channel model wth AWGN, two transmt antennas, one receve antenna, Vterb eualzer wth deal
More informationSimulation of Distributed Power-Flow Controller (Dpfc)
RESEARCH INVENTY: Internatonal Journal of Engneerng and Scence ISBN: 2319-6483, ISSN: 2278-4721, Vol. 2, Issue 1 (January 2013), PP 25-32 www.researchnventy.com Smulaton of Dstrbuted Power-Flow Controller
More informationImplementation of Fan6982 Single Phase Apfc with Analog Controller
Internatonal Journal of Research n Engneerng and Scence (IJRES) ISSN (Onlne): 2320-9364, ISSN (Prnt): 2320-9356 Volume 5 Issue 7 ǁ July. 2017 ǁ PP. 01-05 Implementaton of Fan6982 Sngle Phase Apfc wth Analog
More informationDigital Differential Protection of Power Transformer Using Matlab
Chapter 10 Dgtal Dfferental Protecton of Power Transformer Usng Matlab Adel Aktab and M. Azzur Rahman Addtonal nformaton s avalable at the end of the chapter http://dx.do.org/10.5772/48624 1. Introducton
More informationA Novel Soft-Switching Converter for Switched Reluctance Motor Drives
WEA TRANACTION on CIRCUIT and YTEM A Novel oft-wtchng Converter for wtched Reluctance Motor rves KUEI-HIANG CHAO epartment of Electrcal Engneerng Natonal Chn-Y Unversty of Technology 35, Lane 15, ec. 1,
More informationA Feasible Approach to the Evaluation of the Tractions of Vehicle Wheels Driven by DC Motors
A Feasble Approach to the Evaluaton of the Tractons of Vehcle Wheels Drven by DC Motors Jeh-Shan Young Insttute of Vehcle Engneerng, Natonal Changhua Unversty of Educaton Changhua, Tawan, R.O.C. and Sheng-You
More informationNetwork Reconfiguration in Distribution Systems Using a Modified TS Algorithm
Network Reconfguraton n Dstrbuton Systems Usng a Modfed TS Algorthm ZHANG DONG,FU ZHENGCAI,ZHANG LIUCHUN,SONG ZHENGQIANG School of Electroncs, Informaton and Electrcal Engneerng Shangha Jaotong Unversty
More information