High Speed ADC Sampling Transients

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1 Hgh Speed ADC Samplng Transents Doug Stuetzle Hgh speed analog to dgtal converters (ADCs) are, at the analog sgnal nterface, track and hold devces. As such, they nclude samplng capactors and samplng swtches. The acton of these elements as they alternately track the nput sgnal and hold ts voltage produces small transent voltages and currents. These transents can ntroduce dstorton nto the crcutry that drves the ADC analog nput. Hgh resoluton ADCs are partcularly susceptble to these effects. Consder a typcal 6-bt ADC wth a V peak to peak nput range. The analog nput voltage change requred to affect the dgtal output by one bt s on the order of µv. These hgh performance converters are almost always dfferental nput devces, but the analyss here starts wth a sngle-ended crcut model to show the transent effects. The degree to whch these effects appear n a true dfferental settng depend heavly on the common mode rejecton rato of the sgnal source drvng the ADC and the ADC tself. INPUT TRACK AND HOLD MODEL The nput crcut to mplement the track and hold functon s shown n Fgure. Ths s a smplfed model, but t serves to llustrate the charge transfer effects that can dstort the nput waveform. There are three CMOS swtches, a sample capactor and an op amp. The crcut s drven by a sample clock, whch can operate at MHz or more. It alternates between two phases: the track phase, n whch the nput analog voltage s placed onto a sample capactor, and the hold phase, whch dsconnects the sample capactor from the analog nput and makes the capactor voltage avalable to the dgtal crcutry that quantzes t. One edge of the sample clock say the rsng edge ntates the track phase, and the next edge say the fallng edge ntates the hold phase. Note that the transton from the track phase to the hold phase s comprsed of two transton states. The transton states exst because the three swtches change state n sequence not all at once. The transton from track phase to hold phase, along wth the transton states, s shown n Fgure. Note the drectons of the transent currents on the sample and swtch capactances. In some cases the current changes drecton as the swtch control voltage ramps up/down. Durng the transton from track to hold phase, transent charges can be mposed on the sample capactor, alterng the fnal voltage on ths capactor at the begnnng of the hold phase. The reason for these errant charges s the nherent channel capactance of the CMOS swtch. Each of the three CMOS swtches ncludes a parastc capactance from gate to channel. When the control voltage on the swtch changes, a small amount of charge s transferred to the channel. Fgure. Track and hold model for sngle-ended sgnal In the track phase, the condtons are: Swtches SW and are closed; the control voltage on these swtches s SW V C SW V C.8VDC. The channel capactances of the swtches are charged to.8v. Swtch s open; the control voltage on ths swtch s zero volts DC. The channel capactance of ths swtch s charged to zero volts. January : LT Journal of Analog Innovaton

2 desgn deas Fgure. The transton from track phase to hold phase va transton states Here s the sequence of events that make up the transton from track to hold phase:. The control voltage V C for SW ramps to zero volts DC. (a) track phase SW V C SW V C The voltage at Node B s pulled lower by the charge on SW. Some of the charge on the channel of SW flows to the sample capactor; the effect s to ncrease the charge on the sample capactor. capactor ncreases.. The control voltage V C for SW ramps to zero volts DC. (b) transton state SW V C SW The voltage at Node A s pulled lower by the charge on SW. Some of the charge on the channel of SW flows to the sample capactor; the effect s to decrease the charge on the sample capactor. capactor decreases.. The control voltage V C for ramps to.8vdc. The voltage at Node A s pulled hgher by the channel capactance of. (c) transton state SW SW capactor ncreases. At the end of ths sequence, the charge, and hence the voltage, on the sample capactor has changed. (d) hold phase V C SW SW January : LT Journal of Analog Innovaton

3 The nput network that lnks the analog sgnal source to the ADC nput contrbutes to the transent charge effects outlned here. In partcular, elements that store charge, or delay the transt of charge, can produce addtonal artfacts as the swtches change state. Generally the nput network conssts of a drver amplfer, a smple RC network usually lowpass and some length of transmsson lne. Some length of transmsson lne s unavodable, partcularly as ADC packages become smaller. Fgure. End of trackng phase, wth swtch parastcs SW, SW, Fgure. End of trackng phase, wth swtch parastcs, RC network and ps transmsson lne SW, SW, Fgure. Detal of transents on the sample capactor voltage SW, SW, January : LT Journal of Analog Innovaton

4 desgn deas TIME DOMAIN MODELING The tme doman behavor of a typcal nput track and hold crcut can be modeled n PSPICE. Here are the assumed parameters: Input sgnal = MHz snewave, V peak Sample capactance = pf Swtch channel capactance =.pf Swtch control voltages = /.8V Swtch ramp tme = ps The effects of the swtchng events are more evdent f the three events are separated by ns each. Fgure shows each of the swtchng events, startng wth swtch SW openng at ns. At 7ns, SW opens; closes at 9ns. Note that once the trackng phase s complete, the op amp output voltage matches that of the sample capactor. Ths voltage, however, dffers from the nput voltage because of the charge njected by the swtches. at ps ntervals. Less evdent but stll present are the transents and ther echoes on the sample capactor. Note that f the swtch events are separated enough n tme for the transents to settle out before enterng the hold phase, ther effect on the fnal sample capactor voltage decays to zero. Fgure shows these transents on the sample capactor voltage n greater detal. In practce the three swtch events are separated not by ns, but by ps or so. In ths short wndow, transents have lttle tme to decay before the last swtch s closed and the voltage on the sample capactor s captured. Ths gans mportance wth regard to the echoes from the transmsson lne structure. Fgure 6 shows ths behavor. The transents on the sample capactor are shown n detal n Fgure 7. It has been shown that charge njecton from the sample swtches affects the fnal charge stored on the sample capactor. Ths s a classc ssue wth track and hold crcuts. We have also seen that settlng transents can further affect ths fnal charge, and hence the voltage passed on to the dgtal quantzaton porton of the ADC for that sample. MULTIPLE SAMPLE EFFECTS Thus far we have examned the effect of these artfacts upon a sngle sample. The next step s to expand the feld of vew to see how the sample capactor voltages dffer from the nput voltages at several sample nstants. Fgure 8 llustrates ths. The nput sgnal s a MHz sne wave, and the sample rate s Msps. The end of each track phase s denoted by a blue dashed vertcal lne. The error voltage on the sample capactor s defned as the INPUT NETWORK EFFECTS The nput network that lnks the analog sgnal source to the ADC nput contrbutes to the transent charge effects outlned above. In partcular, elements that store charge, or delay the transt of charge, can produce addtonal artfacts as the swtches change state. Generally the nput network conssts of a drver amplfer, a smple RC network usually lowpass and some length of transmsson lne. Some length of transmsson lne s unavodable, partcularly as ADC packages become smaller. Smply conveyng the nput sgnal, whch s always dfferental, from the dscrete network to the ADC nput pns nvolves dstance. So a dfferental transmsson lne structure s used. Examnaton of these artfacts n Fgure shows the transents mposed upon the nput sgnal. In ths case the nput network conssts of a p secton RC lowpass and a ps transmsson lne. The nput sgnal shows the ntal transent once SW opens, and echoes of ths transent appear Fgure 6. Fast swtch behavor Fgure 7. Detal of transents on the sample capactor wth fast swtch events SW, SW, SW, SW, January : LT Journal of Analog Innovaton 7

5 The track and hold crcut at the nput of an ADC necessarly njects transent charges nto the crcut that drves t. These charges can affect the accuracy of the voltage stored on the sample capactor at each sample nstant. The key nterval s the tme t takes to transton from the track phase to the hold phase. Durng ths tme swtches are toggled and the voltage stored on the sample capactor can be perturbed. dfference between the sample capactor voltage and the nput sgnal voltage. The real error of nterest conssts of the dfference between the sample capactor voltage at the end of the hold phase and the nput voltage at the end of the track phase. A set of these error samples has been plotted for one sgnal cycle and plotted n Fgure 9. Note that the devaton from true nput sgnal values s a tme-varyng quantty; t does not represent a DC offset that can be removed or gnored. It appears, most lkely, as multple harmonc and spurous sgnals n the dgtzed ADC output. COMMON MODE VERSUS DIFFERENTIAL MODE Havng explored all of ths, there s an mportant factor that greatly reduces the effect of these transents on the output sgnal. Ths factor s the common mode rejecton of the ADC. The ADC nput s dfferental, and accepts a dfferental nput sgnal. The swtch effects, however, are not dfferental; they are the same on both sdes of the nput crcut. Snce all of the swtch charge transfers are common mode, they are rejected by the ADC. So the net effect of these dstortons on the dgtally represented output sgnal depends not only upon the magntude of the errant charges, but also on the common mode rejecton of the ADC. Fgure 8. Sample capactor values vs source voltages CONCLUSION The track and hold crcut at the nput of an ADC necessarly njects transent charges nto the crcut that drves t. These charges can affect the accuracy of the voltage stored on the sample capactor at each sample nstant. The key nterval s the tme t takes to transton from the track phase to the hold phase. Durng ths tme swtches are toggled and the voltage stored on the sample capactor can be perturbed. ERROR (mv) AMPLITUDE (V) SAMPLE CAPACITOR ERROR VOLTAGE TRACK PHASE END V ADC(IN) Fgure 9. Error voltage at sample nstants Fortunately the ADC nput s typcally dfferental and the undesred transents are common mode. Nevertheless, any nput crcut elements that store large amounts of charge, or cause charge to bounce back and forth wll exacerbate the charge dsturbances. The latter effect s usually the result of transmsson lne structures whose round trp delay falls wthn the transton tme between the track and hold phases. In partcular, f there are crcut elements at the nput end of the lne that are reflectve relatve to the transmsson lne, these contrbute to the magntude of the reflectons. All of the precedng modelng was done usng LTspce and a smple nput crcut model. There s no practcal way to estmate the magntude or spectral dstrbuton of the dstortons outlned, but the analyss suggests that mnmzng the storage and reflecton of transent charges wll reduce them. n 8 January : LT Journal of Analog Innovaton

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