High Performance Integer DCT Architectures For HEVC

Transcription

1 Hgh Performance Integer DT Archtectures For HEV V.Sruth, V.Rekha,. Subtha,.Sugtha, S. Jeya Anusuya.E., V. Satheesh kumar.e.,,,, Dept Of Electroncs and ommuncaton Engneerng, Assocate professor, Dept Of Electroncs and ommuncaton Engneerng,,,,, T.J.S Engneerng ollege, Peruvoyal Abstract- Our proposed system proceeds VLSI archtecture for nteger Dscrete osne Transform (nteger DT), whch s used n real tme Hgh Effcency Vdeo odng (HEV) applcatons. It has -pont D-Integer DT archtecture, whch ncludes sgned confgurable carry save adder tree based multpler unt. So, the depth of the archtecture falls wthn the bounds of O (log ). The proposed D archtecture s used to perform one -pont or Integer DTs n parallel. The proposed D archtecture s used to desgn D folded and parallel desgns. The performance results show that the proposed archtecture gves better performance compared wth exstng archtectures usng nm OS TS lbrares. The proposed *-pont parallel Integer DT acheves 9.% of mprovement n worst path delay compared wth odd-even decomposton based archtecture. Keywords- Integer DT, HEV, D DT Archtecture, D DT Archtecture Page 9 I. ITRODUTIO Dgtal sgnal processors (DSPs) are very mportant for the real-tme processng of real-world dgtzed data to do hgh-speed numerc calculatons used for lot of applcatons from basc consumer electroncs to sophstcated ndustral nstrumentaton. The dscrete transform s used to change the representaton of a sgnal from one doman to another for reducng the complexty of a partcular dgtal sgnal processng applcaton. Dscrete cosne transform (DT) s very powerful transformaton used n mage compresson. The crcut complexty of DT s greater than nteger DT because DT s floatng pont and the nteger DT s fxed pont. So, the delay of the multpler adders used n the adder. The output can be stored at one partcular * Buffer. The outputs of I th, * -Buffer are b, b, b8, b, and b, whch are the resultants of,, 8,, and -pont Integer DTs respectvely. Each *-Buffer s made up of numbers of regsters and -to- multplexers wth common select lne. ultmeda communcaton typcally nvolves the transfer of large amount of data Therefore, compresson of vdeo, audo, and mage data s essental for a cost-effcent use of exstng communcaton channels and storage meda. The DT helps separate the mage nto parts of dfferng mportance wth respect to the mage's vsual qualty. The DT chp presented here wll form a part of one such mage compresson system. The system s based on a -D block cosne transform codng scheme, where the mage s of sze x and each block s of sze 8x8. There are two man computatonal task nvolved. The frst conssts of computng the -D DT on blocks of sze 8x8, whle the second task conssts of quantzng the transform coeffcents usng scalar quantzes. We present an mplementaton of a chp that computes the DT of an 8x8 element block. The DT applcaton can have many purposes Such as flterng, teleconferencng, hgh-defnton televson (HDTV), speech codng, mage codng, data compresson, and more. All of these use DT algorthm for compresson and/or flterng purposes. The DT has the energy packng capabltes and also approaches the statstcally optmal transform n decor relatng a sgnal. It was mplemented wth dscrete components at the board level. Ths was followed by ts mplementaton usng general purposes (DSP) chps. Also, mage compresson boards and multprocessor workstatons based on DT have been developed by ndustry. For our proect, t s usng the algorthm for mage compresson purpose. Wth hgh speed and low power desgn, t s best for handheld devce use. Such devce consumes power from ts battery. It s an mpact to have low power consumpton for the devce, because battery carry lmted power. Therefore, the desgn must have low power consumpton components to compose the chp. Otherwse, the devce wll be force to offlne due to nsuffcent power supply. Furthermore, hghspeed algorthm s necessary for urge of current software and operatng system. The performance of the chp s optmzed and specfed for mage compresson purposes. II. LITERATURE SURVE Hgh performance ultpler less DT Archtecture for HEV, Wenun Zhao, Takao Onoye, and Tan Song()

2 There are numerous vdeo compresson format for storage or transmsson of dgtal vdeo content. Hgh Effcency Vdeo odng (HEV) s a vdeo compresson standard, a successor to H./PEG- Advanced Vdeo odng (AV). In ths paper, we propose an effcent archtecture for the computaton of, 8, and pont DT used n HEV standard. The archtecture uses the anoncal Sgned Dgt (SD) representaton and ommon Subexpresson Elmnaton (SE) technque to perform the multplcaton wth shft-add operaton. A Reconfgurable ult-transform VLSI Archtecture Supportng Vdeo odec Desgn Kanwen Wang, Jaln hen, We ao, ng Wang, Lngl Wang. The proposed system for the real-tme processng of 8P HD vdeo, whch can support both forward and nverse transforms of PEG usng mult transform VLSI archtecture. The (R) algorthm s the multple constant multplcaton algorthm wth fusng strateges, whch s provded to generate constant multplers n the matrx calculaton blocks. ult-mode parallel and folded VLSI archtectures for Dfast Fourer transform ohamed Asan Basr and oor ahammad Sk. Ths paper proposes effcent FFT VLSI archtectures usng folded/parallel mplementaton. The folded FFT archtecture has number of cycles requred to complete the operaton s less than sngle/mult-path delay commutator (D) archtectures. -pont FFT s mplemented by usng one /-pont FFT wthout much extra hardware. Both the proposed archtectures are mplemented for radx-,. III. EISTIG SSTE In all the exstng archtectures, thread-shft network based multpler s used. So, the delay of the multpler s based on the number of adders used n the add-shft network. The exstng technque s add-shft network. It uses confgurable carry save addton Dsadvantages of Exstng System: In the proposed archtecture, confgurable carry save adder (SA) tree based multpler s used. It shows the seres of multplexers used for confgurable carry save addton based multplcaton n the proposed archtecture. The maxmum number of values to be added n the confgurable carry save addton based -pont Integer DT s log = log =.IV. The mathematcal representatons of the -D Forward DT and the -D IDT are represented n the followng: Formulae Forward DT F( u, v) ( u) ( v)[ ( ) ( ) x (x ) u (y) v f ( x, y)cos cos ] y Inverse DT ( ) ( ) (x ) u (y) v f ( x, y) [ ( u) ( v) F( u, v)cos cos ] u v Where: (u) =, (v) = for u,v = (u) = through -; =, 8, or, (v) = for u,v = In the desgn, = 8. F(u,v) s called the (u,v)th transform coeffcent. The above formula shows that the -D DT can be computed by applyng the -D DT to each of the columns of the matrx separately and then applyng the - D DT to each of the rows separately. Ths s the reparablty property of the -D DT. All the -D DT processors developed so far have made use of ths property of the -D DT. In ths report, we present the desgn of the -D DT functon under VLSI archtecture for mage processng. The desgn layout wll be at cells block level, whch t does not show n great detal for the entre chp desgn. DT Algorthm V. WORKIG PRIIPLE ultplcaton requrement s more. ore delay Hgh Power IV. PROPOSED SSTE -D DT Archtecture: The two dmensonal (-D) Dscrete osne Transform (DT) forms the cornerstone of many mage processng standards such as JPEG and PEG. any proposed solutons are based on row column decomposton mplementaton whch allows the -D DT to be mplemented by two one dmensonal (-D) DTs separated by a transposton memory. Page

3 Page -D DT Archtecture: The dervaton of the l-d DT archtecture can be more easly explaned by examnng the l- D DT n matrx form, gven as below: ] ]*[ [ ] [ () () () () Where (k) = os( K/). As multplers are m tmes more complex than adders, the am s to reduce the number of multplcatons at the expense of addtons. The sparse matrx approach acheves ths by manpulatng the terms n the nput matrx as shown n equaton. () () () () () () () () * () () The crcut conssts of 8 multplers and 8 adders and 8 subtracters connected n a regular matrx of cells. Bt seral logcal adders and subtracter cells have been used and the array multplers have been mplemented. The bt seral multpler wll be ppelned every two cells. By usng K-ap, The seral logcal adder and subtracter equaton s mplemented. The followng table showng the equatons: Sum = A B n Dfference = A B bn arry = AB + An +Bn Borrow = A B + A bn + Bbn onsder the two unsgned bnary numbers and that are and bts wde respectvely. and n a bnary representaton are as below: x x, y y Wth, {,}. The multplcaton operaton s then defned as follow: * k x z k y x z x y x y The multplcand s consecutvely multpled wth every bt of the multpler, resultng n a number of partal products. These ntermedate results are adder after the proper shftng has been appled. Use the algorthms of two bnary number multplcatons to mplement the array multpler. The array multpler conssts numerous of AD and full adder. Ths type of multpler requres -bt (ultplcand) x -bt (ultpler) number of AD gates and full adders. The transpose component s an array of 8x8, -bt shft regsters. It receves the output from the -D DT (row), and transposes the row to the column of the second -D DT nput. The shft regster used to store the bts nto regsters. Then, connect the metal plate to other shfter s nput, and shft the each bts arrange as column format. VI. FLOWHART Fg. Flow chart of D DT Archtecture Fg. Flow chart of D-DT Archtecture VII. PROPOSED DT ARHITETURE Proposed block archtecture used for -pont D- Integer DT. In -pont D-Integer DT, the co-effcent matrx s n the sze of _. The nput sgnal sample values should be multpled wth the co-effcent, whch forms the matrx-vector multpler. In all the exstng archtectures, the add-shft network based multpler s used. So, the delay of the

4 multpler s based on the number of adders used n the addshft network. In the proposed archtecture, confgurable carry save adder (SA) tree based multpler s used. Fg. (a) shows the seres of multplexers used for confgurable carry save addton based multplcaton n the proposed archtecture. Fg. Proposed Archtecture The maxmum number of values to be added n the confgurable carry save addton based -pont Integer DT s log = log =. For example, the multplcaton of the co-effcent 8 wth the nput sgnal sample value x s equal to 8x = x +x +x +x +x. The mnmum number of values to be added n the confgurable carry save addton based -pont Integer DT s. For example, the multplcaton of the co-effcent wth the nput sgnal sample value x s equal to x = x + x + x + x + x. So, the correspondng left-shfted (power of two) nput sgnal values are sent as the nput of the seres of multplexers used n Fg. (a), whch s named as ell. The maxmum possble cells used to obtan one multplcaton result s. Therefore, fve ells are used n Fg. (b). So, the maxmum possble levels of the confgurable carry save adder (SA) tree s log =. The Sum and arry from the fnal carry save adder are added. The proposed block archtecture (Block) used for - pont D-Integer DT wth (a) Seres of multplexers used for confgurable carry save addton based multplcaton (ell) (b) confgurable carry save adder tree based multplcaton unt (c) Seres of multplexers used to fnd the resultant sgn bts for the multplcaton. Fg. VLSI archtectures for proposed -pont D-Integer DT The overall archtecture of proposed -pont D- Integer DT, where the nputs are from numbers of Blocks as shown n Fg.. Therefore, log = levels of sgned fxed pont adders are used. Therefore, the crtcal path depth of the sgned adder tree (Tadd; pro delay) used n the -pont proposed Integer DT archtecture s (log)t(add). Here, T (add) represents the crtcal path depth of the sgned adder. The proposed -pont D archtecture s used to perform one -pont or two -pont or four 8-pont or eght -pont or sxteen -pont Integer DTs n parallel. The -pont Integer DT output s fous; oug. Fg. shows the -Buffer archtecture, where numbers of *-Buffers are used. The *-Buffer nputs are the outputs from the column of -to- multplexers, wth select lne se. Here, se = ; ; ;, and for ; ; 8; ; and -pont Integer DTs respectvely. Each *-Buffer s made up of numbers of regsters and -to- multplexers wth common select lne. The select lnes used n the *-Buffers,,..., and are en, en,...en, and en respectvely. The output from Fg. can be stored at one partcular *-Buffer wth correspondng select lne as. The *-Buffer archtecture s shown n Fg.. The outputs of th *-Buffer are b, b, b8, b, and b, whch are the resultants of,, 8,, and -pont Integer DTs respectvely. Here, en = to mantan the values ( values) stored n the buffer and en = f the the new value. Page

5 Fg. Proposed DT FORWARD TRASFOR (DT): Fg. VLSI archtectures for -Buffer Frst Stage of Forward Transform: The frst stage of the forward transform conssts of multplcaton of the result of the D. The nput nto the second stage of the forward transform s the output matrx from the frst stage of forward transform whch s a matrx wth only the D element. The output of multplcaton wth DT wll be a matrx wth frst column elements. onsequently, the scalng requred after the frst stage of the forward transform for the output to ft wthn bts s S T = -(B-+9). Fg. Archtecture of *-Buffer * -Buffer archtecture: The output from Fg. can be stored at one partcular *-Buffer wth correspondng select lne as. The *-Buffer archtecture s shown n Fg.. The outputs of th * -Buffer are b, b, b8, b, and b, whch are the resultants of,, 8,, and -pont Integer DTs respectvely. Here, en = to mantan the values ( values) stored n the buffer and en = f the the new value s obtaned. Second Stage of Forward Transform: The second stage of the forward transform conssts of multplcaton of the result of the frst transform stage wth D. The nput nto the second stage of the forward transform s the output from the frst stage whch s a matrx wth all elements n the frst row. All other elements wll be zero. The output of multplcaton wth wll be a matrx wth only a D value. Ths mples that the scalng requred after the second stage of transform s n S T = -(-B) order for the output to ft wthn bts. Page

6 VIII. TEHOLOG USED The multpler unt used n the latest -pont Integer DT archtectures s n the form of add-shft network, whereas n the proposed archtecture, sgned confgurable carry save adder tree s used. Therefore, the depth of the archtecture falls wthn the bounds of O(log ). The proposed D archtecture s used to perform one -pont or multple,,...- pont Integer DTs n parallel. The performance results show that the proposed archtecture gves better performance compared wth exstng archtectures usng nm OS TS lbrares. odel Sm software s used to check ths model. For I development they have three processes n lnx software. a. heck syntax b. Pn assgnment c. Implementaton heck syntax s used to check our desgn havng any error. After fnshng ths process we allocate the nput and output pns by usng pn assgnment. In the fnal process s mplementaton. Here we mplement the desgn nto our assgnng pns. Then we convert our code nto bt fle then after we dump ths bt fle n to FPGA spartan (S PQ8) and verfed t. professor, whose contrbuton n gvng suggestons and encouragement helped us for ths proect to complete. II. RESULTS AD OLUSIO The multplers are, at less, twce faster than the conventonal desgn, and consume half of the power. Ths can be done by gnore the zeros n the multply constant and the nsgnfcant parts of the answer. The crcut s further reduced. Therefore, t consumes less power. The reducton wll more stages, because the scares of resources. Ths can be countered by dong mult-stage n one perod. The multpler operaton wll take one perod and one or two adders operatons wll perform n one perod. Then, there wll be less power consumpton wthout comprsng the speed. The D DT and Transpose s fnshed and the smulaton s shown above. The area of the D DT chp s.8mm x.mm. The total delay 8.ns. The Transpose s 9ns. The area s.mmx.mmthe results s the same as the calculaton. We don t have tme to construct the D DT. But, t s smple. It ust need to connect two D DT to the transpose. The performance results show that the proposed archtecture gves good mprovement as compared wth exstng archtectures. The Snapshot below gves the clear elaboraton of applcaton. Devce Utlzaton Summary -Pont DT I. ADVATAGES Better ompresson Performance omputaton Performance s good Page. APPLIATIOS Used n health department. Human welfare It s used to montor ndustral radaton levels. I. AKOWLEDGEET We would lke to thank all those who provde us the possblty to propose ths proect. A specal grattude to our Proect Gude r. V. Satheesh kumar, Assstant professor and Proect coordnator rs. S. Jeya Anusuya, Assocate Fg.8 Smulaton Snapshot of -POIT DT REFEREES [] ohamed Asan Basr and oor ahammad Sk, ultmode Parallel and Folded VLSI Archtectures for D-Fast Fourer Transform, Integraton, the VLSI Journal, Elsever, vol., pp. -, Sept.. [] Fe Lang, ulan Peng, and Jzheng u, A lghtweght HEV encoder for mage codng, IEEE

7 Internatonal onference on Vsual ommuncatons and Image Processng (VIP), pp. -, ov.. [] Pramod Kumar eher, Sang oon Park, Basant Kumar ohanty, Khoon Seong Lm, and huohao eo,, Effcent Integer DT Archtectures for HEV, IEEE Transactons on rcuts and Systems for Vdeo Technology, vol., no., pp. 8-8, Jan.. [] Pa-Tse hang and Tan Sheuan hang, A Reconfgurable Inverse Transform Archtecture Desgn for HEV Decoder, IEEE Internatonal Symposum on rcuts and Systems (ISAS), pp. -9, ay.. [] Honggang Q, Qngmng Huang, and Wen Gao, A Low- ost Very Large Scale Integraton Archtecture for ult Standard Inverse Transform, IEEE Transactons on rcuts and Systems - II, Express Brefs, vol., no., pp. -, July. [] Khan Wahd, uhammad artuza, ousum Das, and arl crosky, Resource Shared Archtecture of ultple Transforms for ultple Vdeo odecs, IEEE Internatonal anadan onference on Electrcal and omputer Engneerng (EE), pp. 9-9, ay. [] Kanwen Wang, Jaln hen, We ao, ng Wang, Lngl Wang, and Jarong Tong, A Reconfgurable ult- Transform VLSI Archtecture Supportng Vdeo odec Desgn, IEEE Transactons on rcuts and Systems - II, Express Brefs, vol. 8, no., pp. -, July. [8] ao Zyou, He Wefeng, Hong Lang, He Guanghu, and ao Zhgang, Area and Throughput Effcent IDT/IDST Archtecture for HEV Standard, IEEE Internatonal Symposum on rcuts and Systems(ISAS), pp. -, June. [9] Hong Lang, He Wefeng, Zhu Hu, and ao Zhgang, A ost Effectve -D Adaptve Block Sze IDT Archtecture for HEV Standard, IEEE th Internatonal dwest Symposum on rcuts and Systems (WSAS), pp. 9-9, Aug.. [] Wenun Zhao, Takao Onoye, and Tan Song, Hgh- Performance ultplerless Transform Archtecture for HEV, IEEE Internatonal Symposum on rcuts and Systems, pp. 8-, ay. [] ohamed Asan Basr and oor ahammad Sk, An Effcent VLSI Archtecture for Dscrete Hadamard Transform, IEEE Internatonal VLSI Desgn onference, pp. -, Jan.. [] Rcardo Gonzalez, Benamn. Gordon, and ark A. Horowtz, Supply and Threshold Voltage Scalng for Low Power OS, IEEE Journal of Sold State rcuts, vol., no. 8, pp. -, Aug Page