1. Introduction. Key words: FPGA, Picoblaze, PID controller, HDL, Simulink

Transcription

1 FPGA Desgn and Implementaton of Dgtal PID Controller based on floatng pont arthmetc Pourya Alnezhad 1, Arash Ahmad 1- M.Sc. student of Electrcal and communcaton engneerng Shahd Bahonar Unversty, Iran - B.Sc. of Electrcal and Electroncs Engneerng Karaj Islamc Azad Unversty, Iran Abstract hs paper proposes a method for the desgn of dgtal PID controller on Feld Programmable Gate Array wth floatng pont arthmetc. Here we use Matlab HDL coder toolbox for mplementng PID controller. Also an 8bt mcroprocessor called Pcoblaze s programmed on FPGA chp to control perpherals lke A/D and D/A converters, nput output bottoms, character LCD etc. Requred logcal and mathematcal operators lke comparson and summaton are overloaded to accept floatng pont numbers as nput so calculatons would have hgher precson than software based PID controllers. Smulnk model s used to plot the tme response of PID controller. VHDL code generaton and programmng s performed n ISE9 software from Xlnx Company. We used Coregen for mplementng floatng pont blocks. he proposed method was mplemented practcally on Xlnx Spartan-3E FPGA Board. Key words: FPGA, Pcoblaze, PID controller, HDL, Smulnk 1. Introducton A control system conssts of two subsystems, a plant and a controller. he plant s an entty controlled by the controller [1]. he controller can be ether analog or dgtal. Generally, an mplementaton of dgtal PID controller ncludes the use of mcroprocessors or mcrocontrollers. he memory holds the applcaton program whle the processor fetches, decodes, and executes the program nstructons. One of dsadvantages of ths method s the speed of operatons because the operatons depend on software whch has a sequence of nstructons and commands whch needs many machne cycles to execute. herefore, FPGA-based dgtal PID controller s proposed because the operatons on FPGA are hardware compatble operatons. Better speed performance could be acheved because all operatons are down n parallel. Proposed FPGA-based dgtal PID controller uses floatng pont math operands for computatons. Here we overloaded these computatons for floatng pont arthmetc to acheve better accuracy. Modern FPGAs and ther dstngushable capabltes have been advertsed extensvely by FPGA vendors. Moreover, some refereed artcles addressed the advantages of utlzng these powerful chps []. Recently, Spartan II and III FPGA famles from Xlnx have been successfully utlzed n a varety of applcatons whch nclude nverters, communcatons, mbedded processors, and mage processng.

2 Here we use Spartan-3E toolkt from Xlnx Company to mplement our desgned PID controller. So many works have been down to mplement conventonal PID controllers but a few studes were made for mplementng PID controllers on FPGA s. Gupta and Khare [1] proposed a method to desgn the PID controller n Smulnk but no practcal works were made. XU and SHUANG [3] desgned a Fxed-pont Dgtal PID Controller and showed that hgh relablty and fast response speed wth wde dynamc range could be acheved. Sonol and Nagabhushan [4] used FPGA based PID Controller for controllng DC Motor system. Behnam and Mansouryar [5] desgned a dgtal PID Controller and Encoder Usng Xlnx System Generator lbrary n Smulnk. Xlnx System Generator s a Smulnk lbrary block set provded by Xlnx Company to generate FPGA compatble models. In [6] a PID controller desgned to acheve a balance between the speed and the exhausted FPGA resources. [7] Presents a novel technque for mplementaton of an effcent FPGA based dgtal PID controller for the moton control of a permanent magnet DC motor. In [8] Patel & sngh desgned FPGA-based all Dgtal PID Controller on Spartan3e XC3S100E FPGA. In ths paper, we develop a new PID controller model based on floatng pont arthmetc. In secton dscrete PID model s revewed and a Smulnk model s desgned and smulatons are performed to verfy model. Also some practcal ssues lke Untwndup mplementaton are consdered. Secton 3 llustrates floatng pont numbers and HDL code generaton. Secton 4 shows practcal results of desgned PID controller and also descrbes some practcally used tools. Fnally, secton 5 concludes the paper..dscrete PID model At frst we need a complete model of the dgtal controller. We start our work by contnues model and then the dscrete model could be acheved wth some manpulatons. Consder a PID and the Planet model as shown n Fg 1. Fg 1. A typcal Planet model As we know PID controller conssts of proportonal, dervatve and ntegral coeffcents. he controller could be shown n tme doman by Eq.1. u(t) = k p [e(t) + 1 t e(τ)dτ + d de(t) ] 0 dt k p s the proportonal coeffcent and e(t) shows controller nput sgnal. and d are ntegral and dervatve coeffcents respectvely. In Laplace doman we can wrte Eq.1 as follows: (1) H(s) = K p [1 + 1 s + s d ] ()

3 Now n order to have dscrete form we must transfer Eq. to z doman. We can determne a dgtal mplementaton of ths controller by usng a dscrete approxmaton for the dervatve and ntegraton [9].Impulse nvarance or blnear methods [10] could be used to acheve dscrete form. Here we use blnear transform. Blnear transform s made by aylor seres expanson of functon and usng tme shft property of sgnal wth s equal to a delay n z doman (Eq.3). Z{x[k n]}] = z n X[z], where (3) Z{x[k]} = X[z] Z s transform operator and n llustrates tme shftng. Blnear transformaton equaton s performed as follows: y(k) = y(k 1) + f(k) + f(k 1) s (4) Y[z](1 z 1 ) = s F[z](1 + z 1 ) (5) Y[z] F[z] = s z + 1 z 1 Eq.4 shows aylor expanson and Eq.5 shows transformed seres to Z doman. Fnally, Eq.6 s rearranged form of Eq.5 and shows the blnear formula. s s samplng me. Applyng blnear transform on PID controller by Eq. and Eq.6 results: U[z] E[z] = K s p + K (z + 1) (z 1) + K (z 1) d (7) z s (6) U[z] K p (z z) + K s (z + z) + K d E[z] = (z z + 1) s z z U[z] (K p + K s + K d E[z] = ) z + ( K p + k s s K d ) z + K d s s z z After multplyng numerator and denomnator of Eq.8 by z we have: (8) (9) U[z] (K p + K s + K d E[z] = ) + ( K p + k s s 1 z 1 K d s ) z 1 + K d s z And after some straght forward smplfcatons we reach the followng formula: (10) U[z] = z 1 U[z] + a E[z] + b z 1 E[z] + c z E[z] (11) U[k] = u[k 1] + a e[k] + b e[k 1] + c e[k ] (1) Eq.1 shows the tme doman dscrete PID controller.

4 Now we progress our work by smulatng the dscrete PID controller base on Eq.11. Fg. shows the desgned PID controller n Matlab s Smulnk envronment. he coeffcents are tuned practcally. hs model stll has some problems. We have to use an Untwndup to prevent ntegral term from saturaton. here are many ways to protect aganst wndup where the ntegrator part of PID controller saturates due to accumulaton nature of ntegraton. rackng s a smple method whch s llustrated n block dagram n Fg.3.a. Fg..Dsceret PID controller model Fg.3.b shows the Smulnk model of Untwndup. In Fg.3.a the system has an extra feedback path around the ntegrator. he sgnal e s s the dfference between the nomnal controller output v and the saturated control output u. he sgnal e s s fed to the nput of ntegrator through gan1/ t. he sgnal e s s zero when there s no saturaton. Under these crcumstances t wll not have any effect on the ntegrator. When the actuator saturates, the sgnal e s s dfferent from zero and t wll try to drve the ntegrator output to a value such that the sgnal v s close to the saturaton lmt. Fg.3.a. Untwndup presentaton Fg.3.b. Untwndup smulaton model he desgned PID controller s smulated n a planet wth H(s) = s +4s+100 as system s transfer functon n a closed loop and a perodc pulse wth f = 1/0Hz s appled to nput. Moreover predefned Smulnk PID model s ncluded for comparng results. Fg.4 shows the nput sgnal, desgned dscrete PID controller wthout Untwndup, desgned dscrete PID controller wth Untwndup and predefned Smulnk Model

5 respectvely from top to bottom. It s obvous that the PID wthout Untwndup couldn t answer to nput step pulse appled n 10sec. So far we have defned the essental concepts for dscrete PID controller. In next secton a bref revew on floatng pont representaton s explaned. Fg.4. top to bottom : nput sgnal, desgned dscrete PID controller wthout Untwndup, desgned dscrete PID controller wth Untwndup, predefned Smulnk PID block output 3. Floatng pont blocks Floatng-pont numbers are the favortes of software people, and the least favorte of hardware people. he reason for ths s because floatng pont takes up almost 3X the hardware of fxed-pont math. he advantage of floatng pont s that precson s always mantaned wth a wde dynamc range, where fxed pont numbers loose precson. Floatng-pont numbers are well defned by IEEE-754 (3 and 64 bt) and IEEE-854 (varable wdth) specfcatons. Floatng pont has been used n processors and IP for years and s a well-understood format. hs s a sgn magntude system, where the sgn s processed dfferently from the magntude. here are many concepts n floatng pont that make t dfferent from our common sgned and unsgned number notatons. hese come from the defnton of a floatng-pont number. Below s a 3-bt floatng-pont number format: S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF (13) +/- exp. Fracton Bascally, a floatng-pont number comprses a sgn bt (+ or ), a normalzed exponent, and a fracton. o convert ths number back nto an nteger, the followng equaton can be used: S ^ (exponent exponent_base) (1.0 + Fracton/fracton_base) (14) Where the exponent_base s ^((maxmum exponent/) 1), and Fracton_base s the maxmum possble fracton (unsgned) plus one. hus, for a 3-bt floatng-pont an example would be: (15) = +1 ^ (19 17) * ( / ) = +1 * 4.0 * 1.65 = 6.5

6 here are also denormal numbers, whch are numbers smaller than can be represented wth ths structure. he tag for a denormal number s that the exponent s 0. hs forces you to nvoke another formula where you drop the : (16) = -1 * ** -16 * ( / ) = -1 * **-16 * 0.5 = -**-17 Next, the constants that exst n the floatng-pont context are: = = -0 (whch = 0) = postve nfnty (17) = negatve nfnty In ths project we defne and use a smaller floatng pont wth just 11 fracton bts and 7 exponent bts. So countng the sgn bt, our floatng pont number has 0 bts. Floatng pont blocks are mplemented usng ISE9 Corgen whch easly produces embedded codes based on user defned adjustments. 4. Results HDL code of the desgned PID Model n secton s generated usng Matlab HDL Coder oolbox. On the other hand floatng pont arthmetc operands are programmed usng Corgen. Mergng these two codes results an overloaded PID controller wth floatng pont operatons. he whole code s smulated n ISE9 envronment and the results are shown n F.4.a., Fg.4.b and Fg.5. Fg.4.b. Part of the technologcal schematc (Zoomed) Fg.4.a. Full PID technologcal schematc

7 Fg.5. PID controller RL schematc Devce utlzaton summary could be seen n Fg.6. he target devce s xc3s500e FPGA from Xlnx Famly. Fg.6. Utlzed sources of FPGA Now as could be seen n Fg.4 we mplemented a full dgtal PID controller whch has 9 pns. pd_z and pd_u are nput and output ports respectvely. pd_kp, pd_k and pd_kd are proportonal, dervatve and ntegral coeffcents respectvely. hese coeffcents are adjusted by avalable on board devces lke pushbuttons and ther values could be seen on an LCD. Lnear ech LC64 Quad DAC and LC1407A-1 Dual A/D are used to convert nput analog sgnal to dgtal and vce versa. For addtonal nformaton about the perpherals on Spartan-3E board see [11]. All UCF locaton constrants for FPGA pn assgnment are adopted from embedded Kt. At last an 8 bt mcroprocessor called Pcoblaze [1] s programmed on FPGA and hundreds lne of embedded assembly code for ths mcroprocessor was wrtten and assembled usng KCPSM3 Assembler n order to control perpheral devces lke A/D and D/A converter, pushbuttons, LCD.etc. he Pcoblaze and Assembler source codes are avalable at Xlnx offcal webste for free. Smulated sgnals of these perpherals are shown n Fg.7. Fg.7. control sgnals generated by Pcoblaze for controllng perpheral devces 5. Conclusons

8 In ths paper we desgned and mplemented a dgtal PID controller wth floatng pont arthmetc. he advantage of the proposed method s ts capablty to do hgh precson arthmetc. he desgned controller also benefts from other ntrnsc performances of FPGA s lke ts hgh speed and low power. Obvously these floatng pont operands could be used to mplement other dgtal flters. Matlab HDL coder toolbox and Pcoblaze played a man role n PID mplementaton on xc3s500e FPGA. Future researches could be down to use the desgned PID to control a system lke servomotor. Another topc would be mplementng floatng pont wth hgher precson (3 or 64 bt). Acknowledgements he authors gratefully acknowledge the support and encouragements of Sr AmrReza Smnfar wthout whom ths project couldn t be completed. References [1] Gupta & Khare.(009) Effcent FPGA Desgn and Implementaton of Dgtal PID Controllers n Smulnk. Internatonal Journal of Recent rends n Engneerng [] Abdelat.(008).FPGA-Based PID Controller Implementaton.he Islamc Unversty of Gaza [3] XU & SHUANG. (009) FPGA Implementaton of a Best-precson Fxed-pont Dgtal PID Controlle. 009 Internatonal Conference on Measurng echnology and Mechatroncs Automaton [4] Sonol & Raju.(010). Implementaton of FPGA based PID Controller for DC Motor Speed Control System. Proceedngs of the World Congress on Engneerng and Computer Scence 010 Vol II [5] Behnam & Mansouryar.(011). Modelng and Smulaton of a DC Motor Control System wth Dgtal PID Controller and Encoder n FPGA Usng Xlnx System Generator. nd Internatonal Conference on Instrumentaton, Control and Automaton November 011, Bandung, Indonesa [6] Feng & Yan. (011). Implement of dgtal PID Controller Based on FPGA and the System Co-smulaton. Internatonal Conference on Instrumentaton, Measurement, Computer, Communcaton and Control [7] Ghosh & Bara (013) An FPGA Based Implementaton of a Flexble Dgtal PID Controller For a Moton Control System. 013 Internatonal Conference on Computer Communcaton and Informatcs (ICCCI -013), Jan , 013, Combatore, INDIA [8] Patel & sngh. (01). Desgn of FPGA-based All Dgtal PID Controller for Dynamc Systems. Internatonal Journal of Advanced Research n Electrcal, Electroncs and Instrumentaton Engneerng Vol. 1, Issue, August 01 [9] Dorf & Bshop. (010) Modern Control Systems. Prentce Hall [10] Oppenhem & Schafer (1999) Dscrete me sgnal processng. Prentce Hall [11] Dglent, Inc.(011) Spartan-3E FPGA Starter Kt Board User Gude. UG30 (v1.) [1] Dglent, Inc.(011) PcoBlaze 8-bt Embedded Mcrocontroller User Gude. UG19 June, 011