Design of an FPGA based TV-tuner test bench using MFIR structures

Transcription

1 ANNUAL JOURNAL OF ELECTRONICS, 3, ISSN Desgn of an FPGA based TV-tuner test bench usng MFIR structures Jean-Jacques Vandenbussche, Peter Lee and Joan Peuteman Abstract - The paper shows how Multplcatve Fnte Impulse Response (MFIR) flter structures can be used to mplement dgtal lnear phase low pass flters wth a very narrow transton band and a hgh stop band attenuaton n state of the art low-end FPGA technology. A dgtal Intermedate Frequency (IF) flter for a TV-tuner test bench s used as a reference desgn. The desgn procedure and the hardware requrements are presented. The paper concludes that the MFIR flter structures allow the desgn of demandng flters, whle tradtonal lnear phase FIR flters wth equvalent characterstcs would requre sgnfcantly more hardware resources. Keywords MFIR, FPGA, TV-tuner, IF flter I. INTRODUCTION In analog TV transmssons the sgnals at the front-end of a TV recever typcally consst of a desred sgnal accompaned by strong neghbor channels and nterferng sgnals [] []. The receved sgnal s down converted to a standardzed Intermedate Frequency (IF), but before demodulaton can take place, the neghbor channels must be strongly attenuated to exclude any nterference. In analog TV sets, hgh performance surface acoustc wave IF flters developed by specalzed supplers were used to acheve ths hgh attenuaton. Although hgh frequency Analog to Dgtal Convertors (ADC) exst, present state of the art dgtal TV-recevers stll down convert the receved sgnal n the analog doman. The resultng IF frequency s then sampled and ready for further dgtal sgnal processng [] [3]. Before dgtal demodulaton can take place, possble nterference from neghborng channels must be avoded usng hgh qualty band pass flterng. Ths band pass flterng s realzed n the dgtal doman, mplyng TV desgners can desgn the IF flter wthout the need for specalzed flter technology. Moreover, the frequency where demodulaton can take place s now programmable. Unfortunately, n cable TV recepton, the neghbor channel of a desred dgtal TV channel can be an analog TV channel wth an ampltude whch s 4 db hgher than the desred sgnal [4]. Ths puts a very strngent requrement on the dgtal IF flter. In addton, dgtal modulaton schemes (QAM, QPSK etc) carry the nformaton n the phase of the carrer, requrng lnear phase flters to avod nter symbol nterference (ISI). J-J. Vandenbussche s wth the Faculty of Industral Engneerng Scences, KULeuven, KULAB Brugge, Belgum, e- mal: jeanjacques.vandenbussche@kuleuven.be P. Lee s wth the School of Engneerng and Dgtal Arts, Unversty of Kent, Canterbury, Kent CT 7NT, UK, e-mal: P.Lee@kent.ac.uk J. Peuteman s wth the Faculty of Industral Engneerng Scences, KULeuven, KULAB Brugge, Belgum, e-mal: joan.peuteman@kuleuven.be In state of the art TV recevers, a low IF of 4 MHz s chosen resultng n an IF flter wth a low pass characterstc and a requred attenuaton of at least 75 db mmedately outsde the pass band [4]. In a TV desgn lab a hgh performance reference IF low pass flter s used n a test jg to allow benchmarkng of tuner samples from dfferent supplers. The mnmum requrements for ths IF flter are: lnear phase low pass flter 8 db stop band attenuaton Samplng frequency f s = 5 MHz transton band between.8 f s / and.3 f s / A flter wth these specfcatons has been realzed n an FPGA usng the Multplcatve Fnte Impulse Response (MFIR) approxmaton [5] [6] and s presented n ths paper. Secton II ntroduces the prncple of the MFIR flter structure. Secton III presents the actual mplementaton and hardware requrements of the flter. The paper ends wth some conclusons. II. THE MFIR FILTER STRUCTURE MFIR flters are based on the basc expresson [7] = = x = + x for x <. () The nfnte sum n () can be approxmated by a fnte sum [5] P P = = x = + x for x <. () For the case where H(z) s the transfer functon of a stable real pole ( λ < ) IIR flter, the applcaton of () yelds H ( z) = = ( λ z ) λ z = (3) P P P H ( z) ( λ z ) ( λz = + ) = M ( z) = M ( z). = = = Where M(z) ndcates the entre MFIR flter structure and M (z) s called a stage of the MFIR structure. It s clear that for a good approxmaton of the pole flter, a suffcently large number of stages must be chosen. Analyss has shown [6] that even for poles extremely close to the unt crcle ( λ =.99 for example) ten stages are suffcent to approxmate the magntude response of the approxmated pole flter wth a maxmum devaton of just. db. The frst major advantage of the MFIR structure s the ablty to replace a possble unstable IIR flter by a cascade of always stable FIR flter structures. An IIR flter wth a transfer functon H(z) havng a conjugate pole par λ and λ * where λ = re +jθ, λ * = re -jθ and r <, can be approxmated wth a cascade MFIR structure gven by [5]

2 ANNUAL JOURNAL OF ELECTRONICS, 3 H z = * ( λz )( λ z ) P * ( λz ) ( λ z ) P + + = = + P ( rz ) ( θ ) ( rz ) M ( z) M ( z) P + cos + = =. = = It s clear that (4) only apples when λz - and λ * z - are <. A further advantage of the MFIR approxmaton s the ablty to approxmate the magntude behavor of a pole flter (wth a pole nsde the unt crcle) whle obtanng a lnear phase. For such an mplementaton, the followng desgn procedure was proposed n [5]. If the desred magntude response s gven by H(z) :. Desgn an ellptc IIR flter havng stable pole (pars) and realzng H(z) /.. Approxmate all poles of ths IIR flter usng (3) and/ or (4). 3. Cascade to every zero of the obtaned MFIR structure(s) the recprocal zero wth respect to the unt crcle. Note that ths procedure must be followed for every pole(par). 4. The resultng structure must be cascaded wth the zeros of the ellptc IIR flter (that realzes H(z) / ) each doubled. Consequently, the lnear phase approxmaton of an IIR flter H(z) wth a real stable pole at λ, can be desgned by determnng the real (stable) pole λ realzng H (z) = H(z) /. The resultng lnear phase flter H ( z ) can then be approxmated by P M ( z) + ( λ ' z ) + = λ ' z P + M ( z) + ( λ ') + z + z. = ( λ ') For a H(z) realzng an IIR flter wth a complex conjugate pole par λ = re ±jθ, the (stable) poles λ = r e ±jθ of H (z) wth H (z) = H(z) / can be determned. The MFIR approxmaton yeldng the lnear phase flter M ( z) s then gven by M z P = ( r z ) ( θ ) ( r z ) + ' cos ' ' z cos( θ ') + z r ' r ' + ( (( r ') + ( r ') ) cos( θ ')) z.. M ( z) + (( r ) + ( θ ) + ( r ) ) z 3. + ( (( r ') + ( r ') ) cos( θ ')) z + 4. z When (5) and (6) are compared wth (3) and (4) respectvely, t s clear that the lnear phase approxmatons do not requre more multplers than ther non-lnear phase (4) (5) P. ' 4cos ' '. (6) = counterparts. However, the lnear phase approxmatons requre twce the number of delay elements when compared wth ther non-lnear phase counterparts. The desgn procedure s farly smple and straghtforward. Once the requrements of H(z) are fxed, Matlab s Flter Desgn and Analyss tool (FDA-tool) can be used to determne the poles and zeroes that realze an ellptc flter wth a magntude response, whch approxmates H(z) /. For every complex conjugate pole par or real pole, the MFIR lnear phase approxmatons (5) or (6) can be used. The zeros must be doubled and can be mplemented usng standard FIR flter structures. A Matlab m-fle s used to determne the fxed-pont multpler coeffcents of the flters dependng on the chosen scalng method, the flter sequence and the requred number of bts for the quantzaton of the multpler coeffcents. III. THE DESIGN OF THE IF FILTER In ths secton, the desgn procedure of the IF flter wth the specfcatons gven n the ntroducton s dscussed. A. Determnaton of H(z) / As descrbed n II the poles and zeroes of an ellptc flter approxmatng H(z) / are determned usng Matlab s FDA-tool. Ths yelds for the present test case flter the poles and zeros shown n TABLE and FIGURE. TABLE : POLES AND ZEROS OF THE ELLIPTIC IIR FILTER REALIZING H(Z) / Poles λ Zeros.63 +/-.77j.568 +/-.83j.575 +/-.76j.54 +/-.858j.55 +/-.548j.9 +/-.954j.465 +/-.9j /-.835j Each complex conjugate zero par s combned wth the closest complex conjugate pole par as s normally done n bquad desgns [8] [9]. In TABLE, these combnatons are gven on the same row. Imagnary Part Real Part FIGURE. Z-PLANE OF THE ELLIPTIC IIR FILTER REALIZING H(Z) / Every row n TABLE s mplemented as a cascade of an FIR flter realzng the zero par (doubled) and an MFIR

3 ANNUAL JOURNAL OF ELECTRONICS, 3 structure approxmatng the squared magntude response of the pole par, as shown n FIGURE. The FIR-MFIR cascade corresponds wth the frst row of TABLE, FIR- MFIR wth the second row etc. FIR MFIR FIR MFIR FIGURE. GENERAL STRUCTURE OF THE LINEAR PHASE LOW-PASS FILTER B. Realzaton of the flter stages The transfer functon of the doubled zero pars on the unt crcle s gven by ( θ ) Z z = cos z + z, (7) or equvalently Z z 4 = a + z 3 + b z + z + cz, (8) wth a =, b = -4cosθ and c = ( + 4cos θ). The squared magntude response of the complex conjugate pole pars s approxmated usng (6). A smplfed verson of (6) s gven by P ( ) = M z a z b z z c z. (9) =... Comparng (8) wth (9), t s clear that the FIR flter realzng the double zeros uses the same archtecture as the MFIR stages. As can be seen n Table, the desgn presented n ths paper, requres four MFIR flters approxmatng the squared magntude response of the four complex conjugate pole pars wth lnear phase characterstc and four FIR flters realzng the four (doubled) complex conjugate zero pars. The desgn of the FIR-MFIR combnaton wll now be dscussed n detal. In the present desgn, nfnty bound scalng [8] [9] s used as a scalng method. Flter FIR creates the double zero par.568 +/-.83j. Usng (8), the transfer functon of ths flter s gven by 4 3 Z z = + z.736 z + z z. () The scalng factor for nfnty bound scalng s determned n Matlab and equals.638. The coeffcents are mplemented usng 6-bt plus a sgn bt, allowng the use of standard IP multplers. Consequently, the coeffcents n () are multpled wth the scalng factor and wth 6 (6 bts plus sgn bt fxed-pont converson) resultng n the followng fxed-pont multpler values for FIR : TABLE : MULTIPLIER VALUES OF THE FIR FILTER REALIZING THE DOUBLED ZERO PAIR.568 +/-.83j S a S b S c S a, S b and S c are respectvely, the scaled and converted to fxed-pont factors, and of (). The coeffcents of the MFIR flter approxmatng the squared magntude response of the conjugate pole par.63 +/-.77j wth P = 9 stages are calculated n Matlab usng (6) and are gven n TABLE 3. The scalng factors (for nfnty bound scalng) are determned n Matlab and are gven n TABLE 4. TABLE 3: COEFFICIENTS OF THE UN-SCALED MFIR FILTER APPROXIMATING THE SQUARED MAGNITUDE RESPONSE OF THE POLE PAIR.63 +/-.77j stage number a b c The coeffcents are mplemented usng 6-bt plus a sgn bt, mplyng the values n TABLE 3 are multpled wth the respectve values of Table 4 and wth 6 (6 bts plus sgn bt fxed-pont converson) resultng n the fxed-pont multpler values of TABLE 5. S a, S b and S c are the scaled and to fxed pont converted a, b and c factors of (9). TABLE 4: SCALING FACTORS OF THE MFIR FILTER APPROXIMATING THE SQUARED MAGNITUDE RESPONSE OF THE POLE PAIR.63 +/-.77j stage number Scalng factor e-5 TABLE 5: FIXED-POINT MULTIPLIER VALUES OF THE MFIR FILTER APPROXIMATING THE SQUARED MAGNITUDE RESPONSE OF THE POLE PAIR.63 +/-.77j stage S a S b S c number In case a stage has a multpler value that does not ft n the 7 bts that are foreseen for the hardware multplers n the actual VHDL mplementatons, all multplers of that stage are dvded by powers of two untl the multplers ft n the bt wdth. The dvson by the power of two s undone n the output sgnal of the stage by shftng the result.

4 ANNUAL JOURNAL OF ELECTRONICS, 3 The above-dscussed desgn method s also appled on the other pole and zero pars gven n TABLE. Fgures 3 to 6 show the ampltude and phase response of the respectve FIR-MFIR combnatons. FIGURE 7 shows the ampltude and phase response of the entre structure. Notce the very narrow transton band of the low pass flter and the hgh rejecton band attenuaton. C. The hardware utlzaton For the mplementaton of the lnear phase low pass flter presented above, the sgnal nput and output bt wdth equals 6 bt. The mplementaton n a Xlnx Spartan3A- DSP : XC3SD34A, n speed grade -4 requres 37 slces (9%), 366 four-nput LUTs (6%), 84 multplers (66%) and has a maxmum clock frequency of.8 MHz. 37 slces mght seem a lot for the mplementaton of a flter, but the lnear phase flter has an mpressve ampltude response realzng a very good suppresson of the adverse effects (on the ISI) of the neghbor channel. The number of multplers s substantal. However, a tradtonal equvalent equrpple lnear phase FIR mplementaton, determned usng Matlab s FDA-tool, requres 36 multplers (7nd order) whch s 6% more and does not ft n the Spartan 3A-DSP. Implyng there s, for ths applcaton, when usng the consdered hardware, no alternatve than usng the MFIR flter structures. A Xlnx ISE.5 generated Devce Utlzaton Summary s gven n FIGURE 8. Gan [db] Gan [db] Approxmated Ampltude response Approxmated Phase response FIGURE 4: AMPLITUDE AND PHASE RESPONSE OF THE CASCADE OF FIR AND MFIR Approxmated Ampltude response Approxmated Phase response Approxmated Ampltude response Gan [db] Approxmated Phase response FIGURE 5: AMPLITUDE AND PHASE RESPONSE OF THE CASCADE OF FIR3 AND MFIR FIGURE 3: AMPLITUDE AND PHASE RESPONSE OF THE CASCADE OF FIR AND MFIR Gan [db] Approxmated Ampltude response Approxmated Phase response FIGURE 6: AMPLITUDE AND PHASE RESPONSE OF THE CASCADE OF FIR4 AND MFIR4

5 ANNUAL JOURNAL OF ELECTRONICS, 3 Gan [db] Ampltude response Phase response followed to desgn ths lnear phase flter wth a very narrow transton band and hgh stop band attenuaton. Although the flter has demandng specfcatons, the hardware utlzaton s very acceptable. The small FPGA footprnt of the flter, combned wth the hgh maxmum clock frequency and throughput, prove that the MFIR structure s very well suted for the mplementaton of demandng, possbly lnear phase, dgtal flters n FPGA technology FIGURE 7: AMPLITUDE AND PHASE RESPONSE OF THE LINEAR PHASE MFIR FILTER STRUCTURE Devce Utlzaton Summary Logc Utlzaton Used Avalable Utlzaton Number of Slce Flp Flops ,744 % Number of occuped Slces,37 3,87 9% Total Number of 4 nput LUTs 3,66 47,744 6% Number used as logc Number used as Shft regsters 3,64 Number of bonded IOBs % Number of BUFGMUXs 4 4% Number of DSP48As % Average Fanout of Non-Clock Nets.44 FIGURE 8: XILINX ISE.5 DEVICE UTILIZATION SUMMARY FOR THE IMPLEMENTATION OF THE ENTIRE LINEAR PHASE FILTER CONSISTING OF 4 MFIR FILTERS AND 4 FIR FILTERS IV. CONCLUSION In ths paper, the mplementaton of a hgh performance lnear phase low pass flter n an FPGA has been shown. A very straghtforward and tradtonal desgn procedure was REFERENCES [] M. Parker, Dgtal Sgnal Processng, Newnes,, Ch., pp. 8-9 [] F. Harrs, C. Dck, M. Rce, Dgtal Recevers and Transmtters Usng Polyphase Flter Banks for Wreless Communcatons, IEEE Trans. On Mcrowave Theory and Technques, Vol 5, Aprl 3, pp [3] S85 Hybrd DVB-T/C and Analog TV Recever, datasheet, Slcon Laboratores Inc., Austn, TX,. [4] B. Pandta, Oversamplng A/D Converters wth Improved Sgnal Transfer Functons, Analog Crcuts and Sgnal Processng, Sprnger,, ch Low IF complex ADC-based DTV recever, pp. -3 [5] A.T. Fam, ''MFIR Flters: Propertes and Applcatons, IEEE Transactons on Acoustcs, Speech and Sgnal Processng, vol. 9 no. 6, 98, pp [6] JJ Vandenbussche, P. Lee and J. Peuteman Analyss of tme and frequency doman performance of MFIR flters, Proceedngs of the Internatonal Conference on Embedded Systems and Applcatons, Las Vegas, July 8, pp [7] H. Rademacher, Topcs n Analytc Number Theory, Sprnger-Verlag, 973, chapter, pp. 3-4 [8] L. B. Jackson, Dgtal Flters and Sgnal Processng, Kluwer Academc Publshers, 996. [9] L.B. Jackson, On the Interacton of Roundoff Nose and Dynamc Range n Dgtal Flters, Bell Systems Techncal Journal, vol. 49, Feb. 97, pp