Fully Redundant Decimal Arithmetic

Transcription

1 9 9th IEEE Internatonal Symposum on Computer Arthmetc Fully Redundant Decmal Arthmetc Saed Gorgn and Ghassem Jaberpur Dept. of Electrcal & Computer Engr., Shahd Behesht Unv. and School of Computer Scence, nsttute for research n fundamental scences (IPM), Tehran, Iran Gorgn@sbu.ac.r, Jaberpur@sbu.ac.r Abstract Hardware mplementaton of all the basc radx- arthmetc operatons evolvng as a new trend n the desgn and mplementaton of general purpose dgtal processors. Redundant representaton of partal products and remanders common n the multplcaton and dvson hardware algorthms, respectvely. Carry-free mplementaton of the more frequent add/subtract operatons, wth the byproduct of enhancng the speed of multplcaton and dvson, s possble wth redundant number representaton. However, converson of redundant results to conventonal representatons entals slow carry propagaton that can be avoded f the results are kept n redundant format for later use as operands of other arthmetc operatons. Gven that redundant decmal representatons, contrary to redundant bnary, do not necessarly requre extra storage, we are motvated to develop a framework for fully redundant decmal arthmetc, where all operands and results belong to the same redundant decmal number system and can be stored and later used as operands of further decmal operatons. In ths paper, we present a new faster decmal sgned dgt add/sub unt and show how t can be effcently used n the desgn of decmal multplers and dvders, where all operands and results are represented wth the same redundant dgt set [ 7, 7].. Introducton Decmal computer arthmetc and the supportng hardware unts are once agan n the forefront of commercal, fnancal, scentfc, and nternet-based applcatons []. The current trend s mrrored, n the ndustry, by commercalzaton of dgtal processors wth embedded decmal arthmetc unts (e.g., IBM z9 eserver [], power6 [] and z [4]), and n the lterature, va the state of the art parallel decmal multplers (e.g., [5] and [6]), dvders (e.g., [7], [8] and [9]), functon evaluaton and CORDIC [] hardware. In both decmal and bnary arthmetc, partal productn multplers and partal remandern dvders are often represented va a redundant number system (e.g., Bnary sgned dgt [], decmal carrysave [5], double-decmal [6], and mnmally redundant decmal [9]). Such use of redundant dgt sets, where the number of dgts suffcently more than the radx, allows for carry-free addton and subtracton as the basc operatons that buld-up the product and remander, respectvely. In the aforementoned works on decmal multplers and dvders, nputs and outputs are nonredundant decmal numbers. However, a redundant representaton s used for the ntermedate partal products or remanders. The ntermedate addtons and subtractons are sem-redundant operatonn that only one of the operands as well as the result s redundant. In contrast there are fullyredundant add/subtract schemes, where both operands and certanly the result are represented va redundant decmal dgt sets (e.g., [], [] and [4]). Fully redundant decmal addton s also used wthn a sequental decmal multpler [5], where partal products are represented n Svoboda s decmal sgned dgt encodng []. However, we have not encountered any fully redundant radx- multpler or dvder n the lterature. In a comprehensve study on the frequency of arthmetc operatons of a general computaton [6], t has been shown that add/subtract operatons occur more frequently than multplcaton and dvson. Therefore, carry-free addton/subtracton can have a great mpact on the overall executon tme. However, there are usually two problems: Problem (Storage of redundant results): The redundant result of an addton/subtracton s not necessarly used mmedately as the operand of a subsequent operaton. Therefore, t should be approprately stored for later use. But, redundant results often requre wder storage words or regsters due to extra redundancy bts wthn a dgt /9 $5. 9 IEEE DOI.9/ARITH.9. 45

2 Ths may not be requred when the radx of the number system s not a power of two. For example, n radx- arthmetc, at least four bts are requred for representaton of a -valued nonredundant decmal dgt. Therefore, there are possbly sx extra 4-bt codes avalable to be assgned to extra dgts of a redundant decmal dgt set. For nstance, the dgt set [ 7, 7] has been used n the desgn of a fully redundant decmal adder [] and for representaton of quotent dgtn the desgn of a nonredundant radx- dvder [8], where each dgt s represented as a 4-bt two s complement number. The overloaded decmal dgt set [, 5] used n [7] represents another example of a redundant decmal encodng wth no extra redundancy bt. There are however, redundant decmal dgt sets that use more than four bts per dgt (e.g., 6 btn [] and 8 btn [4]). Problem (Intermxed operatons): Other operatons such as multplcaton and dvson may be ntermxed wth addtons and subtractons. Therefore, use of conventonal multplers and dvders that requre nonredundant operands enforces the converson of redundant results, of add/subtract operatons, to conventonal nonredundant format. The converson may requre word wde carry propagaton that may jeopardze the speed ganed va carry-free add/subtract operatons. Ths problem can be avoded f we keep the redundant resultntact when they are needed as operands of other operatons such as multplcaton or dvson; hence the necessty to desgn fully redundant multplers and dvders. In ths paper, a prelmnary dscusson on decmal addton s offered n Secton. We propose fully redundant add and subtract schemes for a redundant decmal number system wth dgtn [ 7, 7], n Sectons and 4, respectvely. To further strengthen the framework for fully redundant decmal arthmetc, wthout tryng to be comprehensve due to space lmt, we show n Sectons 5 and 6 that how the proposed carry-free decmal adder and subtractor can serve as buldng blocks for fully redundant decmal multplers and dvders, respectvely. Secton 7 s dedcated to comparsons wth the prevous fully redundant adders, where fve dfferent adders are syntheszed based on TSMC. μm standard CMOS technology. Also, the proposed multpler and dvder are compared wth the best prevous nonredundant desgns. Fnally, Secton 8 contans our concludng remarks.. Prelmnares.. Nonredundant decmal addton Straghtforward mplementaton of decmal addton/subtracton on bnary dgtal computers based on decmal full adders (D) that compute the Eqn. set, where, s, x and y are decmal dgts, c n and c out are decmal carres, and A m stands for A modulo m., () Desgn of the D, based on a standard 4-bt bnary adder, entals the tasks of over-9 detecton and +6-correcton. Eqn. set descrbes the operaton of a 4-bt adder, where w 4 s the hexadecmal carry-out and w s the 4-bt sum., () Eqn. set llustrates the aforementoned tasks that arse n the straghtforward computaton of c out and s from p and w, respectvely., f 9 f 9,,, f 6, f () Several decmal addton algorthms and ther hardware realzatons have been offered n the lterature (e.g., the classcal work n [8] and the recent one n [9]). Gven that n s complement arthmetc the addton crcutrs used for subtracton, where the overhead s only one XOR gate per bt, the obvous challenge s to also unfy, wth mnmal overhead, the crcutry for decmal addton and subtracton... Redundant decmal addton Let,, and all n [ α, β] (e.g., α = β = 7) denote the dgts of the operands and result n poston (.e., weghted ), such that, where [ α, β], ruled by Eqn. set 4, s the redundant decmal dgt set, the poston sum, and (smlarly t ) s computed an Eqn. 5, wth, f α δ, f α α + β 5, α, β, α, β (4), f δ, f, f α α β β (5) 46

3 The restrctonn (4) guarantee that α, β (see [] for a general proof) and only four bts are enough for encodng the dgt set [ α, β]. The straghtforward mplementaton of Eqn. 5, as more or less followed n [] for the balanced dgt sets (.e., α = β), entals the followng four steps: t + z u z V t I. Compute. II. Extract transfer t + va comparson of p wth α. III. Compute the nterm sum dgt. IV. Form the fnal sum dgt t + T + t T All the above steps normally experence worst case carry propagaton across the 4-bt dgts of the operands. More effcent mplementaton, however, may be envsaged by notng that the nterm sum dgt w and transfer dgt t + can be expressed and mplemented n hardware drectly as functons of and. But, ths calls for the uneasy task of desgnng 8- nput combnatonal logc, where the hardware cost may not be apprecated. We propose a compromse desgn wth less complex combnatonal logc and shorter carry propagaton chans.. The mproved decmal SD addton We assume a redundant decmal number system wth decmal sgned dgt set [ 7, 7] and call the dgt set as decmal septa sgned dgt (DSSD) set, to reflect the boundary values α = β = 7. Followng [], we represent each DSSD as a 4-bt two s complement number. Step I of the decmal addton scheme, outlned n Secton, can be mplemented at no cost by representng p as a two s complement carry-save (TCCS) number []. Thllustrated n Fg., where superscrpts (subscrpts) ndcate bt (dgt) weghted- (-) postons. Also, whte (black) crcles wth uppercase (lowercase) varables represent negabts (posbts). Fgure. The TCCS poston sum p. Let, where represents the arthmetc value of the bt collecton, s composed of the three most sgnfcant bts of one operand and two of the other and represents the three remanng bts, allustrated n Fg.. Then,, 4 and { 6, 4,,,, 8, }. We further decompose, to the decmal transfer,, and the resdue 6,4,,, assocated wth the bt collecton. Therefore, the range of the nterm sum s 6, 6 6,, 4, whch leads to 7, 7. Fgure. Decomposton of u to transfer t + and z Note that n the alternatve balanced decomposton, wth the am of extractng t + from only four bts (.e.,,, and ), a postve resdue nevtable. On the other hand, the arthmetc value of the remanng bts falls wthn [, 6]. Therefore there wll be cases, where no room s left for the comng transfer t. Fg. llustrates the addton process that s composed of the followng overlappng step to v, where Eqn. sets 6 to are derved, va straghtforward truth tables.. Decomposton of u ruled by u = t + + z (see Fg. ), where the consttuent bts of t + and z are derved an Eqn. set 6., q S z Q C,,,. (6) V t T Fgure. The complete addton process. 47

4 . Transformaton of to (n parallel wth Step ), descrbed by Eqn. set 7.,, (7). -bt addton leadng to carry bt and sum bts and (Eqn. set 8).,,,,,,, (8) v. -bt addton n poston (Eqn. set 9) leadng to (n parallel wth ).,,, (9) v. Fnal -bt addton leadng to sum bts and, as descrbed by Eqn. set.,,, () Note that the functon carrn Eqn. sets 8 to s the carry functon assocated to standard full adders and half adders wth possblnverted nputs and outputs []. Moreover, snce s a negabt and no carrs to be generated out of poston, the sum logc for s smplfed to a NOR gate. Ths further llustrated n Fg. 4-a, where the crtcal delay path goes through nne logc levels, ndeed a consderable mprovement over the prevous 8 logc level desgn n []. A more relable Logcal Effort [] delay analyss leads to.56 FO4 for the latter and 7.8 FO4 for our adder. Also, n Secton 7, we report the results of syntheszng both crcuts by TSMC. μm technology usng Synopss Desgn Compler. 4. DSSD subtractor Snce each DSSD s encoded as a 4-bt two s complement number, we smplnvert all the bts of the subtrahend and perform an enforced carry addton per DSSD. The crcutrs the same as the adder of the prevous secton except for the logc that derves, and (see Eqn. set 7', below) correspondng to, and (see Eqn. set 7, above) and of course two nverters for the two most sgnfcant bts of the subtrahend.,, (7') The gate level analyss of the subtractor just descrbed shows that the latencs equal to that of nne logc levels wth -nput gates, whch s no more than that of the adder descrbed n the prevous secton. Moreover, the FO4 delas 7.8 (.e., the same as that of the adder of Fg. 4-a). The adder (subtractor) by tself can be used as the buldng block for partal product reducton (partal remander computaton) n the DSSD multpler (dvder) to be brefly explaned n Secton 5 (6). However, n a general purpose decmal arthmetc hardware unt, t may be desred to perform subtracton usng the adder crcutry. To realze such a unfed add/sub unt we can use a sub sgnal to nvert all the bts of the subtrahend va XOR gates, and also to select between the outputs of the crcutmplementng the Eqn. sets 7 and 7'. It turns out that only the XOR gates le wthn the crtcal delay path, thus addng two logc levels to the overall latency, whch amounts to eleven logc levels and 9.5 FO4. Nevertheless, Eqn. sets 7 and 7' and ther selector can be replaced by Eqn. set, to save hardware, as depcted n Fg. 4-b. Note that the boxes wth same degree of shadng n Fgs. 4-a and 4-b are logcally dentcal.,, () t + T + t + T + q S S z Q 4-level logc for Eqn. set 6 q z Q HA C 4-level logc for Eqn. set 6 HA C (a) DSSD adder Sub v -level logc for Eqn. set 7 V 4-level logc for Eqn. set v V (b) DSSD add/subtract logc Fgure 4. The th dgt slce of the DSSD adder-only and add/sub unt. t T t T 48

5 5. Fully redundant DSSD multpler Multplcaton s normally a three phase process; namely partal product generaton (PPG), partal product reducton (PPR) and fnal product computaton. The ntermedate results wthn the PPR phase are often represented n a redundant format (e.g., bnary carry-save [4], bnary sgned dgt [], or decmal carry-save [5]) that enables carry-free addton. The conventonal multplcaton technques assume nonredundant operands and result. Therefore, the fnal redundant partal product needs to be converted to the nonredundant representaton that s delneated for the fnal product. It s well known that such converson s essentally a slow carry propagatng operaton. However, n fully redundant multplers, one may use the same redundant format for nput operands, partal products and the fnal product. Consequently, the fnal product s readly avalable as the output of the PPR phase. In ths secton, we descrbe the PPG phase of a redundant dgt decmal multpler wth DSSD operands. Although the explanatons are somewhat lengthy, the hardware realzaton s smple. The second phase would smply make multple use of the DSSD adder of Secton, and drectly produces the fnal product wth DSSD dgts; hence obvatng the need for fnal carry-propagatng phase. 5.. PPG for DSSD operands Decmal partal products are commonly expressed as unevaluated sum of two decmal numbers. For example, n conventonal decmal multplers (e.g., [5]), the requred multples are expressed as unevaluated sum of two easy multples; that s (,,, 4, 5) multplcand X. The easy multples are precomputed, carry-freely, as sngle decmal numbers. As another example, [5 and 6] precompute (±, ±, 5, ) X, and more recently, [6] precomputes (,,, 5, 8, 9) X. To reduce the selecton cost, t s naturally desrable to restrct the number of precomputed carryfree multples to as few as possble. For the DSSD multpler the set of precomputed multples Π = {±X, ±X, ±4X} s a mnmum set, where the rest of the requred multples can be expressed as two DSSD numbers as follows:, 5 4, 6, 7 4 () We provde a carry-free logc to precompute the Π multples as two restrcted DSSD numbers and add them by a smple 4-level logc that produces sngle DSSD multples. It can be shown that the same procedure, f appled to other mnmum set of multples (e.g., ±X, ±X, ±5X), s not as effcent. Fg. 5 depcts the requred archtecture, where and are the two dgts of the precomputed (,, 4) and. The -bts of can be computed va a smple -level logc. The multplexers lead the approprate hgh or low dgt or to the fnal selector (expanded n Fg. 6) that s controlled by a decoder ruled by Eqn. set, where,,,,,, and,,. μ h μ l h l Mux 4 4, j l, j h, j l, j h μ h μ l h l 4 h Mux 4μ 4 l Selector 4μ 4 h 4 l Mux 5 σ ς j Decoder ν j Fgure 5. A dgt-slce for of PPG network.,,,, () ± 4μ μ ± ±μ s ±4 s ± s ± s ± s ± h, l, j, j h, l, j, j Fgure 6. The logc for the selector of Fgure 5. Table I shows the complete and values, where [, ] and [ 5, 5]. Table II contans logcal equatons for the three bts of and the four bts of n terms of the bts of. These equatons have been easly derved va straghtforward -bt truth tables. To see the carry-free nature of the computaton of sngle DSSD multples, let be the k- dgt multplcand and denote the k+-dgt j th partal product, where,,,,,, wth, and,, defned as:,,,,,,, ( k ),,,,,, (4) It can be easly explored from Table I that [ 7, 7] leadng to,,, [ 7, 7]. 49

6 Therefore, computaton of the two components of the DSSD dgts of the j th partal product (.e.,, and, n Eqn. set 4) does not produce any carry. Ths also shown by Fg. 7 and Eqn. set 5, where l, h and p dgts are represented by L l l l, H h h and P p p p, respectvely and s the carrnto poston.,,, (5) L l H l h l h P p p p Fgure 7. Addton of the Low and hgh components. The latency of the descrbed -logc-level PPG s evaluated as 9. FO4 va Logcal effort analyss []. 6. Fully redundant DSSD dvder In ths secton we brefly examne the mpact of fully redundant operands and results on the state of the art decmal hardware dvson algorthms, whether multplcatve or subtractve, where Z, D, Q and R denote dvdend, dvsor, quotent and remander, respectvely. 6.. DSSD multplcatve dvson The recprocal of the dvsor /D s produced ether va convergng multplcatons, an Eqn. 6, or approxmaton of /D wth the help of a table lookup operaton (Eqn. 7). (6) The recurrence Eqn. 6 s specfcally sutable for bnary dvson, where D and R j are fractons, assumes an ntal approxmaton of /D, and each teraton s composed of two multplcatons before and after a two s complement operaton [7]. The other multplcatve method [8] s based on Eqn. (7), where agan D s a normalzed fracton and D h and D l are ts most- and least-sgnfcant halves, respectvely. s smply obtaned by algnng D l on the rght of D h ; thus no subtracton s actually requred. can be looked up n a table, n parallel wth the multplcaton. Fnally, a multplcaton by derves the quotent. A smlar method usng approxmaton based on Taylor seres expanson s offered n [9], where the desgner decdes on where to break D nto two parts. (7) We beleve that Eqn. 7, s more sutable for DSSD dvson than Eqn. 6. The reason s that no decmal subtracton s needed here. The negaton requred for D l can be performed by 4-bt two s complementaton of all the DSSD dgtn parallel wth a latency of two logc levels. The multpler desgn of the prevous secton can be used for the requred two multplcatons. Table II: Logcal equatons for the bts of and. Poston Table I. Generaton of Π multples as hgh and low restrcted DSSD numbers

7 6.. DSSD subtractve dvson The subtractve method s typcally based on Eqn. 8, where W = Z < D, s the partal remander after j teratons, Z (D =.d d d m ) s normally a m (m) dgt fracton wth d, and s the (j+) th dgt of the fractonal quotent Q =.q q q m. (8) A radx- subtractve (or dgt recurrence) dvson method has been recently proposed n [8] for nonredundant decmal operands, where quotent dgts are prmarly produced as [ 7, 7] dgts (.e., DSSD) and converted to conventonal decmal, on the fly. In the fully redundant DSSD dvson that we propose, the dvdend, dvsor, quotent and the partal remanders are all represented as DSSD numbers. We can mplement Eqn. 8 usng the multpler of the prevous secton, for precomputaton of DSSD multples of the dvsor (.e., { 7D, 6D, 6D, 7D}), and the subtractor of Secton 4, for producng the partal remanders. We adopt the technques descrbed n [8], for the DSSD representaton, to obtan the comparson multples and new quotent dgts. For the former a look up table can be set up based on the three most sgnfcant dgts (MSD) of D and for the latter the three MSDs of partal remanders are kept as a bnary number (the rest n orgnal DSSD form) to allow the use of very fast bnary carry-save addern dervng the three MSDs of the new partal remander. Moreover, t can be shown that as the case n [8] the three MSDs of the dfference of the partal remander and a comparson multple are suffcent for quotent dgt selecton. The only extra unts that are to be specfcally desgned for our fully redundant dvson scheme are the DSSDto/from-bnary converter of the three MSDs and the sgn detector for the three MSDs of the comparson dfferences. 7. Comparson It was noted at the end of Secton that the proposed DSSD adder s twce as fast, n terms of logc levels, as compared to the best prevous work n []. Ths rough comparson was supported by evaluaton of FO4 delays of the two crcuts wth 7.8 FO4 for the proposed desgn versus.56 FO4 of the prevous one. To assess ths advantage n a more realstc manner, and also for area comparson, we produced VHDL code for all the redundant decmal adders that we have encountered n the lterature and syntheszed them usng the Synopss Desgn Compler. The target lbrary was based on TSMC. μm standard CMOS technology. The results appear n Table III, where the proposed desgn outperforms all the prevous ones. Table III. delay/area for SD decmal adders Adder; ref. Dgt Delay Area Rato set (ns) ( ) Rato Svoboda;[] [ 6, 6] RBCD; [] [ 7, 7] DSD; [4] [ 9, 9] DSD; [] [ 9, 9] DSSD; new [ 7, 7].87 6 We have not encountered any fully redundant decmal multpler or dvder n the lterature to serve as a comparson bass wth our desgns. However, the fastest reported nonredundant decmal parallel multpler s due to [6] wth 65 FO4 delay, whle the latency of the proposed fully redundant one s evaluated to be 48. FO4. As for the fully redundant DSSD dvder, proposed n Secton 6, we beleve that the latency wll not be more than the nonredundant radx- dvder of [8]. The reason, n bref, s that our desgn bascally mmcs the nonredundant one, where the qute smlar quotent dgt selecton of both desgnn the crtcal delay path of each recurrence. 8. Conclusons We have proposed a framework for fully redundant decmal arthmetc based on decmal septa sgned dgt (DSSD) set [ 7, 7], where the operands and results of the four basc operatons are represented as DSSD numbers. Ths allows for ultra fast carry-free addton and subtracton of DSSD numbers, whch can lead to consderable speed up of conventonal general computatons, where the frequency of add/subtract operatons more than that of multplcaton and dvson. To avod converson of DSSD result to conventonal decmal, except at the end of computaton, we proposed fully redundant DSSD multplers and dvders to complete the requred framework. Contrary to bnary or hgh power-of-two radx redundant arthmetc, no extra storage s requred for representaton of DSSD numbern comparson wth conventonal nonredundant decmal arthmetc. Therefore, a whole computaton can be conducted effcently, wth the hgh speed ganed due to hghly frequent carry-free addtons/subtractons, wthn the proposed DSSD framework up to the pont of reportng a result to an output devce. The detaled desgns for the proposed DSSD adder, subtractor, and unfed add/subtract unt were explaned. The results of synthess of the proposed adder and other prevous adders, as was tabulated n Table III, show 4% speed mprovement over the fastest prevous desgn. The proposed fully redundant parallel decmal multpler, apparently the frst one of ths knd, s compared wth the best nonredundant multpler due to [6] showng 4% speed mprovement. 5

8 We beleve that the latency of the proposed fully redundant DSSD dvder s no more than that of the nonredundant one due to [8]. The same outlne desgn can be appled for a fully redundant DSSD square rooter. Ths research can be further contnued by synthess of the proposed multpler and dvder and usng benchmarks to evaluate the speed advantage of the proposed framework n typcal computatons. Acknowledgement Ths research has been funded n part by the IPM School of Computer Scence under grant #CS87-- and n part by Shahd Behesht Unversty under grant #D/6/. References [] Cowlshaw, M. F., Decmal Floatng-Pont: Algorsm for Computers, n Proc. of the 6 th IEEE Symposum on Computer Arthmetc, pp. 4-, Jun.. [] Busaba, F. Y., Krygowsk C. A., L W. H., Schwarz E. M., and Carlough S. R., The IBM z9 Decmal Arthmetc Unt, n Proc. of the 5 th Aslomar Conference on Sgnals, Systems, and Computers, Vol., pp. 5 9, Nov.. [] Shankland, S., IBM s POWER6 Gets Help wth Math, Multmeda, ZDNet News, Oct. 6. [4] Webb C. F., IBM z: The Next-Generaton Manframe Mcroprocessor, IEEE Mcro, Vol. 8, Issue, pp. 9-9, 8. [5] Lang, T. and A. Nannarell, A Radx- Combnatonal Multpler, n Proc. of the 4 th Aslomar Conference on Sgnals, Systems, and Computers, Nov. 6. [6] Vazquez, A., E. Antelo, and P. Montusch, A New Famly of Hgh-Performance Parallel Decmal Multplers, n Proc. of the 8 th IEEE Symposum on Computer Arthmetc, pp. 95-4, 7. [7] Nkmehr H., B. Phllps, and C.-C. Lm, Fast Decmal Floatng-Pont Dvson, IEEE Trans. on VLSI Systems, Vol. 4, pp.95 96, 6. [8] Lang T. and, A. Nannarell, A Radx- Dgt Recurrence Dvson Unt: Algorthm and Archtecture, IEEE Trans. Computers, 56(6), pp , Jun. 7. [9] Vazquez A., E. Antelo, P. Montusch, A Radx- SRT Dvder Based on Alternatve BCD Codngs, n Proc. of the 5 th Internatonal Conference on Computer Desgn, pp. 8-87, Oct. 7. [] Jmeno A., Hgno Mora, Jose L. Sanchez, and Francsco Pujol, A BCD-Based Archtecture for Fast Coordnate Rotaton, Journal of System Archtecture, Vol. 54, Issue 8, pp , Aug. 8. [] Crookes D., and M. Jang, Usng Sgned Dgt Arthmetc for Low-power Multplcaton, Electroncs Letters, Vol. 4, No., pp. 6-64, May 7. [] Svoboda, A., Decmal Adder wth Sgned Dgt Arthmetc, IEEE Trans. on Computers, Vol. C-8, No., pp. -5, Mar [] Shraz, B., D.Y. Yun, and C.N. Zhang, RBCD: Redundant Bnary Coded Decmal Adder, n IEE Proc. Computer & Dgtal Technques, Vol.6, No., Mar [4] Nkmehr H., B. J. Phllps, and C. C. Lm, A Decmal Carry-Free Adder, n Proc. of the SPIE Conference. Smart Mater., Nano-, Mcro-Smart Syst., pp , Dec. 4. [5] Erle, M. A., E. M. Schwartz, and M. J. Schulte, Decmal Multplcaton wth Effcent Partal Product Generaton, n Proc. of the 7 th IEEE Symposum on Computer Arthmetc, pp. -8, Jun. 5. [6] Oberman S. F., Desgn Issuen Hgh Performance Floatng Pont Arthmetc Unts. PhD thess, Stanford Unversty, Nov [7] Kenney, R. D., M. J. Schulte and M. A. Erle, A Hgh- Frequency Decmal Multpler, n Proc. of the IEEE Internatonal. Conference on computer Desgn: VLSI n Computers and Processors, pp. 6-9, Oct. 4. [8] Schmookler, M. and Wenberger A., Hgh Speed Decmal Addton, IEEE Trans. on Computers, Vol. C-, No. 8, pp , Aug. 97. [9] Vazquez A. and E. Antelo, Condtonal Speculatve Decmal Addton, n Proc. of the 7 th Conference on Real Numbers and Computers, pp , Jul. 6. [] Parham, B., Generalzed Sgned-Dgt Number System: A Unfyng Framework for Redundant Number Representaton, IEEE Trans. on Computer, Vol. 9, No., pp , 99. [] M. Daumas, and D. W. Matula, Further Reducng the Redundancy of a Notaton over a Mnmally Redundant Dgt Set, Journal of VLSI sgnal processng, Vol., pp. 7-8,. [] Kornerup Peter, Revewng 4-to- Adders for Mult- Operand Addton, Journal of VLSI Sgnal Processng, Sprnger, Vol. 4, No., pp. 4-5, May 5. [] Sutherland, I. E., R. F. Sproull and D. Harrs, Logcal Effort: Desgnng Fast CMOS Crcuts, Morgan Kaufman, 999. [4] Dadda, L., Mult Operand Parallel Decmal Adder: a Mxed Bnary and BCD Approach, IEEE Trans. on Computers, Vol. 56, No., pp. -8, Oct. 7. [5] Erle, M. A. and M. J. Schulte, Decmal Multplcaton Va Carry-Save Addton, n Proc. of the Conference on Applcaton-Specfc Systems, Archtectures, and Processors, pp , Jun.. [6] Jaberpur G. and Amr Kavan, Improvng the Speed of Parallel Decmal Multplcaton, IEEE Trans. on Computers, to appear. [7] Ercegovac M. D., and T. Lang, Dgtal Arthmetc, Morgan Kaufman, 4. [8] Flynn M. J., and S. F. Oberman, Advanced Computer Arthmetc Desgn, John Wley,. [9] Wang L. K., and M. J. Schulte, A Decmal Floatng- Pont Dvder Usng Newton Raphson Iteraton, Journal of VLSI Sgnal Processng, Vol. 49, pp. -8, 7. [] Moskal, J., E. Oruklu, J. Sane, Desgn and Synthess of a Carry-Free Sgned-Dgt Decmal Adder, n Proc. of the IEEE Internatonal Symposum on Crcuts and Systems, pp. 89-9, May 7. 5