Voltage-Fed Three-Phase Push-Pull DC-DC Converter

Transcription

1 Voltage-Fed hree-phase Push-Pull DC-DC Cverter Hugo R. E. arco and Ivo Barb IEEE, Senor Member Power Electrcs Insttute INEP Federal Unversty of Santa Catarna - UFSC P. O. box Floranópols SC- Brazl estofanero@nep.ufsc.br vobarb@nep.ufsc.br Abstract-hs paper presents the voltage-fed three-phase pushpull dc-dc cverter, some of the man characterstcs are low sze and lght weght of the nput and output flters, reduced number of compents, n-pulsat current n the output, n-pulsat current n the nput for 33.3% of duty cycle and low voltage stresses the semcductors. Some applcats can be battery chargers, automotve, ntercnect of photovoltac, wnd, and fuel cells systems. Analyss and a desgn approach, for the proposed cverter under large nput voltage and load varat, are presented. Fnally, theoretcal results are expermentally verfed. I. INRODUCION Some applcats such as battery chargers, the low voltage and the hgh current n the output make the push-pull cverter a typcal solut [], but, t s necessary to employ resant technque to allevate the flux-mbalance problem [], [3] and [4]. A another solut s the three-phase dc-dc cverter [5], whch requres a larger number of compents, however, ts use s ly justfed n hgh power applcats. Many works were made to mprove ths cverter performance, e. g. as n the asymmetrcal duty cycle [6], soft swtchng [7] and resant ccepts [8]-[9]. hey ncrease the effcency but do not reduce the number of compents of the three-phase cverter. In ths paper a new cverter whch was generated from the cvental voltage-fed push-pull cverter showed n the Fg. s proposed. hrough the replacement of the snglephase transformer by a three-phase transformer, results n the crcut shown n Fg.. It s denomnated the voltage-fed three-phase push-pull cverter. he advantages of ths cverter nclude: ) ower rms current through the swtches; ) Reduct n sze of the flter nductor f and the flter capactor C o ; 3) Reduced number of compents, n compars wth tradtal three-phase cverters; 4) Operat from 0% to 66.6% of duty cycle, 6.6% more than the voltage-fed push-pull cverter; 5) N-pulsatng current n the nput for operat wth 33% of the duty cycle; 6) ow voltage stress n the semcductor for duty cycle less than 33.3%. As for the dsadvantages: ) Ctrol crcut complexty, may requre a dgtal processor; Fg.. Voltage-fed push-pull cverter Fg.. Voltage-fed three-phase push-pull cverter ) Hgh voltage stress n the semcductors for duty cycle more than 33.3%, t becomes three tmes the nput voltage the swtches. Even though the cverter s a step-down, t s possble to obtan an output to nput voltages rato hgher than the unt through the turns rato of the transformer (n =N p /N s ). However, t rases the voltage stress the dodes for turns rato lower than the unt (n <). he descrpt of the prncple of operat s presented for ctnuous cduct mode (CCM) and dsctnuous cduct mode (DCM). Mathematcal analyss n steady state s also treated, comprsng, the equats of the statc gan n CCM and DCM, output characterstcs, current rpple n the nductor, voltage rpple and rms current n the capactor. Fnally, expermental results are presented. II. CIRCUI OPERAION he operat prncple of the cverter s made csderng steady state operat. hree-phase transformer and semcductors are deal, and the capactor s large enough so that the output voltage s cstant. he gatng sgnals u, u and u 3 are 0º phase shfted from each other. hrough these es the cduct tme t of the swtches durng e swtchng tme perod s s /09/$ IEEE 956

2 ctrolled. he rato between these tmes s called of duty cycle D (D = t / s ). In ths cverter t s employed the pulse-wdth modulat (PWM), where the output voltage s regulated adjustng the durat of the swtches and keepng a cstant swtchng tme perod. Four modes are presented by the proposed cverter. A. Ctnuous cduct mode for D < /3 In ths mode, the current through the nductor s ctnuous. Sx stages are presented by the cverter; the two frst stages are shown n the Fg. 3, whch correspd to the nductve energy storage and the transference of the stored nductve energy. hese states happen three tmes n a swtchng tme perod (Fg. 4).. Stage of storage he storage of energy n the nductor happens when e swtch s cductng, therefore the nductor stores energy three tmes durng a swtchng tme perod (Fg. 4). Csderng the case of the Fg. 3(a), the swtch S s turned at tme t 0, the nput voltage s appled to the prmary wndng of the phase (), the nduced magnetc flux n the phase s equally dstrbuted n the other phases, so the voltages the prmary wndngs of the phases and 3 are the half part of nput voltage (). he voltage the nductor s postve (3), ts current s cducted through the dodes D and D 3 (4), csequently the current n the prmary wndng of phase s half part of the nductor current referred to the prmary sde (5). Because of that ly S cducts, and ts current s equal to the nput current (6). he voltages the semcductors are gven by (7)-(8). vp = E () E vp = vp3 = () d E = Vo (3) dt n f D = D3 = (4) p = = (5) n S = (6) 3 vs = vs3 = E (7) 3 E vd = vd3 = n (8). Stage of transference In ths stage, the stored energy n the nductor s transferred to the load when all swtches are turned-off. he transference happens three tmes n a swtchng tme perod (Fg. 4). Due to the all dodes are cducng (Fg. 3(b)), the voltage n the prmary and secdary wndngs of the transformer are zero (9), thus the voltage the nductor s equal to the output voltage (0). he current through each dode s e-thrd of the nductor current (). he voltages the swtches are equal to the nput voltage (). Fg. 3. Frst and secd stage n CCM for duty cycle less than 33.3% of the three-phase push-pull cverter Fg. 4. Man waveforms n CCM for duty cycle less than 33% of the threephase push-pull cverter vp = vp = vp3 = 0 (9) d Vo = dt f (0) D = D = D3 = 3 () /09/$ IEEE 957

3 v = v = v = E () S S S3 B. Dsctnuous cduct mode for D < /3 In ths mode, the current through the nductor s dsctnuous; therefore three stages are present n the nductor, e storage-energy, e transference-energy and e zero-energy, the two frst stages are the same as n the CCM. In the zero-energy stage, the nductor current s zero. he load power s suppled by the capactor. he man waveforms of ths mode are shown n Fg. 5. Fg. 5. Man waveforms n DCM for duty cycle less than 33.3% of the threephase push-pull cverter C. Ctnuous cduct mode for /3 D < /3 he two frst stages n ths mode are shown n the Fg. 6, where t s possble to see that the storage stage n the prevous CCM (Fg. 3(a)) becomes a transference stage here, however, the equats n both modes are the same. herefore, ly the stage of storage s presented. he man waveforms of ths mode are shown n Fg. 7.. Stage of storage In ths stage two swtches are cducng. Csderng the case showed n the Fg. 6(a), the swtches S and S 3 are cducng. he nput voltage s appled the phases and 3 of the prmary wndngs of the transformer (3), these voltages nduces magnetc fluxes whch are summed n phase 3, thus the voltage over phase s twce the nput voltage (4). he nductor voltage s postve (5). Only D cducts the nductor current (6), csequently the current through the phase and 3 of the prmary wndngs s equal to the nductor current referred to prmary sde (7). he nput current s the sum of the currents from the swtches (8). he voltages the semcductors are gven by (9)-(0). vp = vp3 = E (3) vp = E (4) d E = Vo dt n f (5) D = (6) p = S = p3 = S3 = n (7) = n (8) vs = 3E (9) E v 3 3 D = vd = n (0) Fg. 6. Frst and secd stage n CCM for duty cycle from 33.3% to 66.6% of the three-phase push-pull cverter Fg. 7. Man waveforms n CCM for duty cycle from 33.3% to 66.6% of the three-phase push-pull cverter /09/$ IEEE 958

4 D. Dsctnuous cduct mode for /3 D < /3 In the same way as n DCM for duty cycle of less than 33%, the nductor has three stages, where the stages of storage and of transference are smlar to the CCM. he man waveforms n ths mode are shown n the Fg. 8, t can see that the nductor transfers all stored energy to the load, csequently ts current becomes zero, after ly the capactor supples the load. Fg. 8. Man waveforms n DCM for duty cycle from 33.3% to 66.6% of the three-phase push-pull cverter III. MAHEMAICA ANAISIS In ths sect are developed the man equats for the desgn of the cverter. A. Statc gan. Statc gan n CCM Accordng to the Fg. 4 and 7, the average nductor voltage n e-thrd of the swtchng tme perod s zero (). 3 s /3 V = vdt 0 = () t0 s Replacng (3) and (0) n () for duty cycle less than 33.3%, leads to (). E t t Vo Vo = 0 () n 3 Substtutng (5) and (3) n () for duty cycle more than 33.3% and less than 66.6%, t obtans (3). E t E t Vo + Vo = 0 (3) n 3 n 3 herefore, the statc gan n CCM s gven by (4). 3 D, f, D /3 V < o n a = = (4) E ( 9D ), f, /3 D < /3 n. Statc gan n DCM he statc gan n DCM s obtaned from the average nput current or the average output current accordng to the duty cycle. For duty cycle less than 33.3%, the average nput current s obtaned from the Fg t Δ I = (5) 4n From (3) s obtaned (6). E t Δ = Vo (6) n f Ideally, the relatshp between the nput current and the output current s gven by (7). Vo I = Io (7) E Replacng (6) and (7) n (5), t s obtaned (8). I o f 3D E Io = = (8) E s 4n nv o For duty cycle of 33.3% to 66.6%, the average nput current s obtaned from the Fg Δ Δt0 Io = (9) From (5) s obtaned (30). E 3t Δ = Vo (30) n 3f From the Fg. 8 s obtaned (3). 3t Δ s f n Δ t0 = + (3) 3 nv o E Substtutng (30) and (3) n (9), t s obtaned (3). E nvo I ( 3 ) o = D (3) n nvo E Fnally, the statc gan n DCM s gven by (33). 3D D, f, D < /3 n 4n Io + 3D a = (33) n Io + ( 3D ), f, /3 D < /3 n 4n Io + ( 3D ) B. Output characterstc Fg. 9 shows the output characterstc of the cverter, the turns rato of the transformer s assumed to be :. he graphc s obtaned from (4) and (33). C. Current rpple n the nductor he current rpple n the nductor n CCM can be calculated from the stage of storage or of transference. For duty cycle less than 33.3%, t s obtaned from (3). Δ f t Δ = = (34) V s o na For duty cycle of 33.3% to 66.6%, t s obtaned from (5). Δ f 3t Δ s = = (35) V s o na /09/$ IEEE 959

5 Fg. 9. Output characterstc of the three-phase push-pull cverter Replacng the statc gan (4) n (34) and n (35), the current rpple n the nductor (36) s obtaned. 3 D, f, D < /3 3 Δ = (36) 3D ( 3 D ), f, /3 D < /3 9D D. Flter capactor he waveform of the capactor current s shown n the Fg. 0, t s to CCM, from that s obtaned the voltage rpple n the capactor and ts rms current. Fg. 0. Current and voltage rpple n the flter capactor. Voltage rpple n the capactor for CCM he voltage rpple n the capactor can be obtaned by (37). + ΔQ Co = (37) Δ vco Accordng to Fg. 0, t s gotten (38). Δ Co Δ Q + = (38) 8 Csderng that the operat frequency of capactor s three tmes the swtchng frequency ( Co = s /3), and replacng (38) n (36), t s obtaned (39). ΔvCo Δ vco = f Co fs = Δ (39) Vo 4 Substtutng (36) n (39), t s gotten the voltage rpple n the capactor (40). 3 D, f, D < /3 7 Δ vco = (40) ( 3D)( 3D ), f, /3 D < /3 4 9D. RMS current n the capactor for CCM Equat (4) can be used to the calculate the rms current through the capactor, ths equat correspds to the current waveform of the Fg. 0. Δ Co tx ICef = (4) 4 3 ty he relatshp (4) between the tmes tx and ty are obtaned from Fg. 0. Co tx + ty = (4) Replacng (4) n (4), t s obtaned (43). Δ ICef = (43) 3 Fnally, the rms current through the capactor s gven by (44). I Cef 3 D, f, D < /3 Δ 6 3 = = 3 ( 3D)( 3D ), f, /3 D < /3 3( 9D ) (44) E. Voltage stresses the semcductors he voltage stress n the swtches and the dodes can be determned by (45) and (46) respectvely. 3 E, f, D < /3 VSmx = (45) 3 E, f, /3 D < /3 3 E, f, D < /3 n VDmx = (46) E 3, f, /3 D < /3 n IV. EXPERIMENA RESUS Fg. shows the man currents of the cverter for duty cycle of 7%. he output voltage was 4V, the average output current was 9A. he waveforms of ths fgure correspd to theoretcal waveforms of Fg. 4, where the nput current s pulsatng and the output current s ctnuous, the swtch current ly cducts n e-thrd of swtchng tme perod and ts value s equal to the nput current. As for the dode current, t cducts when the swtch does not cduct, ts values are e-thrd and a half of output current. In the same way, Fg. shows the currents correspdng to duty cycle of 58%, where the voltage and average current n the output were 60V and 7.8A respectvely. Currents for duty cycle of 33.3% are shown n the Fg. 3, the result shows that the nput and the output current are npulsatng. he nput current rpple correspds to the magnetzat current of the transformer /09/$ IEEE 960

6 Fg. 4. Inductor current rpple n CCM Fg.. Currents for duty cycle of 7%: channel nput current, channel output current, channel 3 swtch current, channel 4 dode current Fg.. Currents for duty cycle of 58%: channel nput current, channel output current, channel 3 swtch current, channel 4 dode current V. CONCUSION In ths paper a new topology denomnated voltage-fed three-phase push-pull dc-dc cverter was proposed. Some characterstcs of the cverter are the reduced sze and lght weght of the flter nductor and the flter capactor, low voltage stress n the semcductors, and reduced number of compents. For turns rato :, the output voltage s a half of the nput voltage for duty cycle of 33.3%, f the duty cycle s hgher than 66.6%, the output voltage s twce the nput voltage. he expermental result verfed the theoretcal analyss presented n ths work for the waveforms and the relatshp between the current n the cverter. he expermental results where obtaned for 7%, 33.3% and 58% of duty cycle. Fnally, the compars between theoretcal curve and expermental results of the current rpple n the nductor showed that these es are approxmately equal valdatng the study. REFERENCES Fg. 3. Currents for duty cycle of 33.3%: channel nput current, channel output current, channel 3 swtch current, channel 4 dode current Fnally, the theoretcal and the expermental nductor current rpple are shown n the Fg. 4, the result of the compars between these es shows that the theoretcal curve descrbes perfectly the rpple behavor for duty cycle less than 33.3%, but n the other case, there s a lttle dfference. hs s due to the leakage nductance of the transformer that dstorts the waveform of the current rpple and was not csdered n the theoretcal analyss. [] N. Mohan,. M. Undeland, and W. P. Robbns, Power Electrcs, New York: John Wley & Ss, 995. [].-F. Wu, J.-C. Hung, J.-. a, C.-. a, and Y.-M. Chen, An actve-clamp push-pull cverter for battery sourcng applcats, n IEEE ransacts Industral applcats., vol. 44, no., pp , Jan.-feb [3] M.J. Ryan, W.E. Brumsckle, D.M. Dvan, and R.D. orenz, A new ZVS C-resant push-pull DC-DC cverter topology, n IEEE ransacts Industral applcats., vol. 34, no. 5, pp , Sept.-Oct [4] I. Boyaroate and S. Mor, A new ZVCS resant push-pull DC/DC cverter topology, n Proc. Appl. Power Electr. Cf., 00, pp [5] P. D. Zogas, A. R. Prasad, and S. Manas, Analyss and desgn of a three phase off-lne dc/dc cverter wth hgh frequency solat, n Proc. IEEE Industry Applcats Soc. Annu. Meetng, Pttsburgh, PA, Oct. -7, 988, pp [6] D. S. Olvera Jr. and I. Barb, A three-phase zvs pwm dc/dc cverter wth asymmetrcal duty cycle for hgh power applcats, n IEEE ransacts Power Electrcs, vol. 0, no., pp , March 005. [7] J. Jacobs, A. Averberg and R. De Dcker, A novel three-phase dc/dc cverter for hgh-power applcats, n 35 th Annual IEEE Power Electrcs Specalsts Cference (PESC 004), pp , Aachen, Germany, 004. [8] A. K. S. Brat and. Zeng, Analyss and desgn of a three phase CCtype resant cverter, n Proc. IEEE 7 th Annu. Power Electrcs Specalsts Cf. (PESC 96), vol., Baveno, Italy, Jun. 3-7, 996, pp [9] P. D. Zogas, A. R. Prasad, and S. Manas, A three phase resant PWM dc/dc cverter, n Proc. IEEE nd Annu. Power Electrcs Specalsts Cf. (PESC 9), Cambrdge, MA, Jun. 4-7, 99, pp /09/$ IEEE 96