Unified Non-Inverting and Inverting PWM AC-AC Converter with Versatile Modes of Operation

Transcription

1 Unfed Non-Invertng and Invertng PW AC-AC Converter wth Versatle odes of Operaton Peng, ember, IEEE, Yhua Hu, Senor ember, IEEE Abstract Ths paper proposes unfed non-nvertng and nvertng AC-AC converter (UNI-AC) usng pulse wdth modulaton (PW) for the utlty voltage compensaton. It offers four effectve swtchng states to regulate the output voltage n bpolar manner, facltatng versatle modes of operaton wth dfferent number of swtchng states beng modulated. Each mode of the proposed UNI-AC s able to compensate both the grd voltage sag and swell problems due to ts bpolar voltage gan. The operatonal prncple and comparson for all these modes are nvestgated n detals. Also, the UNI-AC s reversble and compatble wth full range of power factor. Other techncal merts offered by the proposed approach nclude the compact hardware nstallaton, reduced swtch voltage stress (also low dv/dt) and decreased control complexty. Detaled analyss and expermental verfcaton are presented n ths paper. Index Terms polar voltage gan, PW drect ac-ac converter, utlty voltage compensaton, versatle modes of operaton. O I. INTRODUCTION WING to the rapdly ncreasng load condton dversty and varous dsturbance sources at the dstrbuton level of power system, the grd voltages suppled to local consumers are exposed to an ncreasng rsk of power qualty problems such as utlty voltage sag/swell, three-phase unbalance and voltage fluctuaton (flcker) phenomenon, whch are usually orgnated from the severe load varatons, for example, the transent of large power motors; as well as the vast use and uneven spread of sngle-phase load [1, ]. The flexble ac transmsson system (FACTS) devces are a range of technques to address the grd control ssues. Among all knds of FACTS devces, the seres compensator s able to stablze the dstrbutve grd voltage durng the power qualty events, servng as the dynamc voltage restorer (DVR) [3-5]. Typcal DVR employs the dc-ac voltage source converter anuscrpt receved June 0, 016; revsed August 11, 016; accepted September 13, 016. P. s wth the Electronc & Electrcal Engneerng Department, Unversty of Strathclyde, Glasgow, G1 1XW, U.K. (e-mal: peng.l@strath.ac.uk). Y. Hu s wth the Electrcal Engneerng and Electroncs Department, Unversty of verpool, verpool, 69 3GJ, U.K. (e-mal: y.hu35@lverpool.ac.uk). (VSC) to generate the desred ac voltage n seres wth the grd and supply proper amount of power to the load. Specfcally, to mantan the grd voltage ampltude wthout consderng the harmonc dstorton and phase-shft, the drect ac-ac converter s vable to replace the szeable dc-ac soluton by savng the dc-lnk capactor bank; thus, reducng the footprnt and cost as shown n Fg. 1. Under ths motvaton, the ac-ac converters for voltage ampltude regulaton are of nterest to be studed contnuously [6, 7]. Fg. 1. DVR wth ac-ac converter for grd voltage compensaton. The basc ac-ac converters ncludng buck, boost and buck-boost topologes all suffer from a unpolar voltage gan range, whch, n use of the grd voltage compensaton, restrcts them to mtgate ether voltage sag or swell but not both. Although the tapped-wndng transformer can assst them n generatng bpolar voltage, the combned system cost and total volume are uneconomcal [8]. In order to overcome ths constrant, the Z-source topology based ac-ac converter has been presented to acheve the bpolar voltage output ablty by an addtonal mpedance network [9]. However, ths converter has a dscontnuous voltage transfer rato; also ts nput and output ports are floatng to each other, ncreasng the nsulaton demand for the couplng transformers n grd applcatons. An alternatve verson of Z-source ac-ac converter n [10] s able to share the same ground for nput and output but stll has a hgh cost due to the passve devce network. In [11, 1], a varety of quas-z-source based ac-ac converters are reported wth some advantages compared to the orgnal Z-source ac-ac converter such as the reduced passve devces, mproved nput profle and common ground shared by nput and output termnals. The Gamma structure Z-source ac-ac converter n [13] employs the coupled nductor to offer an extra hardware desgn degree of freedom for varyng the voltage gan. The man constrant of the above solutons s ther ncapablty of generatng n-phase step-down ac voltage; and hereby, the extremely sharp change n ts gan curve that s challengng for the adaptve adjustment of duty cycle command

2 from the controller. A reversed scheme of [1] s analyzed n [14]. Ths soluton has a contnuous bpolar voltage transfer rato wth the use of the nner voltage boostng cell; besdes, the ground sharng feature s kept. However, t stll suffers from the hgh voltage and current stresses for the power swtches (low devce utlzaton) as n the Z-source type converters due to the voltage lftng capactors; also, n these approaches, the hgh order passve elements n the mpedance network result n a low bandwdth for the converter transfer functons; hence, slow dynamc response. In an effort to reduce the passve devce volume, a current source type composte ac-ac converter usng sx undrectonal swtches s proposed n [15] wth a wde range bpolar voltage generaton capablty. It uses less number of passve elements compared to the Z-source based schemes; therefore, reducng the voltage (current) stress on the semconductor devce and enhancng the converter dynamc response. The drawbacks of ths soluton nclude the lack of common ground sharng and the complex modulaton due to ts composte structure. Ths paper nvestgates a unfed non-nvertng and nvertng ac-ac converter (UNI-AC) operatng n versatle modes thanks to the extra control degree of freedom. The UNI-AC offers followng features: t acheves contnuous and bpolar voltage transfer rato wthout sharp changes as n Z-source based converters; t has mproved flexblty and varous operaton modes wth ncreased number of control varables; the use of less passve devces n the UNI-AC leads to a reduced footprnt and hgher swtchng devce utlzaton (low electrcal stresses); also, the common ground between the nput and output ports s retaned. The remnder of ths paper s arranged as follows: secton II descrbes the prncples for dfferent operaton modes of the UNI-AC; n secton III, the performance evaluaton for the proposed converter under each mode s carred out; based on whch, the desgn gudelnes of the UNI-AC s suppled n secton IV; then, n secton V, the expermental test results are presented to verfy the proposed approach; fnally, the conclusons are hghlghted n secton VI. II. OPERATIONA PRINCIPE OF THE PROPOSED UNI-AC Fg.. The schematc of the proposed UNI-AC. The proposed UNI-AC s depcted n Fg., where the four bdrectonal swtches usng the back-to-back seres-connected nsulated gate bpolar transstor (IGT) are adopted to facltate the bdrectonal current conducton and bdrectonal voltage blockng capablty. In Fg., the two swtches n the same leg such as S 1 and S (or S 3 and S 4 ) are complementarly trggered usng pulse wdth modulaton (PW) scheme; and also, there must be two conducted swtches to form a power path at each nstance. ased on these constrants, t s concluded that there are four swtchng states are vald for regulatng the output voltage as descrbed n Fg. 3. (c) (d) Fg. 3. Four effectve swtchng states of UNI-AC: state I wth S 1 and S 4 turned on; state II wth S and S 3 turned on; (c) state III wth S and S 4 turned on; (d) state IV wth S 1 and S 3 turned on. The swtchng state I n Fg. 3 turns on S 1 and S 4 to force the nductor to release energy for chargng the capactor C. Whle for swtchng state II n Fg. 3, s charged by the nput source wth S 3 and S turned on; and the output current o s drectly drawn from the output capactor C. In Fg. 3(c), S 4 and S conduct to form a zero-nput power loop between and C, whch s noted as swtchng state III. The swtchng state IV when S 3 and S 1 are turned on as n n Fg. 3(d) represents the nductor current freewheelng mode wth the output current suppled by capactor C. ased on Fg. 3, t s observed that dfferent combnatons of the four states can result n versatle modes of operaton; and ts control degrees of freedom vares accordngly. Detaled analyss for all possbltes s suppled n ths secton.

3 A. Operaton mode A Fg. 4. Gate sgnals of the UNI-AC n operaton mode A: postve voltage gan; negatve voltage gan. Wth the gate sgnals arranged as n Fg. 4, ths mode uses the swtchng states I-II of Fg. 3 for the voltage converson. The four swtches are vewed to be separated nto two groups {S 1, S 4 } and {S, S 3 }; and these two groups are conducted n a complementary manner. Assumng the swtchng frequency s suffcently hgh compared to the fundamental frequency, f d s the duty cycle of {S 1, S 4 } n pulse wdth modulaton (PW), the swtchng average model of the UNI-AC s acheved as (1) usng the establshed modellng procedures n [16, 17]. d d ( vn vo ) (1 d) vn dt (1) dv o C d ( ) (1 ) o d o dt In steady state, snce all state varables of the UNI-AC are purely dstrbuted n fundamental frequency, the rght terms of (1) s approxmately vewed as zero due to ther low varaton rates. Hence, the transfer rato of the voltage ampltude from nput voltage to output voltage s acheved based on a quas-steady-state analyss as shown n (), where v o_m and v n_m are the magntude of the output and nput voltages respectvely. vo_ m 1 A () v d n _ m Then, the plot for the relatonshp between A and d can be drawn as n Fg. 5. Notce that d s the only control degree of freedom n the operaton mode A of UNI-AC; therefore, ts voltage magntude gan n ths case can be descrbed by a two-dmensonal curve, where t s observed that the UNI-AC can offer bpolar voltage gan to ether compensate the voltage sag or swell as a voltage stablzer. swtchng states I-III n Fg. 3 to offer a bpolar voltage transfer rato. For postve voltage gan, S 4 s kept to be conducted whle S 3 s turned off constantly; at the same tme, S 1 and S are modulated n a PW manner. Ths scheme combnes swtchng states I and III to form a normal buck type operaton for the UNI-AC wth a gan range from 0 to 1. If negatve voltage gan s requred, states II and III are used, where S 1 remans blocked and S s turned on as short crcut. Hence, the UNI-AC operates as a typcal buck-boost converter wth natve voltage ampltude transfer rato. Fg. 6. Gate sgnals of the UNI-AC n operaton mode : postve voltage gan; negatve voltage gan. In mode, the gate sgnals are shown n Fg. 6; also, the duty cycles of S 1 and S 3, d 1 and d 3, are used to descrbe the UNI-AC performance. Due to the hybrd buck and buck-boost operaton, the dynamc equatons of the UNI-AC n ths case are pecewse, see (3) and (4). It s observed, when d 3 =0, the UNI-AC works n buck mode; whle f d 1 =0, t s an nvertng buck-boost converter. In further, by neglectng the varaton of the state varables n (3) and (4) under steady state, the UNI-AC voltage gan n mode can be acheved as n (5) wth bdrectonal voltage output ablty n a pecewse pattern. d d1 vn vo dt [0, 1], (3) dv 3 0 o d C o dt d d3 vn (1 d3) vo dt 0, dv 1 0 o 3 (1 3) ( ) d C d o d o dt vo_ m d1, when d3 0 vn _ m d3 / (1 d3), when d1 0 (4) (5) Fg. 5. Voltage ampltude transfer rato of the UNI-AC under operaton mode A usng swtchng states I-II.. Operaton mode Ths operaton mode of the proposed UNI-AC employs the Fg. 7. Voltage ampltude transfer rato of the UNI-AC under operaton mode usng swtchng states I-III.

4 From (5), the voltage gan of UNI-AC n mode can be dsplayed by Fg. 7 wth a three-dmensonal pecewse curve beng produced. In the coordnates of d 1, d 3 and, the frst part of the space curve s dstrbuted n the d 1 - plane wth d 3 =0 for the buck operaton; whle the second pece s located n d 3 - plane (d 1 =0) as a buck-boost converter for nvertng voltage generaton. Also, mode offers lower swtchng losses for UNI-AC compared to mode A due to ts reduced total swtchng actons offered by the buck and buck-boost pecewse operaton. C. Operaton mode C The mode C employs all swtchng states I-IV n Fg. 3 to supply mum control degree of freedom for the UNI-AC. In ths scenaro, the duty cycles of both legs are n PW manner as n Fg. 8,.e. d 1 and d 3 are free varables that are coordnated to regulate the output voltage. Hence, the dynamc equatons for UNI-AC mode C s descrbed by (6). Smlarly, the voltage gan for ths mode s manpulated to be (7). acheve a certan voltage gan for the UNI-AC, the two control nputs can have nfnte number of combnatons as observed from Fg. 9. In practcal control desgn of the proposed UNI-AC n operaton mode C, the sgnal of d s can be set to adjust the mum nvertng output voltage range and mantaned constant when d 1 s changng for regulatng the output voltage. In ths manner, the lnearty of the UNI-AC transfer functon can be guaranteed. For example, n (7), f d 3 s set to be 0.5, the voltage gan c becomes a lnear expresson of d 1 rangng from -1 to 1 as shown by the lne S n Fg. 9. In further, wth dfferent preset values of d 3, c can be a famly of straght lnes n parallel wth S, resultng n the varant output voltage range. Ths method s an optmzed way for ndexng d 1 and d 3 from the three-dmensonal surface of voltage gan n Fg. 9 when operatng the UNI-AC under mode C. It s worth notcng that the UNI-AC gan curves n mode A and are both specal cases of the voltage transfer rato for mode C. When settng d 1 =1-d 3 =d n (7), t s smplfed to be the same as () for mode A; whle f (7) s restrcted by the assumpton of ether d 1 =0 or d 3 =0, the same concluson as (5) for mode can be acheved. In Fg. 9, the dentfed curves A and are transplanted verson of the gan curves n Fg. 5 and Fg. 7 for operaton mode A and, respectvely. Fg. 8. Gate sgnals of the UNI-AC n operaton mode C: postve voltage gan; negatve voltage gan. d d v d v (1 d ) v dt dv o C (1 d3) o dt C 1 n 3 n 3 o v d d v 1 d o_ m 1 3 n _ m 3 Fg. 9. Voltage ampltude transfer rato of the UNI-AC under operaton mode C usng swtchng states I-IV. In (7), snce d 1 and d 3 are both free varables for the control of output voltage, the plot of c dependng on d 1 and d 3 s a three-dmensonal surface as shown n Fg. 9. In ths mode, to (6) (7) III. PERFORANCE EVAUATION OF UNI-AC In ths secton, the performance evaluaton for the UNI-AC s carred out; and then, a comprehensve comparson between dfferent operaton modes of UNI-AC and other tradtonal ac-ac converters are presented. A. UNI-AC and current source ac-ac converter The conventonal current source type ac-ac converter n [18] employs an ntermedate current dc-lnk to connect the two back-to-back undrectonal swtch based brdge crcuts, where twce amount of swtches are nserted n the conducton path compared to the UNI-AC, resultng n hgher losses. Another man drawback of ths converter compared to UNI-AC s the ncreased sze and weght due to the dc current carred by the ntermedate nductor. Whle n the UNI-AC, the nductor current s n ac pattern wth small footprnt. Also, the common ground feature between nput and output s lost n the current source ac-ac converter.. UNI-AC and mpedance source based bpolar ac-ac converters Observed from Fg. 3, the voltage stresses of S 1 and S n UNI-AC are the same as the nput voltage v n ; whle S 3 and S 4 sustan a voltage of v n -v o. The current ratng for all swtches of UNI-AC are equal to the nductor current. y assumng the state varables varaton rates n (1), (3), (4) and (6) to be zero, the steady state voltage transfer rato of the UNI-AC under dfferent modes have been acheved by (), (5) and (7). Smlarly, the transfer ratos {K A, K, K C } for the nductor current magntude _m from load current magntude o_m can be solved nto (8), (9) and (10) for mode A, and C, respectvely. Snce mode C s the generc case of UNI-AC, t s adopted for a comparson wth the bpolar ac-ac converter n

5 [14], the (modfed) quas-z-source schemes n [11, 1], and the orgnal Z-source ac-ac converters n [9, 10], see TAE I. _ m 1 K A (8) d K o_ m _ m 3 o_ m 1, when d 0 1/ (1 d3), when d1 0 _ m 1 KC 1 d o_ m 3 (9) (10) In ths comparson, the fxed nput voltage and load current magntude v n_m and o_m are assumed for each converter; and based on (7) and (10), the voltage and current stresses of UNI-AC power swtches under mode C can be quantfed as n TAE I, where t s observed the proposed soluton employs reduced number of passve components than the Z-source type converters, resultng n lower swtchng voltage and current ratngs. Therefore, although more power swtches are used n UNI-AC, ts total semconductor devce cost and conducton losses are not ncreased compared to ts rvals wth hgh power rated swtches n TAE I. esdes, the overall sze of UNI-AC s reduced drastcally wth the sgnfcant save on the passve elements, leadng to a compact hardware desgn and a hgh power densty. Also, the proposed converter s able to share a common ground for the nput and output ports by the sold connecton of the reference termnals. Due to the ncreased control degree of freedom n the UNI-AC, ts voltage gan s controlled by two varables, d 1 and d 3 ; whle other canddates have only one control nput. Ths can brng versatle modes of operaton to the proposed converter as analyzed n secton II wth advanced features. For example, the dynamc response of UNI-AC s fast due to the less use of passve elements; further, n operaton mode of the UNI-AC, the swtchng losses can be reduced sgnfcantly snce there s only swtchng actons n one leg; also, the mode C offers two ndependent control degrees of freedom n the UNI-AC wth the possblty for a lnear bpolar modulaton range that s benefcal for the robustness and bandwdth of the controller due to the tme-nvarant features of the converter model. In contrast, the Z-source based converters usually have hgher number of poles and zeros n ther transfer functons ncludng rght-half-plane (RHP) zeros, whch, as a tme-varant model, wll drft when the operaton pont changes n an ac system. Ths deterorates the global stablty and dynamc response of the ac-ac converter appled as a voltage compensator [16]. C. Dfferent operaton modes of the UNI-AC In further, detaled performance of UNI-AC n dfferent operaton modes are nvestgated. If the desred voltage gan of the UNI-AC s from -1.5 to 1, the swtchng voltage stresses are the same for all operaton modes wth v n_m (nput voltage) for {S 1, S } and.5 v n_m (mum dfference between nput and output voltages) for {S 3, S 4 }; whle the current ratngs for the power swtches under each mode are dfferent dependng on ts extreme value of the duty cycle. From (), the control sgnal d (duty cycle of S 1 ) should range from to 1 n operaton mode A to guarantee the desred output voltage range; smlarly, usng (5) for mode, d 1 vares from 0 to 1 for non-nvertng buck operaton and d 3 changes from 0 to 0.6 for the nvertng buck-boost voltage generaton; n mode C, usng the lnear ndexng method, d 3 s fxed as 0.6 and d 1 s modulated from 0 to 1. ased on above observatons and (8)-(10), the current stresses for the power devces of UNI-AC n each operaton mode can be calculated as n TAE II, where t s found mode A suffers from the hghest swtchng current stresses due to ts hgher duty cycle for S 3 than other cases for generatng out-of-phase voltage. From (1), the rpple voltage and rpple current on the state varables of the UNI-AC n mode A can be estmated by (11), where f sw s the swtchng frequency. The mum rpple components are then acheved as n TAE II by substtutng the mnmum value of d nto (11) to generate the mum out-of-phase voltage (nvertng). vn _ m (1 d) _ A fsw (11) o_ m(1 d) v _ o A fsw C ased on (3) and (4) for mode, the rpple components equatons are n a pecewse pattern. Wthn postve gan area, the UNI-AC works n typcal buck mode wth mnmum rpple components; thus, the rpple expressons n the nvertng gan regon are focused, see (1). As n TAE II, the mum rpples happen at the negatve peak voltage gan pont when d 3 reaches ts mum, whch s 0.6. vn _ m d3 _ fsw, when d1=0 (1) o_ m d3 v _ o fsw C In mode C, from Fg.7 and (7), when d 1 s larger than d 3 for TAE I COPARISON RESUTS ETWEEN THE PROPOSED UNI-AC AND REPRESENTATIVE Z-SOURCE TYPE AC-AC CONVERTERS polar ac-ac converter n (modfed) quas-z source Orgnal Z-source ac-ac UNI-AC (n mode C) [14] ac-ac converters n [11, 1] converters n [9, 10] d 1 d 3 d 1 1 d 1 d Voltage gan 1 d 3 d 1 d 1 d S 1, S v n_m Swtchng voltage stress v n_m 1 v d n_m 1 v 1 d n_m 1 S 3, S 4 v n_m 1 d 1 1 d 1 d 3 Swtchng current stress o_m 1 1 d o_m 1 3 d o_m 1 1 d o_m 1 1 d two nductors, two three or two nductors, three three nductors, three Passve devce one nductor, one capactor capactors or two capactors capactors Ground sharng Yes Yes Yes Possble

6 postve voltage gan, the swtchng state II n Fg. 3 wll not be used; whle f d 1 s smaller than d 3 for negatve voltage transfer rato, the swtchng state I does not emerge. Smlarly, n ths mode, the UNI-AC rpple performance becomes worse durng the voltage nvertng regon; hence, (13) s employed to calculate the mum rpple current and voltage, whch are shown n TAE II wth d 3 =0.6 and d 1 =0. vn _ m ( d3 d1) _ C fsw, when d1< d3 (13) o_ m( d3 d1) v _ o C fsw C TAE II COPARISON ETWEEN EACH OPERATION ODES OF UNI-AC WITH VOTAGE GAIN FRO -1.5 TO 1 AND FIXED OAD CURRENT IO_ UNI-AC operaton mode ode A ode ode C Swtchng current ratng 3.5 o_m.5 o_m.5 o_m axmum voltage rpple o_m f sw C 0.6 o_m f sw C 0.6 o_m f sw C axmum current rpple v n_m f sw 0.6 v n_m f sw 0.6 v n_m f sw Conducton loss Relatvely hgh ow Hgh Swtchng loss Relatvely hgh ow Relatvely hgh Control degree of freedom One One Two Fg. 10. Percentage of the power swtch conducton losses n the UNI-AC: output voltage gan s 0.8; output voltage gan s -1. To evaluate the conducton losses of power semconductor devces n the proposed UNI-AC, two operatonal ponts wth bpolar voltage transfer rato of 0.8 and -1 are examned for each mode. It s observed from Fg. 3, n each nstance, there are always two swtches from dfferent legs n the conducton path. Snce the voltage ratngs of power swtches are the same for each mode, the equvalent IGT parameters ncludng ther total forward voltage drop and equvalent resstance are fxed and denoted by V F and R av, respectvely. Thus, f the output current s expressed by (14), from (10), the generc conducton losses are obtaned by (15). For gven output voltage v o_m, the output power S o s equal to ½v o_m o_m ; and the percentage of semconductor conducton losses are calculated usng (16). snt (14) o o _ m 1 Pcon ( ) V 0 F Rav d t V F 1 (1 ) o _ m o _ m Rav d3 d3 (15) Pcon = (16) So Pcon Specfcally, the equvalent duty cycle of d 3 for two cases wth 0.8 and -1 voltage gans can be determned usng (), (5) and (7). Then, assumng v n_m =150V, V F =0.8V and R av =0.03Ω, the conducton losses n percentage for the above cases can be plotted n Fg. 10, where mode has the lowest on-state power dsspatons. Also, as stated prevously, mode can reduce the swtchng losses wth the decreased swtchng actons. The above conclusons are lsted n TAE II, where t s concluded that mode s an optmzed operatonal trajectory for the UNI-AC n terms of effcency performance; whle the mode C offers superor control flexblty. IV. DESIGN OF THE UNI-AC ased on prevous analyss, the gudelnes of the parameter selecton for the UNI-AC are provded usng a scale-down case study n followng procedure: The known parameters: nput peak voltage v n_m =150V, output voltage gan range [ n, p ]=[-1.5, 1], total load mpedance Z =40Ω, swtchng frequency f sw =5kHz, allowable current and voltage rpples κ =0% of _m and κ v =10% of v o_m (or v n_m ); Recall Fg., voltage stresses of S 1 and S are equal to v n_m =150V; the voltage stresses of S 3 and S 4 are the subtracton of v n_m and the mum nvertng output voltage, whch s expressed as v n_m (1- n ) =375V; ased on (), (5) and (7), the duty cycle of S 3 for generatng the mum out-of-phase voltage (the voltage gan n ) n each mode can be obtaned as (17); d3_ A 11 ( n) d3_ 11 (1 n) 0.6 (17) d3_ C 0.6 Wth mum load current n (18); the swtch current stresses n each mode can be calculated by (19); o_ m vn _ m ( n, p ) 5.6A Z (18)

7 Istr _ A o _ m (1 d3_ A) 0A Istr _ o _ m (1 d3_ ) 14A (19) Istr _ C o _ m (1 d3_ C ) 14A The nductance value can be determned by (0), based on (11)-(13); v mn n _ m d3 _ A (1 d3 _ A ) A 1.09mH fsw o _ m v mn n _ m d3 _ (1 d3 _ ) 1.8mH (0) fsw o _ m v mn n _ m d3 _ C (1 d3 _ C ) C 1.8mH fsw o _ m The requred nput capactance depends on the duraton of current dscontnuty n the nput, whch s nearly zero for mode A. For other modes, wth the mum fundamental nput current n (1); the needed mnmum capactance can be calculated based on (); v n _ m n n _ m 8.44A (1) Z C mn n n _ m (1 d3_ ) 9μF v f v n _ m sw () The output capactance s chosen by (3) based on the voltage rpple requrement. mn o _ m d3 _ A CA 7.15μF fsw v vn _ m n mn o _ m d3 _ C 6μF (3) fsw v vn _ m n mn o _ m d3 _ C CC 6μF fsw v vn _ m n For all above calculated passve devces, ther reactve power ratngs should be reexamned as for an ac system, whch are requred be wthn the reasonable range of the total power capacty. To be compatble wth all operaton modes, the experment specfcatons of UNI-AC are selected as n TAE III, where OSFETs and dodes are adopted as bdrectonal swtches n ths low voltage desgn case. TAE III SPECIFICATION OF THE UNI-AC EXPERIENT Input voltage peak value v n_m 150V oad mpedance Z 40Ω Power ratng 300VA Swtchng frequency f sw 5kHz Inductance 1.3mH Output capactance C 10µF Input capactance C n 10µF drectonal swtch S 1-S 4 SPHX0N60S5 and STTH601 In fact, the rght terms of the volt-second balance equatons n (1), (3), (4) and (6) are not zero n steady state due to the reactve power consumpton of nductors; nstead, they should be equal to the loop voltage drop caused by nductor current flowng the nner mpedance r (loop resstance) and ω (ω s the fundamental angular frequency). If the load mpedance s Z and λ s mpedance rato n (4), the voltage gans of UNI-AC n each mode can be revsed as (5), (6) and (7). * v v o_ m * A n _ m r Z n _ m vo_ m (d 1) d v d d1, when d3 0; 1 d3(1 d3), when d1 0. (1 d3) vo_ m ( d d ) (1 d ) v (1 d ) * C n _ m 3 (c) (d) Fg. 11. Practcal gans of UNI-AC consderng nner mpedance: mode A; mode (postve); (c) mode (negatve); (d) mode C. (4) (5) (6) (7) Wth the parameters n TAE III and the total conducton path resstance of 0.45Ω, the voltage gans n (5), (6) and (7) can be plotted by Fg. 11. It s observed from Fg. 11 and (c), when the duty cycle of S 3 s larger than a crtcal value, the output voltage gan wll decrease sgnfcantly due to ts nner voltage drop, whch s smlar as n normal boost dc-dc converter. Ths has resulted n an uncontrollable regon for the proposed UNI-AC. Hence, n the test case of TAE III, d 3 s lmted to be lower than V. SIUATION AND EXPERIENT A. Smulaton Results The smulaton results of the UNI-AC wth specfcatons n TAE III are shown n Fg. 1. In ths test, the output voltage s controlled as 10V n-phase n Fg. 1 wth the largest nductor current n mode C; then, the output voltage s set to be 150V out-of-phase n Fg. 1; and nductor current n mode A s largest. Ths observaton agrees wth prevous analyss. Furthermore, the sampled waveforms of voltage across the bdrectonal swtches S and S 4 wth both postve and negatve voltage gans are gven for operaton mode C n Fg. 1(c) and (d), respectvely.

8 19] s adopted to avod addtonal passve snubber crcuts. Fg. 14 shows the voltage waveforms of the bdrectonal swtches S and S 4 for each case. It s observed that when the voltage gan of the UNI-AC changes to negatve drecton, for all the operaton modes, the swtchng voltage stresses on the swtches S 3 and S 4 become larger than those n postve gan regon. Ths s because the swtch leg composed by S 1 and S sustans a total voltage equal to nput voltage; whle the S 3 and S 4 together have to block the voltage dfference between the nput and output termnals. Specally, mnmzed swtchng acton (thus, swtchng losses) can be acheved by the operaton mode of the proposed converter as n Fg. 14 and (c). (c) (d) Fg. 1. Smulaton results for the UNI-AC: 10V non-nvertng output voltage and nductor current; 150V nvertng output voltage and nductor current; (c) voltage of swtches S and S 4 wth n-phase output voltage under mode C; (d) voltage of swtches S and S 4 wth out-of-phase output voltage under mode C. (c) (d). Experment Verfcaton For further verfcatons, a prototype of the UNI-AC has been bult and tested usng the same specfcatons n TAE III; then, an Infneon TC1796 DSP platform s adopted for the dgtal modulaton of the proposed converter. The photo of the expermental setup s dsplayed n Fg. 13. (e) (f) Fg. 14. Voltage on the bdrectonal swtches (Vs and Vs4): mode A wth voltage gan of 0.8; mode A wth voltage gan of -1; (c) mode wth voltage gan of 0.8; (d) mode wth voltage gan of -1; (e) mode C wth voltage gan of 0.8; (f) mode C wth voltage gan of -1. Fg. 13. Photo of the expermental setup. The UNI-AC test rg works n operaton mode A, and C at pre-set output voltage gan of 0.8 and -1, respectvely. In the PW mplementaton, all the gate sgnals are arranged n the centre-algned pattern. Specally, the duty cycle d 3 s set to 0.6 for operaton mode C. The safe commutaton strategy n [13, The lne frequency waveforms for UNI-AC are also shown n Fg. 15, where the nput voltage v n, nductor current and output voltage v o are dsplayed for the two pre-set operaton ponts under each mode, respectvely. In postve gan regon, operaton mode C has the hghest current stress for the power swtches (nductor current) due to the large conducton perod of S 3, whch results n poorest effcency performance n ths regon. On the other sde, wthn the negatve voltage gan area, the average swtchng current for mode A ncreases and fnally exceeds that n mode C. Hence, mode A s not compettve for producng hgh magntude out-of-phase voltage compared to mode and C due to the relatvely large crculatng current stmulated through the power swtches. Among all operaton cases, mode offers the lowest average current and conducton

9 losses for the power swtches. These observatons are n lne wth the analyss and conclusons n TAE II. A changes drastcally for dfferent operatonal ponts snce the duty cycle d 3 (thus, average current n the power swtches) has the largest varaton range among all modes. Whle n mode C, snce d 3 s fxed to offer a lnear modulaton range as shown n Fg. 11(d), the conducton losses of the UNI-AC n ths case are less nfluenced by the voltage gan change; thus, ts overall effcency dfference at dfferent operatonal ponts are manly determned by the swtchng losses. (c) (d) Fg. 16. The effcency performance of UNI-AC n dfferent modes and operaton ponts wth load varatons. (e) (f) Fg. 15. The nput voltage (vn), output voltage (vo) and nductor current ( ) waveforms: mode A wth voltage gan of 0.8; mode A wth voltage gan of -1; (c) mode wth voltage gan of 0.8; (d) mode wth voltage gan of -1; (e) mode C wth voltage gan of 0.8; (f) mode C wth voltage gan of -1. The measured total harmonc dstorton (THD) values of the UNI-AC output voltage wth -1 voltage gan for each operaton mode are lsted n TAE IV. As s analysed prevously, the swtch voltage stresses of the UNI-AC are much lower than those n the mpedance network based converters, whch means the overall dv/dt s smaller. Thus, generally, a reduced THD n the UNI-AC can be expected. Further, dfferent modes of the UNI-AC have dfferent PW patterns and harmonc content. The use of zero voltage states n mode reduces the total number of swtchng nstances and acheves lowest THD. TAE IV EASURED UNI-AC OUTPUT VOTAGE THD IN EACH ODE ode A ode ode C UNI-AC output voltage THD 3.56% 3.34% 3.88% If the nput voltage s 150V (peak value) and the nomnal resstve load s R =40Ω, by varyng the load R, the UNI-AC effcency for mode A, and C at voltage gan of 0.8 and -1 are shown n Fg. 16, whch ndcates that mode has hghest effcency performance for both 0.8 and -1 voltage gans. Ths s acheved by the reduced average current n the power devce and the mnmzed swtchng actons. The effcency for mode C. Smulaton Study of UNI-AC ased DVR Smulaton of the UNI-AC appled as a DVR s carred out based on the confguraton of Fg. 1. The nomnal grd phase voltage s 40V (root-mean-square, RS). In the UNI-AC devce, 10μH nductor and 10μF output capactor are adopted. The system power ratng s 10kVA per phase. Fg. 17 shows that the UNI-AC s able to generate ether n-phase or out-of-phase voltage to compensate both voltage sag and swell problems. Durng 0s~0.1s, the grd remans stable, and the UNI-AC devce produces domnantly reactve power to support the grd voltage at the load bus. Then, at 0.1s, the grd voltage starts a 0% swell and the UNI-AC generates out-of-phase voltage to force the voltage at the crtcal bus to track the reference. Fnally, at 0.s, the grd experences 30% sag, whch s managed by the UNI-AC wth n-phase voltage njecton. Fg. 17. DVR applcaton of the proposed UNI-AC for dstrbuted grd voltage sag/swell compensaton. VI. CONCUSION In ths paper, the unfed non-nvertng and nvertng PW ac-ac converter (UNI-AC) wth reduced passve components and hgh power densty s analysed. Thanks to ts ncreased control degrees of freedom, versatle modes of operaton can be establshed for the UNI-AC. Further, the law of operaton and the performance analyss for each mode are presented n detals. ode A has the smplest modulaton scheme wth only two swtchng states beng used; however, ts power swtch

10 current stresses, conducton losses and rpple performances are uncompettve compared to other operaton modes. ode s able to reduce the losses sgnfcantly due to ts lower current stresses for swtches and the decreased total swtchng actons. ode C offers mum control flexblty wth both two legs beng modulated ndependently (hgher swtchng losses than mode ). y certan arrangement for the modulatng sgnals, ths mode s able to manpulate the converter average model to be a lnear form wth enhanced global stablty and robustness. The UNI-AC also has a common ground shared by the nput and output ports. Expermental work has been carred out to verfy the feasblty and effectveness of the UNI-AC. REFERENCES [1] F. C.. Trndade, K. V. d. Nascmento, and J. C.. Vera, "Investgaton on Voltage Sags Caused by DG Ant-Islandng Protecton," IEEE Trans. Power Del., vol. 8, pp , Apr., 013. [] J. Y. Chan and J. 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Appl., vol. 7, pp , ay/jun., [19] P., Y. Wang, G. Phlp Adam, D. Hollday, and. W. Wllams, "Three-Phase AC-AC Hexagonal Chopper System Wth Heterodyne odulaton for Power Flow Control Enhancement," IEEE Trans. Power Electron., vol. 30, pp , Oct., 015. Peng ( 16) receved the.sc. and.sc. degree both from the Department of Electrcal Engneerng, Zhejang Unversty, Hangzhou, Chna, n 009 and 01, respectvely. In 015, he receved the Ph.D. degree from Electronc & Electrcal Engneerng Department, Unversty of Strathclyde, Glasgow, U.K., where he s currently workng as a postdoctoral research fellow. Hs research nterests nclude hgh capacty power converters and the networkng of power electroncs unts for power system applcatons. Yhua Hu ( 13-S 15) receved the.s. degree n electrcal motor drves n 003, and the Ph.D. degree n power electroncs and drves n 011, both from Chna Unversty of nng and Technology, Jangsu, Chna. etween 011 and 013, he was wth the College of Electrcal Engneerng, Zhejang Unversty as a Postdoctoral Fellow. etween November 01 and February 013, he was an academc vstng scholar wth the School of Electrcal and Electronc Engneerng, Newcastle Unversty, Newcastle upon Tyne, UK. etween 013 and 015, he worked as a Research Assocate at the power electroncs and motor drve group, the Unversty of Strathclyde. Currently, he s a ecturer at the Department of Electrcal Engneerng and Electroncs, Unversty of verpool (Uo). He has publshed more than 50 peer revewed techncal papers n leadng journals. Hs research nterests nclude PV generaton system, power electroncs converters & control, and electrcal motor drves.