Process Variability Modeling for VLSI Circuit Simulation

Transcription

1 Process Varablty Modelng for VLSI Crcut Smulaton Samar K. Saha SuVolta, Inc., 30 D Knowles Drve, Los Gatos, CA, USA, samar@eee.org ABSTRACT Ths paper presents a systematc methodology to develop statstcal compact MOS models for advanced VLSI crcut smulaton. Process varablty n advanced CMOS technologes mposes a serous challenge for computer-aded VLSI crcut desgn. Therefore, statstcal compact model has become ndspensable for realstc assessment of the mpact of random process varablty on advanced VLSI crcut performance. Ths paper descrbes the major parameter set causng local and global process varablty n nanoscale CMOS devces and presents a methodology to generate smplfed statstcal compact MOS models for VLSI crcut smulaton. Keywords: MOS compact models, process varablty, local varatons, global varatons, modelng process varablty, statstcal compact model. INTRODUCTION In advanced CMOS technologes, process varablty severely mpacts delay and power varablty n VLSI devces, crcuts, and chps [] [6]. Typcally, process varablty ncludes local or ntra-de varablty and global or nter-de varablty [3] [6]. Local varablty s the parametrc fluctuatons between dentcally desgned MOSFETs wthn a short dstance [3] [6]. And, global varablty refers to such fluctuatons between dentcal MOSFETs separated by a longer dstance or fabrcated at dfferent tme [3] [6]. Local varablty s wthn a de, whereas global varablty s from de to de, wafer to wafer, or lot to lot. Global varablty causes a shft n the mean value of senstve desgn parameters ncludng channel length (L), channel wdth (W), layer thckness, resstvty, dopng concentraton (N A ), and body effect (K) [3] [5]. Local varablty ntroduces systematc varablty n patternng and random varablty n patterns [3] [5]. Systematc varablty ncludes the varablty caused by optcal-promty correcton, phase-shft maskng, layoutnduced stran, and well-promty effects. Random varablty ncludes random dscrete dopng (RDD), lneedge roughness (LER), lne-wdth roughness (LWR), nterface roughness, gate-ode thckness (T o ) varaton, poly-slcon granularty, and hgh-k delectrc morphology wth metal gates [3] [5]. Systematc varablty can be addressed through layout desgn and more controlled resoluton-enhancement technques. However, addressng the mpact of random varablty requres nnovatve process and crcut desgn technques and statstcal devce models for accurate analyss of VLSI crcuts [5], [6]. For technology nodes below 90 nm, the mpact of random local varablty on crcut performance s becomng ncreasngly mportant. The mpact of local varablty on yeld n VLSI crcuts such as SRAM necesstates the development of new desgn technques. Hence, accurate characterzaton and modelng of local process varablty for crcut smulatons are mperatve to accurately predct yeld and evaluate the benefts of these new crcut desgn technques. To acheve accurate crcut smulaton results, local varablty must be accurately modeled at the process temperature and voltage condtons that most affect the crcut yeld. Smlarly, global process varablty must, also, be accurately characterzed and modeled to accurately predct across the chp performance fluctuatons n advanced VLSI crcuts. Tradtonally, VLSI crcuts are optmzed usng foundry suppled fed corner models. Due to ncreasng amount of process varablty constrants, a crcut optmzed usng such methodologes s more susceptble to random fluctuatons. Therefore, statstcal desgn methodologes have become ndspensable for modern VLSI crcut desgn. And, statstcal compact model addressng the mpact of both local and global random varablty s crucal for computer-aded desgn and analyss of advanced VLSI crcuts. Statstcal compact models are requred for yeld predcton durng crcut smulatons to mtgate the rsk of yeld loss n advanced VLSI crcuts. The objectve of ths paper s to present a systematc methodology to develop statstcal compact MOS models for accurate desgn and analyss of advanced VLSI crcuts. In order to acheve ths goal, frst of all, the major parameter set causng local and global process varablty s determned. Then the procedure to model the local and global process varablty s descrbed. Fnally, methodology to generate statstcal compact MOS models to account for the mpact of process varablty n VLSI crcuts s presented. CRITICAL DEVICE PARAMETERS In order to generate compact varablty model for crcut smulaton, frst of all, the crtcal devce parameters causng process varablty are determned.. Local Process Varablty Local process varablty or msmatch between dentcally desgned transstors s caused by mcroscopc process that makes every transstor dfferent from ts neghbors. As a result, a devce parameter P can be NSTI-Nanotech 0, ISBN Vol., 0 75

2 consdered as consstng of a fed component P 0 and a randomly varyng component P' resultng n dfferent values of P for closely apart dentcal pared-transstors. The actual msmatch n P between dentcal-pared transstors s defned by Δ P. For a large number of samples, ΔP converges to a Gaussan dstrbuton. Now, f P s the model parameter causng msmatch ΔP between the paredtransstors, then the varance of relatve dran current, I msmatch between pared-transstors s gven by [7]: σ ΔI / I = N = + I I n = σ + ΔP ρ ( ΔP, ΔP ) + where N s the number of randomly varyng devce parameters contrbutng to I msmatch, σ ΔP s the standard devaton n ΔP and ρ ( ΔP, ΔP +) s the correlaton between Δ P and ΔP +. In order to model I msmatch between pared-transstors, we need to compute the randomly varyng devce parameters Δ P. For any regonal compact MOS models, the smplfed epresson for I s gven by [8]: μ eff W VGS VTH V I0 ep ep ; VGS < VTH L nkt kt I W V μ eff Co VGS VTH V ; VGS > VTH L () where I 0, W,, C o, and V TH, are the and subthreshold current, channel wdth, channel length, nversonlayer moblty, gate ode capactance, and threshold voltage, respectvely; V GS and V are gate and dran voltage, respectvely; and n, k, and T are the dealty factor of subthreshold slope, Boltzmann constant, and ambent temperature, respectvely. From (), we fnd that the value of I depends on the V, W, C, μ, V, V. Consderng parameter set { } TH o the msmatch due to process varatons only, ΔP n () represents ΔV TH, ΔW, Δ ΔT o, and Δ μ eff. Agan, V TH can be epressed as V TH = f ( VT 0, K, φs, VBS ), where V BS s the appled bas at the bulk of MOSFETs and V T0 = V TH at V BS = 0; whereas, K and φ S are the body effect coeffcent and channel surface potental, respectvely. Here, V T0 models the msmatch (ΔI ) n I due to the fluctuatons n N A n the nverson regon of MOSFETs; whereas, K models the msmatch n I (V BS ) due to the fluctuatons n N A n the depleton regon under the gate. We know that K = f ( N A, V ) and wth the change n the value of V BS, BS eff GS () the wdth of the depleton layer under the gate changes. As a result, the amount of bulk charge, qn A changes wth the changes n V BS as shown n Fg. for a graded-retrograde (GR) channel dopng profle [9]; where q s the electronc charge. Thus, the fluctuatons n the vertcal channel dopng under the gate due to process varablty contrbute to the msmatch n I (V BS ). Hence, I (V BS ) msmatch between dentcal pared-transstors due to fluctuatons n the vertcal channel dopng concentraton must be modeled by K. Thus, the set of major devce parameters contrbutng to the msmatch between dentcally desgned transstors wthn a chp s { VT 0, W, μ eff, K}. Here, ΔVT0 models ΔI due to RDD, ΔW and ΔL models ΔI due to LER and LWR, ΔT o models ΔI due to ode thckness fluctuatons, Δμ eff models ΔI due to moblty fluctuatons caused by surface roughness and remote roughness scatterng, and K models ΔI due to fluctuatons n the vertcal channel dopng concentraton. Therefore, n order to model msmatch n VLSI crcuts, the fluctuatons n the crtcal devce parameters due to mcroscopc process varatons must be modeled accurately. Channel Dopng Concentraton (cm -3 ).E+9.E+8.E+7.E+6 d d d Depth n Slcon (nm) Fg.. A typcal MOSFET channel dopng profle from the slcon/slcon-dode nterface at depth = 0 nto the substrate; d, d, and d3 are the depleton wdth due to the appled bas V BS, V BS, and V BS3, respectvely causng V TH (V BS ) varatons due to the fluctuatons n vertcal N A.. Global Process Varablty BS BS3 BS BS3 Global process varablty s caused by non-unform processng temperature as well as fluctuatons of mplant doses across wafers and relatve locaton of devces. The global varaton shfts the average value of devce performance. From (), the global fluctuatons, ΔI can be descrbed by the parameter set { VTH, W, T o, μeff }. In addton, ΔI due to the fluctuatons n the source-dran (S/D) mplant dose across wafers can be modeled by varatons n the S/D seres resstance, R. d d d 3 where V < V BS BS < V 75 NSTI-Nanotech 0, ISBN Vol., 0

3 Agan, the gate delay, τ pd C load, where C load s the load capactance. Therefore, for accurate smulaton of dgtal crcuts, across the chp fluctuatons n MOSFET gate capactance (C g ) along wth that n S/D juncton capactance (C J ) must be accurately modeled. The fluctuaton n C g s modeled by fluctuatons n the gate overlap capactance (C ov ) whereas, that n C J s modeled by the area as well as S/D sdewall capactances. For eample, n BSIM4 compact MOS model, the fluctuatons n the transent performance can be prmarly descrbed by the parameter set { } ov C J C,. Therefore, the set of major model parameters to account for the global varablty n MOSFET V, W, T, μ, C, C. devces s { } TH o eff 3 CORNER MODEL PARAMETERS 3. Local Component In secton., we have descrbed the randomly varable set of devce parameters causng msmatch between dentcally desgned transstors as { VT 0, W, μ eff, K}. The correspondng BSIM4 MOS model parameters are { VT 0, XW, X U 0, K} [0]; where, XW and XL are the channel wdth and length offset parameters due to maskng and photolthography, respectvely and account for the msmatch due to LER and LWR; whereas, U0 and K accounts for the fluctuatons n μ eff and N A wth V BS, respectvely. The msmatch, ΔP, msmatch s descrbed by standard normal dstrbutons, N ( 0, σ ) where the varance, σ for each varable s calculated from a large number of samples usng Pelgrom s law [] and s descrbed by σ ΔP AP / WL where A P s a process dependent constant. For eample, the varance n VT0 s gven by: A vt σ Δ VT 0 (3) WL Typcally, msmatch ΔVT0, ΔXW, ΔX ΔT o, ΔU0, and ΔK are represented by standard normal dstrbutons N(0,). Therefore, we can show: Δ P, msmatch = σ Δ N(0,) (4) P In (4), ΔP, msmatch represents fluctuatons n P due to local process varablty and s computed usng Monte Carlo (MC) smulaton for a large number of samples. 3. Global Component In secton., we have descrbed the crtcal set of devce parameters { V TH, XW, X T o, μ eff, C ov, C j } causng global process varablty. The correspondng set of BSIM4 model parameters s {VT0, XW, X TOX, U0, K, RW, CGSO, CGDO, CGS CGD CJS, CJD, CJSWS, CJSWD, ov j CJSWGS, CJSWGD}. Here, {CGSO, CGDO, CGS CGDL} defnes C ov ; {CJS, CJD} defnes S/D juncton area capactance; and {CJSWS, CJSWD, CJSWGS, CJSWGD} defnes S/D juncton sdewall capactance. For MC statstcal modelng, the global varance, ΔP, global s, also, descrbed by normal dstrbuton, N ( 0, σ). Typcally, σ 3 and s etracted from the statstcal dstrbutons of electrcal test (ET) data for P measured from multple des, wafers, and lots over a perod of tme [5]. The varance n model parameter P due to global process varablty can be modeled by: σ. N(0, 3); for MC corner model ΔP, global (5) σ ; for fed corner model In (5), Δ represents the fluctuatons n P due to P, global global process varablty. Thus, the model parameter P due to both local and global process varablty s gven by: = P + ΔP + P (6) P 0, msmatch Δ, global where, P 0 s the value of the nomnal model parameter and s etracted from the golden de of the golden wafer that represents the target devce specfcatons of the target technology. 3.3 Corner Parameter Etracton The local and global components of ΔP gven by (4) and (5), respectvely are etracted from ET data as shown n Fg.. Target VLSI Technology I V / C V Model Etractons I V / C V / ET Data Collecton (multple de, wafers, lots) Statstcal Dstrbutons and Computaton of ΔP, A, σ Generate Fnal Model Map ET data SPICE Parameter Smulaton Fg.. Basc approach for statstcal compact modelng. The database ncludes electrcal devce characterstcs and producton ET data. (The bell-shaped curve represents a typcal ET data dstrbuton). In the basc modelng approach, ET data are collected from multple devces, wafers, and lots over a long perod of tme. I V and C V characterstcs can be used to NSTI-Nanotech 0, ISBN Vol., 0 753

4 etract corner model parameters. However, ths approach s tme-consumng and therefore, ET data are, typcally, used to generate statstcal models. In the case of a new technology generaton, the producton data for statstcal modelng s lmted; therefore, systematc technology CAD (TCAD)-based process varablty data can be generated for statstcal corner modelng [] [5]. 4 MODEL GENERATION 4. MC Statstcal Model Equaton (6) s used to generate the corner models of the target technology. For MC statstcal corner modelng, normal dstrbuton s used to determne the value of σ for each randomly varyng parameter descrbed n secton 3. From the statstcal dstrbuton of ET data, 3 σ value s used to account for across the chp varatons; whereas, σ value s used for msmatch modelng. Fnally, (6) s mplemented to generate corner models to smulate process varablty of the target CMOS technology. Fg. 3 shows the random dstrbutons of NMOS and PMOS VT0 and I AT data obtaned around ther respectve typcal (TT) values as obtaned by MC statstcal model. (a) 4. Fed Corner wth Msmatch Model The MC smulaton usng both local and global random varables, descrbed n secton 3, s computatonally ntensve for advanced VLSI crcut smulaton. Therefore, fed corner models along wth MC msmatch model can be effcently used to analyze the advanced VLSI crcuts. MC msmatch addresses the stochastc varatons between pared-transstors; whereas, fed corner model wth approprate value of σ can be used to address across the chp varatons at the lower and upper boundares [5]. Equaton (6) s used to generate the fed corner parameters of the target technology. A fed value of 3 σ 6 s used to account for global process varablty. The MC msmatch s performed at the upper and boundares of fed corner model [5] as shown n Fg CONCLUSION Process varablty n advanced CMOS technologes mposes a serous challenge to advanced VLSI crcut desgn. Therefore, statstcal corner models are etremely mportant for realstcally assessng how process varablty mpacts crcut performance. In ths work, we have generated statstcal models and used them n rudmentary dgtal-crcut analyss to nvestgate delay varaton n response to process varablty. The smulaton data shows that ths statstcal-modelng approach enables realstc predcton of the standard devatons of crcut performance and allows for trackng crcut performance due to process varablty by montorng ET data. (b) Fg. 3. Producton data dstrbuton, along wth smulaton data generated from the correspondng statstcal MOSFET models: (a) V TNLIN vs. V TPLIN and (b) I DNSAT vs. I DPSAT. The models approprately nclude the spread n electrcal test ET data due to process varablty; TT represents typcal values of NMOS and PMOS model parameters. σ Msmatch σ Msmatch SS TT FF Fg. 4. Msmatch smulaton around SS and FF corners to account for random process varablty usng fed corner models; SS denotes slow NMOS and slow PMOS devces; FF represents fast NMOS and fast PMOS devces. 754 NSTI-Nanotech 0, ISBN Vol., 0

5 REFERENCES. S. Saha, Desgn consderatons for 5 nm MOSFET devces, Sold-State Electron., vol. 45, no. 0, pp , Oct S. Saha, Scalng consderatons for hgh performance 5 nm metal-ode-semconductor feld-effect transstors, J. Vac. Sc. Tech. B, vol. 9, no. 6, pp , Nov K. Bernsten et al., "Hgh-performance CMOS varablty n the 65-nm regme and beyond," IBM J. Res & Dev. vol. 50, no. 4/5, pp , K. Kuhn et al., Managng vrocess varaton n ntel s 45nm CMOS technology, Intel Technology J., vol., no., pp. 9-0, S.K. Saha, Modelng process varablty n scaled CMOS technology, IEEE Desgn & Test of Computers, vol. 7, no., pp. 8-6, Mar./Apr S.K. Sprnger et al., Modelng of varaton n submcrometer CMOS ULSI technologes, IEEE Trans. Electron Devces, vol. 53, no. 9, pp , Sep J.A. Croon, W. Sansen, and H.E. Maes, Matchng propertes of deep sub-mcron MOS transstors, Sprnger: The Netherlands, N.D. Arora, MOSFET models for VLSI crcut smulaton: Theory and practce, Sprnger Verlag: Wen, S. Saha, Effects of nverson layer quantzaton on channel profle engneerng for nmosfets wth 0. μm channel lengths, Sold-State Electron., vol. 4, no., pp , Nov t.html.. M.J.M. Pelgrom, A.C.J. Dunmajer, and A.P.G. Welbers, Matchng propertes of MOS transstors, IEEE J. Sold-State Crcuts, vol. 4, pp , Oct S.K. Saha, Managng technology CAD for compettve advantage: An effcent approach for ntegrated crcut fabrcaton technology development, IEEE Trans. Eng. Manage., vol. 46, no., pp. -9, May S.K. Saha, Modellng the effectveness of computeraded development projects n the semconductor ndustry, Int. J. Engneerng Management and Economcs, vol., no. /3, pp S. Saha, Etracton of substrate current model parameters from devce smulaton, Sold State Electroncs, vol. 37, no. 0, pp , Oct S. Saha, C.S. Yeh, and B. Gadepally, Impact onzaton rate of electrons for accurate smulaton of substrate current n submcron devces, Sold-State Electron., vol. 36, no. 0, pp , Oct NSTI-Nanotech 0, ISBN Vol., 0 755