DUE TO process scaling, the number of devices on a

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1 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 11, NOVEMBER Latency Inserton Method (LIM) for DC Analyss of Power Supply Networks Dmtr Klokotov, Patrck Goh, and José E. Schutt-Ané, Fellow, IEEE Abstract Process scalng n modern ntegrated crcuts has led to multple sgnal and power ntegrty ssues. In partcular, ensurng relable performance of on-chp power delvery systems has become a major desgn challenge. Rgorous analyss and smulatons are requred at the desgn stage to ensure proper functonalty of an on-chp power supply. Ths puts a stran on exstng numercal tools due to the sheer sze of the power grds. In ths paper, a fast crcut smulaton technque based on the latency nserton method (LIM) s proposed for the steady-state analyss of large-scale crcuts, such as on-chp power dstrbuton network. The proposed method s shown to be very effcent for modelng of networks wth very large numbers of nodes. The comparson wth one of the well establshed methods used for the power grd analyss today, the Random Walk algorthm, shows that LIM s almost two orders of magntude faster. Index Terms DC analyss, IR-drop, latency nserton, latency nserton method, power dstrbuton network, power ntegrty, power supply. I. INTRODUCTION DUE TO process scalng, the number of devces on a chp has ncreased dramatcally. Consequently, modern on-chp power dstrbuton networks (PDNs) are requred to carry very large amounts of supply current. At the same tme, power dsspaton ssues n hgh-performance, hgh frequency devces are forcng the use of lower supply voltages [1]. Also, as nterconnects become narrower, wre resstances ncrease. As a result, large amounts of current are dstrbuted through large-scale power grds wth narrow nterconnects at low voltages, whch causes sgnfcant voltage drop (IR drop) on the grd, serously compromsng the performance of the chp. Therefore, effcent and accurate analyss of the IR drop n the power grd becomes one of the crucal steps n the desgn process. Due to the extremely large sze of the contemporary power grds, ther analyss wth tradtonal technques becomes computatonally neffcent or even mpossble because of prolonged runtmes and excessve memory requrements. A number of methods have been proposed to address the szebased complexty of the problem. For example, herarchcal analyss technque [] manages the complexty by solvng local grds separately, but ths can compromse accuracy. Manuscrpt receved December 16, 0; revsed May 19, 011; accepted July 15, 011. Date of publcaton September 6, 011; date of current verson November 8, 011. Recommended for publcaton by Assocate Edtor M. Nakhla upon evaluaton of the revewers comments. The authors are wth the Department of Electrcal and Computer Engneerng, Unversty of Illnos at Urbana-Champagn, Urbana, IL USA (e-mal: dklokot@llnos.edu; pgoh@llnos.edu; jschutt@emlab.uuc.edu). Color versons of one or more of the fgures n ths paper are avalable onlne at Dgtal Object Identfer.19/TCPMT /$ IEEE Another approach [3] employs a grd-reducton scheme by solvng several coarsened grds and then extrapolatng the results to the orgnal fne-gran grd. Therefore, the method n [3] solves the network approxmately and thus suffers from errors. The statstcal Random Walk method [4] guarantees a lnear runtme and the avalablty of memory, but becomes neffcent when voltages at all the nodes have to be computed or when there s a need for hgh accuracy. The node-based teratve scheme [5] n effect mplements the classcal successve over relaxaton teratve method for solvng lnear systems. The node-based method s effcent for steady-state analyss but not easly extendable nto transent analyss. There also exst a number of technques based on the conjugate gradent method [6], [7]. These methods demonstrate a lot of promse, but, as well as the node-based method n [5], are only appled to DC problems. In the desgn process of a PDN both types of analyses (statc and dynamc) must be employed. Therefore, a method beng proposed as an alternatve to the ndustrystandard drect solvers (such as SPICE) must delver smlar general-purpose capabltes. Ths paper presents an applcaton of the latency nserton method (LIM) to the analyss of the steady-state PDN. The LIM was ntally proposed as a transent smulaton technque to effcently model large networks [8]. The method s based on the fnte-dfference formulaton smlar to the one used by the well-known fnte-dfference tme-doman method (FDTD) [9]. Whle FDTD solves the tme-doman equatons for electrc and magnetc felds, LIM apples the same fnte-dfference technque to crcut equatons for voltages and currents. LIM s meant to be an alternatve to the tradtonal matrx vector product-based crcut smulators such as SPICE, and s targeted prmarly at the smulaton of very large unform networks, whch makes t partcularly sutable for modelng of on-chp power supply. LIM teratvely solves crcut equatons usng a tme-steppng scheme, therefore, t avods constructon and computaton of a large matrx (as opposed to SPICE). The method demonstrates lnear numercal complexty, enables analyss of very large networks, and greatly outperforms conventonal matrx-based methods. In ths paper, t s demonstrated that the LIM, an effcent transent method, can be successfully used for the DC part of the on-chp power supply analyss. For the problem of large crcut DC smulaton, the method s compared to one of the well-establshed technques the Random Walk algorthm [4]. The Random Walk method s an teratve algorthm based on a statstcal solver. The comparson between the two methods shows that LIM sgnfcantly outperforms the Random Walk method both n terms of speed and accuracy.

2 1840 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 11, NOVEMBER 011 The rest of ths paper s organzed as follows. In Secton II, the formulaton of the LIM method s descrbed. Sectons III and IV demonstrate the applcaton of the LIM method to the DC analyss of the PDN. In Secton V smulaton results are presented and benchmark comparson between the LIM and the Random Walk method s made. Fnally, n Secton VI, the conclusons are reported. Fg. 1. R j L j E j V + I j LIM branch equvalent crcut. V j II. LIM FORMULATION LIM treats a crcut as a grd composed of nodes nterconnected wth branches. The approach s based on utlzng an equvalent model for crcut nterconnects (dstrbuted RLGC-based transmsson lne model). The RLGC equvalent crcut representaton of ntegrated crcut nterconnects can be obtaned by runnng a layout extracton procedure n a computer aded desgn tool used n the desgn process. Each branch (a secton of an nterconnect) can be represented by a dstrbuted seres resstor nductor model as a combnaton of a voltage source, an nductor, and a resstor n seres (as shown n Fg. 1). Current I j sassumedtobe drected from node at voltage V to node j at potental V j. Each node s modeled as a combnaton of a current source, a conductance, and a capactor to the ground (as n Fg. ). Usng the Krchhoff s voltage law for the crcut n Fg. 1 the dscrete tme equaton can be wrtten as ( ) ( ) I n+1 j I n+1 j + R j V n+1/ V n+1/ j = L j I n j + I n j E n+1/ j. (1) Superscrpts n (1) represent the dscrete tme. Currents are computed at whole tme ntervals t = n voltages at half ntervals t = (n + 1/),where s the tme step. Ths way voltages and currents are staggered by half a tme step. Ths s known as the leapfrog scheme or sem-mplct scheme [9]. Soluton of the dscrete tme (1) for the branch equvalent crcut n Fg. 1 yelds the followng expresson for branch currents: ( ) V n+1/ Ij n+1 V n+1/ ( j = ( Lj + R ) + I j n Lj R ) ( ). () Lj + R Usng the Krchhoff s current law for the LIM node equvalent crcut n Fg. the dscrete tme equaton can be wrtten as ( n+1/ V V n 1/ ) C M ( n+1/ V + G + V n 1/ ) H n = I k (3) V n+1/ k=1 where M s the total number of branches connected to node. Soluton of (3) yelds the expresson for node voltages ( ) M = V n 1/ (C G ) (C + G ) k=1 Ik n H n (C + G ). (4) Fg.. V I k LIM node equvalent crcut. I 3 I I1 G C H If the crcut model does not nclude shunt node conductance G (whch, as we wll show further, s the case for the power supply network model), expresson n (4) can be smplfed to V n+1/ = V n 1/ C ( Na k=1 Ik n H n ). (5) In the LIM transent smulaton, node voltages and branch currents are computed at each tme step usng the update expressons () and (4). Frst all node voltages are calculated through (4) next, all branch currents are updated through (). As t can be seen from () and (5), the presence of latency generated by the reactve elements L j and C s requred for the algorthm to functon. If the reactve elements are not present n the crcut, small fcttous nductors must be nserted n each branch and capactors must be added at every node to enable LIM formulaton. It can be shown that f the values of those fcttous elements are small enough, the accuracy of the transent smulaton s not compromsed [8]. The LIM algorthm uses central dfference-based fntedfference approxmaton, whch s condtonally stable. In the smple 1-D case (no more than two branches connected at each node) the condton for the numercal stablty of the method can be wrtten as [8], [] < N b ( mn L mn(c, C +1 )) =1 where N b s the number of branches n the network, L s the nductance of the branch, C,andC +1 are shunt capactors connected on ether sde of the branch. Condton (6) s analogous to the Courant crteron for wave propagaton n a dscrete grd [11], that s used to determne the lmt on the tme step n the FDTD method. In the FDTD method the lmt on the tme step s based on the fact that numercal waves n a computatonal space cannot propagate faster than the speed of lght. The same dea apples to the LIM, the speed of sgnal propagaton s lmted by the latency present n the crcut. However, n the case when there are more than two branches (6)

3 KLOKOTOV et al.: LATENCY INSERTION METHOD FOR DC ANALYSIS OF POWER SUPPLY NETWORKS 1841 A 0.3 A 1 1 B 1 C 4 D A 0.05 A 0.05 A Fg. 3. network. Equvalent crcut model for a part of an on-chp power supply Fg. 5. Smple crcut example. Fg. 4. Crcut model for a steady-state PDN. connected at a sngle node, the problem of determnng the stable smulaton tme step s not as straghtforward. Agan usng the analogy wth the FDTD method, we note that the lmt on the tme step reduces as the dmenson of the computatonal space ncreases. The same dea apples to the LIM. However, n the LIM model network the number of connectons at a sngle node s not lmted to tree, and the noton of dmenson n such a model does not have a clear physcal meanng (as opposed to the FDTD case). The problem of fndng a sutable value for the tme step of the smulaton s further dscussed n Secton IV. III. ON-CHIP PDN A typcal power grd model conssts of wre resstances, wre nductances, wre capactances, decouplng capactors, pads, and current sources that represent currents drawn by logc gates or functonal blocks [4]. The equvalent model for a part of PDN s shown n Fg. 3. The model n Fg. 3 s somewhat smplfed and can be vewed as the representaton of a sngle layer of power lnes wth only lne-to-ground capactance taken nto account. Analyss of a PDN s often done n two steps. The steadystate (DC) soluton s found frst and then the transent analyss s performed. The transent smulaton s naturally carred out usng the standard LIM formulaton [8], [1] [14]. In ths paper, we focus on the frst stage, the problem of computng the steady-state node voltages, the DC soluton. Due to the sheer sze of contemporary PDNs even the ntal DC analyss becomes a challengng problem that s not sutable for drect solvers and requres the use of alternatve more effcent algorthms [4], [5]. We show that the LIM, whle beng prmarly a transent smulaton technque, can be effcently appled to the DC steady-state analyss problem. A transent smulaton n the network that contans only constant current and voltage sources rapdly converges to the steady-state voltage and current values. In the steady state all capactors are open crcuted and nductors are short crcuted. The model n Fg. 3 then smplfes to the one shown n Fg. 4. The power grd s then represented as a network of purely resstve branches and nodes of two types: constant voltage sources ( pads) and constant current sources. IV. STEADY-STATE PDN ANALYSIS USING LIM In order to show how LIM can be appled to the DC analyss of a power grd, we use a smple crcut example [4]. Fg. 5 shows a smple crcut that represents a small secton of a PDN. If the supply voltage s chosen to be 1 V, the voltages at nodes A, B, C, and D can be easly calculated: 0.6, 0.8, 0.7, and 0.9 V respectvely. A. Enablng LIM Formulaton: Latency Inserton The DC PDN model does not contan latency. In order to enable the LIM formulaton for the crcut n Fg. 5, latency elements must be nserted n all the branches and at all the nodes. The resultng LIM-enabled augmented crcut correspondng to Fg. 5 s shown n Fg. 6. Snce the nserton elements are fcttous, they must be made as small as possble, so that the accuracy of the soluton s not compromsed. In general, the values of the fcttous reactve elements are chosen to be much smaller than those of the actual nductances and capactances present n the crcut. On the other hand, the choce of the values for fcttous reactve elements affects the stablty for the smulaton. In a

4 P(A) 184 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 11, NOVEMBER 011 V 1 L 1 L DD B C 0 90 C 0.1 A C 0.05 A Fg. 6. Augmented secton of the example crcut from Fg. 5 wth fcttous latency elements n place Stable regon = Unstable regon = Fg. 7. Spectral radus of the amplfcaton matrx A as a functon of the tme step. transent LIM smulaton values of the reactve elements determne the lmt on the maxmum possble tme step of the smulaton. Therefore, t s desrable to have a lot of latency n the crcut that wll allow usng the largest tme step and hence, achevng the shortest runtme. However, n the case of DC analyss the actual values of the nserton elements are not mportant snce only steady-state voltages are computed and not transent waveforms. Therefore, the values of nserton elements can be chosen arbtrarly. Consderatons nvolved n the choce of the optmum tme step are dscussed n some detal further. B. Choosng the Tme Step of the LIM Smulaton In the case of the DC analyss wth an teratve method the duraton of the smulaton s determned by the number of teratons requred for the soluton to converge to the steadystate values. In our case, snce the smulaton s actually transent, there s stll the ssue of choosng the approprate ncrement for the tme step. Frst of all, the must be chosen so that the smulaton remans stable, also a fast rate of convergence s desrable. The exact lmt on the tme step of the LIM smulaton can be found usng the amplfcaton matrx approach [15], [16]. The amplfcaton matrx approach s based on transformng the LIM update equatons nto the matrx form, such that voltage and current vector values at the next tme step are found by multplyng the values from the prevous step wth the matrx A, the amplfcaton matrx. That matrx depends on the structure of the network and the tme step value. Accordng Number of steps Fg = Convergence of the LIM smulaton as a functon of the tme step. to the method n [15] the tme step of the smulaton must be chosen so that the spectral radus of the amplfcaton matrx s less than or equal to unty. If any of the egenvalues of the matrx A exceeds 1, the soluton wll grow uncontrollably. Fg. 7 shows the dependence of the spectral radus of the amplfcaton matrx for the crcut n Fg. 5 on the value of the tme step. It can be seen n Fg. 7 that the system becomes unstable as the value of the tme step exceeds = Whle the amplfcaton matrx approach can produce the exact lmt on the tme step, t s not always convenent to derve the matrx and solve for ts egenvalues. In [1] and [17] the upper bound on the tme step of the transent LIM smulaton was derved usng the drect Lyapunov method (also known as the energy method). In the case when more than two branches are connected to a sngle node the stablty condton can be wrtten as N n mn C =1 N b N b mn p=1 (L,p) (7) where N n s the total number of nodes n the crcut, C s the shunt capactance at node, Nb denotes the number of branches connected to node, L,p denotes the value of pth nductor connected to node. The result of (7) s the square root of the smallest L,p, C product among all the nodes of the crcut dvded by the number of connectons at the node. In 1-D case (7) becomes (6). The lmt n (7) s easy to obtan n the process of parsng a crcut netlst. Condton n (7) s only a suffcent one. If the tme step exceeds the lmt gven by (7), the smulaton does not necessarly become unstable. Condton (7) can be used for the calculaton of the tme step for the steady-state PDN smulaton. As was mentoned before, n the DC case actual values of the fcttous latency elements are not relevant. Therefore, for smplcty and convenence all nserton elements throughout the crcut can be assgned to a value of unty. Then, usng (7), we can wrte the expresson

5 KLOKOTOV et al.: LATENCY INSERTION METHOD FOR DC ANALYSIS OF POWER SUPPLY NETWORKS 1843 Voltage, (V) Estmated voltage at Node A Actual voltage at Node A TABLE II RUNTIME RESULTS FOR LARGE CIRCUITS Number of Nodes LIM (CPU seconds) Random Walk (CPU seconds) K <1 50 K K M M 8 58 Fg Number of steps Convergence of the smulaton usng the LIM algorthm. TABLE I LIM RESULTS FOR THE BASIC CIRCUIT Nodes Estmated Voltage (V) Actual Voltage (V) A B C D for the tme step as = N n max =1 ( ). (8) N b It can be demonstrated usng the crcut n Fg. 4 that the tme step resultng from (8) s stable and closely approxmates the optmum step for fastest convergence. Node C n the crcut has the hghest number of connectons Nb C = 3 then, from (8) the tme step for the crcut s = From Fg. 7 t can be seen that the tme step from (8) s n the stable regon. It s also desrable to use the tme step that results n the fast convergence of the smulaton. The smulaton starts wth zero ntal condtons and then converges to a certan DC voltage level. Larger tme step results n larger ncrements of voltage values at each step of the smulaton. Therefore, n general, a larger tme step allows the smulaton to reach the steady-state voltage value n fewer teratons. However, f the tme step s too close to the stablty lmt, voltages oscllate around ther steady-state values, whch results n prolonged run tmes. The trend s shown n Fg. 8. Frst, as the tme step ncreases, the number of teratons requred for convergence decreases. Then, as the value of approaches 0.9, there s a steep ncrease n the number of steps requred for convergence. The value of predcted by (8) results n the near optmum number of 17 teratons requred for voltages at all nodes of the crcut example to converge. C. Numercal Smulaton Results for the Basc Crcut After latency s created and the tme step s determned, the augmented crcut can be smulated wth LIM. Table I shows the smulaton results for the crcut n Fg. 5. Estmated voltage at the node, (V) Fg.. Estmated voltage at Node A Actual voltage at Node A Number of walks from the node Convergence of the Random Walk algorthm It took only 17 teratons to acheve the relatve error on the order of 0.001%. Fg. 9 shows the convergence of the smulaton for a sngle node of the basc crcut. From Fg. 9 t can be seen that the LIM smulaton quckly reaches the correct steady-state value of the node voltage and stays stable at that value. For the comparson, the same example was smulated usng the Random Walk algorthm. In Fg. the convergence of the smulaton performed usng the Random Walk algorthm s shown. Fg. demonstrates that t s relatvely harder to obtan hgh-precson soluton usng the Random Walk algorthm due to the random nature of the method. Random Walk method s based on the statstcal approach the random walk game. The soluton converges to the correct value as more walks are taken from the node, and the results are averaged over a large number of teratons. However, even after a large number of walks the soluton stll oscllates consderably. V. NUMERICAL RESULTS OF THE DC POWER GRID ANALYSIS As was mentoned above, the man advantage of the teratve technques n general and LIM n partcular s the ablty to effcently analyze the networks wth very large numbers of nodes that are not sutable for matrx-based technques (such as SPICE). Several large crcuts were smulated usng LIM and Random Walk methods. All crcuts used for smulaton had the form of resstve grds wth constant voltage ( ) sources and constant current sources (power drans), smlar to the model n Fg. 4. Runtme results are summarzed and compared n Table II. Runtmes as functons of the number of

6 1844 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 11, NOVEMBER 011 CPU seconds Fg Number of nodes Runtme as a functon of the number of nodes Random walk LIM Fg. 1. Voltage drop profle (on the left) and the correspondng error profle (on the rght) for a K crcut. Color scale on the voltage drop plot corresponds to the percent dfference from the supply voltage. Color scale on the error profle plot shows smple dfference between the LIM smulaton values and the ones produced by the HSPICE. nodes n the crcut are also shown n Fg. 11 on a sem-log scale. Table II can be extrapolated as both algorthms have lnear numercal complexty and runtmes scale nearly lnearly. All computatons were carred out on a Wndows workstaton wth.4 GHz CPU and GB of RAM. In the above smulatons, the error margn was set to 1 mv. It s possble to reduce the runtme of the Random Walk method f hgh accuracy s not requred or f only a few node voltages need to be computed. Otherwse, the LIM method demonstrates almost two orders of magntude speedup over the conventonal Random Walk algorthm. In the Random Walk method, the varance s used as the measure of convergence of a node voltage [4]. LIM s not a statstcal method and does not nvolve random number generaton. In the LIM program convergence s clamed when the dfference between the new voltage value and the old one does not exceed a certan error margn (user specfed). Normally the smulaton runs untl the voltage values at all nodes stay wthn the error margn. A sgnfcant speedup can be acheved f the nodes at whch the convergence s regstered are removed from the computaton. Such nodes are assgned some specal untouchable type values and are not processed any more. A smulaton s stopped once there are no more nodes left to process. There s a certan error ntroduced every tme a node s consdered converged and voltage at that node s fxed However, the error can be kept small. Fg. 1 demonstrates the error values for the K node crcut (wth HSPICE smulaton results treated as exact) produced by the LIM smulaton. The largest error s stll less than 1.7 mv. Wth modfcatons the LIM smulaton of a crcut wth 500 K nodes can be reduced to CPU seconds, whle t takes 509 CPU seconds wth the Random Walk method. The crcut has a favorable structure (large number of supply nodes), but t s favorable for both the LIM and the Random Walk method (as well as for any other teratve method). VI. CONCLUSION The LIM was appled to the analyss of steady-state onchp PDNs. Despte beng ntally developed as a purely transent technque, the method was shown to be an effcent tool for the DC analyss of PDNs. Therefore, the complete analyss of a PDN (both DC and transent) can be carred out usng a sngle method. The LIM algorthm exhbts fast convergence, hgh accuracy, and short runtme. The algorthm has lnear numercal complexty and s sutable for the analyss of very large networks. Expermental results show that LIM sgnfcantly outperforms the conventonal Random Walk method, partcularly for crcuts wth very large numbers of nodes. REFERENCES [1] M. K. Govan, L. L. Bro, and D. B. Jackson, Power consderatons n the desgn of the alpha 164 mcroprocessor, n Proc. 35th Des. Autom. Conf., Jun. 1998, pp [] M. Zhao, R. V. Panda, S. S. Spatnekar, and D. Blaauw, Herarchcal analyss of power dstrbuton networks, IEEE Trans. Comput.-Ad. Des. Integr. Crcuts, vol. 4, no. 5, pp , Aug [3] J. Kozhaya, S. R. Nassf, and F. N. Najm, A multgrd-lke technque for power grd analyss, IEEE Trans. Comput.-Aded Des. Integr. Crcut, vol. 1, no., pp , Oct. 00. [4] H. Qan, S. R. Nassf, and S. S. Sapatnekar, Random walks n a supply network, n Proc. 40th Des. Autom. Conf., Jun. 003, pp [5] Y. Zhong and M. D. Wong, Fast algorthms for IR drop analyss n large power grd, n Proc. Int. Conf. Comput.-Ad. Des., 005, pp [6] J. Xe and M. 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7 KLOKOTOV et al.: LATENCY INSERTION METHOD FOR DC ANALYSIS OF POWER SUPPLY NETWORKS 1845 [16] P. Goh, J. E. Schutt-Ane, D. Klokotov, J. Tan, P. Lu, W. Da, and F. Al-Hawar, Parttoned latency nserton method (PLIM) wth stablty consderatons, n Proc. IEEE 15th Workshop Sgnal Propagat. Interconn., May 011, pp [17] S. Lalgud and M. Swamnathan, Analtcal stablty condton of the latency nserton method for nonunform GLC crcuts, IEEE Trans. Crcuts Syst., vol. 55, no. 9, pp , Sep Dmtr Klokotov receved the B.S. degree n physcs from Saratov State Unversty, Saratov, Russa, n 001, and the M.S. degree n electrcal and computer engneerng from the Unversty of Illnos at Urbana-Champagn, Urbana, n 007. He s currently pursung the Ph.D. degree n the same unversty. Hs current research nterests nclude numercal methods, computatonal electromagnetcs, crcut smulaton, nterconnect analyss, and sgnal and power ntegrty. José E. Schutt-Ané (S 86 M 86 SM 98 F 07) receved the B.S. degree n electrcal engneerng from the Massachusetts Insttute of Technology, Cambrdge, n 1981, and the M.S. and Ph.D. degrees from the Unversty of Illnos at Urbana-Champagn (UIUC), Urbana, n 1984 and 1988, respectvely. He joned Hewlett-Packard Technology Center, Santa Rosa, CA, as an Applcaton Engneer, nvolved wth mcrowave transstors and hghfrequency crcuts. In 1983, he joned UIUC and then joned the Electrcal and Computer Engneerng Department as a member of the Electromagnetcs and Coordnated Scence Laboratores, where he currently specalzes n the study of sgnal ntegrty for hgh-speed dgtal and hgh frequency applcatons. He has been a Consultant for several corporatons. Hs current research nterests span the spectrum from mcrowave measurements to the generaton of computer-aded desgn tools for electronc systems. Dr. Schutt-Ané has been a recpent of several research awards ncludng the Natonal Scence Foundaton (NSF) Magnetc Resonance Imagng Award n 1991, the Natonal Aeronautcs and Space Admnstraton Faculty Award for Research n 199, the NSF Marne Corps Avaton Assocaton Award n 1996, and the UIUC-Natonal Center for Superconductng Applcatons Faculty Fellow Award n 000. Patrck Goh receved the B.S. and M.S. degrees n electrcal engneerng from the Unversty of Illnos at Urbana-Champagn (UIUC), Urbana, n 007 and 009, respectvely, where he s currently pursung the Ph.D. degree. He has been a Teachng Assstant wth the Department of Electrcal and Computer Engneerng, UIUC, snce August 007. Hs current research nterests nclude crcut smulaton for hgh-speed nterconnects, modelng, and computer-aded desgn tools. Mr. Goh was a recpent of the H. L. Olesen Award from UIUC for outstandng effort n undergraduate teachng n 0.