Methods for True Power Minimization

Transcription

1 Methods or True Power Mnmzaton Robert. Brodersen, Mark A. Horowtz 2, Dejan Markovc, Borvoje Nkolc, Vladmr Stojanovc 2 Unversty o Calorna, Berkeley; 2 Stanord Unversty Abstract Ths paper presents methods or ecent power mnmzaton at crcut and mcro-archtectural levels. The potental savngs are strongly related to the prole o a crcut. These savngs are obtaned by usng gate szng, supply voltage, and threshold voltage optmzaton, to mnmze consumpton subject to a delay constrant. The true power mnmzaton s acheved when the reducton potentals o all tunng varables are balanced. e derve the senstvty o to delay or each o the tunng varables connectng ts savng potental to the physcal propertes o the crcut. Ths helps to develop understandng o optmzaton perormance and denty the most ecent technques or reducton. The optmzatons are appled to some examples that span typcal crcut topologes ncludng nverter chans, SRAM decoders, and adders. At a delay o 2% larger than the mnmum, savngs o 4% to 7% are possble, ndcatng that achevng peak perormance s expensve n terms o. Energy savngs o about 5% can be acheved wthout delay penalty wth the balancng o szes, supples, and thresholds.. Motvaton Durng the past ew years the nature o ntegrated crcut desgn has slowly changed; the contnued scalng o the underlyng technology has moved desgns rom beng lmted by the amount o unctonalty on a chp, to beng powerconstraned. The nature o the power constrants may be derent (.e., the chps n cell phones vs. desktop processors, but n many cases today, and n most cases n the uture, the perormance one can acheve wll depend on the how ecently that computaton can be done per unt o. hle hstorcally or CMOS crcuts there has always been a strong relatonshp between power and perormance, the power o the chp remaned wthn the allowable power envelope; n ths scenaro, desgners ocused prmarly on achevng the needed perormance. Power, consdered, was only checked to ensure that t was not too hgh. In order to acheve the hghest perormance n the power-lmted scalng regme, one must use the most ecent method avalable, otherwse one wll overrun the speced power/ budget. Ths new relatonshp between peak achevable perormance and ecency changes the way one tends to thnk about desgn. Tradtonally, archtects try to create a machne organzaton that has the best perormance. Ths desgn s then passed to the block desgners, who agan try to buld the blocks n order to acheve the peak perormance. I ecency s the key n achevng hgh perormance, optmzng each layer ndvdually wll not lead to an optmal desgn, rather, t wll lead to a desgn that dsspates too much power. Instead, one needs to optmze the desgn by usng technques that are the most power ecent rst, untl the desred perormance or power s reached. Merely optmzng or the most ecent desgn s msleadng, snce ths approach rarely acheves needed perormance. Thus, the correct optmzaton typcally ether mnmzes the consumpton, subject to a throughput constrant, or maxmzes the amount o computaton or a gven amount o. Both these desgn optmzatons can be acheved the tradeos between the and delay are known. The dramatc ncrease n leakage currents n today s (and uture technologes adds another actor to the optmzaton problem. Snce some o the leakage power can be traded o or the dynamc power o the desgn, the optmzaton needs to select the correct balance here, as well. Furthermore, as the rato o leakage-to-actve power ncreases, the optmal archtecture and crcuts also change. From a power budget perspectve, leaky gates are expensve snce they cost watts when they are nactve. Thus, or leaky technologes, one wants to keep the gates as actve as possble, leadng to deeply ppelned, rather than parallel, archtectures. Desgn methods that explore true power mnmzaton need to work n a large dmenson search space, where power and perormance o derent solutons are compared. Ths ncludes system archtecture optmzaton (outer loop, blocklevel optmzaton (ntermedate loop, and xed topology optmzaton (nner loop. Gven that the nner loop optmzatons deal wth contnuous varables, one needs some way to gude the optmzaton to yeld globally optmal solutons. The key s to use the -delay tradeo to pece many derent optmzatons together. Ths paper explores ths problem, and uses nner loop examples to provde some nsght nto the method. 2. Power Mnmzaton Crcut optmzaton s not a new area and there s now a large research record on -constraned perormance optmzaton. Snce we utlze many o these technques, we wll brely revew some here, ocusng on nner loop optmzatons. An nner loop tool does not alter the crcut topology, so the prncple varables t aects are transstor szes, supply voltages, and threshold voltages. Szng optmzaton has been explored extensvely resultng n several optmzaton tools such as TILOS [4] and EnsTuner []. Almost all o these tools can at least approxmate -constraned szng by constranng the total transstor wdth avalable or the crcut. In addton, a

2 number o researchers derved analytcal solutons or area and szng optmzatons. The analyss s typcally restrcted to smple logc gates and nverter chans [2], [8]. For many years, usng supply to change the and perormance o crcuts has been utlzed and was one o the key technques n the low-power DSP work o Chandrakasan et al. [6]. Changng the supply to optmze the or a partcular applcaton was proposed n [], [3]. th the emergng mportance o leakage power consumpton, threshold voltage becomes an mportant tunng varable and s mostly consdered together wth supply voltage. Lu and Svensson hnted about the exstence o optmal supply and threshold or a gven desgn [7]. Gonzalez et al. presented a ramework or deeper understandng o jont supply and threshold voltage scalng or -delay product mnmzaton [9]. Nose and Sakura extended ths work and derved closed-orm ormulas or optmum supply, threshold, and leakage-to-swtchng power rato, mnmzng power dsspaton or a gven technology and operatng requency [4]. By usng multple supply voltages n the crcut, one can optmze consumpton by reducng the voltage on gates that drve large loads. Hamada et al. derved a set o practcal expressons or optmal number and values o dscrete supples, thresholds, and gate szes. They concluded that no more than three dscrete values are needed or each tunng varable []. Ther analyss was, however, lmted to sngle-varable optmzatons. More recently, researchers have looked at dong multple optmzatons at once. In modern logc desgn, hgh threshold transstors are placed n non-crtcal paths to trade leakage or avalable tmng slack. In addton, szng optmzaton s combned wth dual threshold to explot the remanng tmng slack [6], [7]. An nterestng approach has been taken by Zyuban and Strensk [8]. They ntroduce a method o balancng optmzatons at derent levels wthn the desgn usng a uned relatve gradent metrc they call hardware ntensty. In ths paper we ormalze the tradeo between and delay va senstvtes (.e. absolute gradents o to delay, whch are very smlar to the hardware ntensty. e develop practcal expressons or the senstvty o szng, supply voltage, and threshold voltage, relatng the potental savngs to the topology and prole o the crcut. The analyss o szng, supply, and threshold senstvtes urther reveals that the perormance o jont optmzatons can be predcted by knowng the reducton potental o each tunng varable and by applyng the concept o senstvty balancng. The -delay tradeo normaton s then passed rom the crcut level up to the block and mcro-archtectural levels. 3. Crcut Senstvtes In order to nd the crcut senstvtes, we rst need to obtan equatons that relate and delay to the transstor szes, the supply voltage, and the threshold voltage. hle there are many derent models that one can use, we ollow our pror work [9] and use the alpha-power law model o [5], as a baselne or the dervaton o the gate delay ormula: t d = + Kd Vdd out par V dd V α on n n ( d where out / n s the electrcal an-out o a gate, and par / n s a measure o ts ntrnsc delay [2]. hle ths model does have some ttng parameters (V on s not exactly, and α d and K d must be t, t does t the SPICE smulated data qute ncely. e consder two components o : swtchng and leakage. The swtchng component s the standard dynamc term shown n Eq. (2, ( 2 E = K + V (2 Sw α e out par dd where K e out s the load capactance, K e par s the selloadng o the gate, and α s the probablty o consumng transton at the output o the gate. Statc gate leakage at V gs = s modeled as ( Vth γvdd ( V ELk = τ d n I Sn e Vdd (3 where τ d s the delay o the logc block, I (S n s the normalzed leakage current o the gate wth nputs n state S n ; V and γ represent sub-threshold slope and DIBL actor. 3.. Senstvty Overvew In -delay optmzaton, the objectve s to utlze avalable tmng slack or maxmal reducton. There are usually several tunng varables that can be used to trade o and tmng slack at varous levels n desgn herarchy. As ponted out by Zyuban and Strensk [8], the -ecent desgn s acheved when the margnal costs o all the tunng varables are balanced. Each o these varables carres a certan reducton potental per delay cost at each pont o -delay space Eq. (4. Ths term (called hardware ntensty n [8] smply represents percent power per percent perormance or an -ecent desgn. E D θ ( X = x (4 E D x x= X The true power mnmzaton method always explots the tunng varable wth the largest capablty or reducton. Ths ultmately leads to the pont where the reducton potentals o all tunng varables are equalzed. In order to urther develop the understandng o these relatve gradents, we wll derve practcal expressons (senstvtes, or derent tunng varables. e consder gate sze, supply voltage, and change n threshold voltage as knobs n the optmzaton. By analyzng senstvtes, the ecency o,, and optmzatons can be estmated rom the prole o the logc block. Further, understandng the relatonshp between the logc block topology and the prole s necessary n order to denty the most ecent tunng varables wthout an exhaustve search Senstvty to Gate Szng The senstvty o to delay due to the szng o wthn a logc block s gven by Eq. (5. There, ec represents the swtchng ntroduced by, p Lk, s (

3 the leakage power o and P Lk s the total leakage power. Parameter h e, s the eectve anout o [2]. ESw ec = D τ h h (,, e e ELk d p = P Lk D h h Lk, e, e, (5a (5b Equaton (5 shows that the largest potental or savngs occurs at the pont where the desgn s szed or mnmum delay wth equal eectve anouts, snce the h e terms wll be equal. Ths extends the varable taper result or an nverter chan [8], to more complex logc gates and topologes. Equaton (5b also suggests that at certan delay, leakage wll start ncreasng wth urther sze reducton Senstvty to Supply Voltage The senstvty o total to delay, due to global supply reducton, s gven by Eq. (6. Agan, the desgn szed or the mnmum delay at a nal supply oers the greatest potental or reducton. Ths potental dmnshes wth the reducton n supply voltage. Supply reducton has a twoold mpact on the leakage : the leakage ncreases because o ncrease n delay, whle on the other hand, t decreases because o the supply reducton and the reduced DIBL eect. The resultng tendency s the decrease n the leakage wth supply reducton, whch results n negatve senstvty to delay, Eq. (6b. ESw Vdd ESw xv = 2 (6a D D αd + xv Vdd ELk V dd xv γvdd = PLk E + (6b Lk αd xv V + V dd Parameter x v = (V on + / ; parameters V on and α d capture the DIBL eect on delay but are xed across the range o supply voltages o nterest. The same ormula can be appled to dual supply voltage optmzaton. In that case, E and D would represent the total and delay o s under low supply voltage Senstvty to Threshold Voltage The senstvty o to delay due to the change n threshold voltage s gven by Eq. (7. Ths senstvty decays exponentally wth the ncrease n because P Lk s an exponental uncton o. E ( Vth Vdd Von Vth = PLk. (7 D αd V ( V th Snce the leakage power s exponental n, threshold voltage optmzaton has a lmted range. For desgns wth very low leakage, lowerng the threshold voltage s very attractve snce t decreases delay wth a very small cost. 4. Crcut Optmzaton Examples The senstvtes dscussed n the prevous secton are derved or ndvdual gates. hat s more nterestng s the senstvty or whole crcut blocks. To evaluate blocks, ths secton looks at a ew crcuts to relate sgncant topologcal propertes o logc paths sngle path, o-path load, reconvergence to the eectveness o each o the optmzaton varables. Crcut block examples nclude a smple nverter chan, a memory decoder, and a tree adder. In all o the examples, the nal crcut s optmzed or mnmum delay d mn at nal supply voltage V dd and nal threshold V th ( =, as a reerence. Startng rom the nal crcut, delay ncrement d nc s speced and s then mnmzed under the delay constrant d = d mn (+d nc. The delay-constraned mnmzaton represents a geometrc program, whch can be ormulated n a convex orm [4]. Optmzaton parameters are gate szng, supply voltage, change n threshold voltage, and optonal buer nserton. Energy-constraned delay mnmzaton s a dual problem to delay-constraned mnmzaton. 4.. Inverter Chan Sngle Path 4... Szng Optmzaton Mechansms The use o gate szng to mnmze the o a xed length nverter chan s shown n Fg. a. Intally, when the crcut s szed or mnmum delay, all s have the same delay. Due to the geometrc progresson n sze, most o the s dsspated n the last ew s, wth the largest stored n the nal load. Startng rom the mnmal delay pont where all o the senstvtes are nnte, we change the gate szes along the chan so that all o the senstvtes decrease equally. Ths, n turn, leads to an ncrease n eectve anout toward the output where most o the s consumed, as shown n Eq. (5. Thereore, the bggest savngs or a xed delay ncrease are acheved by downszng the largest gates n the chan rst. The optmal sze o s derved n Eq. (8. The expresson s smlar to that n [8] and drectly ollows rom Eq. (5a. = ec + S τ In the above ormula, s the sze o that results n the mnmum delay o the chan [3]. In an -ecent desgn, szng senstvty o all s S s equal and also a uncton o the delay constrant. eectve anout, h e (a Fg.. opt d nc = 5% eectve anout, h e (b opt Szng: a xed, b varable number o s (8 d nc = 5%

4 I the number o s can be vared, the delay constrant may be met wth a ewer number o s leadng to a greater reducton. Intutvely, as the nal s downszed to gan the bggest savngs or a gven delay ncrease, the sze and number o the remanng s adjust to meet the delay constrant, Fg. b [9]. It s mportant to realze, due to geometrc progresson n sze n an nverter chan, that most o the s consumed n drvng the xed nal load, and the maxmum savng rom szng s lmted to about 3% Supply Optmzaton Mechansms Unlke szng, scalng the supply drectly aects the needed to charge the nal load capactance, and thereore can have a larger eect on the total. For llustraton, we show supply optmzaton on a per- bass n the nverter chan. Our assumpton here s that the supply voltage can only decrease rom the nput toward the output to avod level converson nsde the block. In the nal case, n whch the delay o each s equal, the supply senstvty o each depends only on the o that, as ndcated n Eq. (6a. As n szng, supply voltage optmzaton adds ncremental delays, rst to the s wth the hghest consumpton (s toward the end o the chan, whle ncreasng the eectve anout o these s by lowerng ther supply voltage. Fgure 2 shows the optmzed per- supply and the resultng eectve anout. 8 d nc = 5%. opt d nc = 5% opt Fg. 2. Per- supply, varable number o s ( Compared to szng, the supply optmzaton requres less change n the eectve anout or the same reducton. In practcal desgns, the eectve anout o the gate s bounded by the sgnal slope constrants to around Memory Decoder O-path Load A buer chan has a partcularly smple dstrbuton, one whch ncreases geometrcally untl the nal. Ths type o prole drves the optmzaton over szng and supply to ocus on the nal s rst. Most practcal crcuts have a more complex prole due to o-path loads and varyng actvtes per logc, or example, a SRAM decoder. The decoder shares some characterstcs wth a smple nverter chan; the total capactance at each grows geometrcally, but the number o actve paths decreases geometrcally, as well. As a result o ths, the peak o the dstrbuton s oten n the mddle o the structure. For example, the 256 wordlne SRAM decoder shown n Fg. 3 has the peak at the output o the predecoder because o the path propertes shown n Table. eectve anout, h e Table. Actvty map o the wordlne SRAM decoder SRAM decoder gates Fgure 3 shows the crtcal path o ths SRAM decoder. The multplcaton actor m denotes the number o actve gates at each. Branchng occurs at the nput o each NAND gate and the number o actve gates per decreases n a geometrc ashon to select only one wordlne at the output Szng and Buer Inserton Szng optmzaton eectvely reduces the nternal peaks through drect gate szng or buer nserton, as shown n Fg. 4. The ntal szng or mnmum delay does not requre an extra buer at the output o the decoder, thus the total number o s s seven. Insertng a buer at the output reduces the eectve load presented by the 256 decoder/word drver cells. Alternatvely, optmzaton by drect gate szng mnmzes the sze o the word drver nput and produces the same eect, as shown n Fg. 4b. Ths essentally dvdes the szng problem nto two sub-problems: a szng o predecoder logc to drve the mnmum word drver nput, and b szng o word drver to drve the wordlne. Ths s readly seen rom the per- senstvty expresson wth branchng: ESw b ec = (9 D τ ( he, he, predrver predecoder Inv Nandnnv Nand- Actve Total word drver Nand-nvbu addr nput Fg. 3. m=6 predecoder m=4 m=2 3 n whch b - s the branchng actor o the -. Downszng the gates drven by the wth the hghest branchng actor yelds the bggest savngs or the gven delay cost. In the decoder example ths stuaton occurs at the output o the predecoder, as shown n Fg. 4a. hle the peak o swtchng s nsde the block, the peak o leakage occurs at the output, due to the (a C word drver m= Crtcal path, 256 wordlne SRAM decoder d d + 5% mn,7 mn,7 E E 7-5% (b C L 2 : E(-26% : E (-5% d nc = % word lne (L Fg. 4. Energy prole n SRAM decoder: a d mn desgn, b d nc =% (L=28, nput actvty s %

5 swtchng leakage E Lk / E Sw =.4 8 E Lk / E Sw = swtchng leakage nal: d=d mn szng: E(-68% d nc =% (a actvty prole o the decoder. Ths s llustrated n Fg. 5, where the prole n a mn-delay szed decoder s shown or cases wth seven and nne s. Output gates are the largest and the majorty o the gates are nactve, resultng n the largest leakage at the output. Although nsertng a buer reduces the sze o the predecoder, the leakage o the word drver ncreases relatve to the swtchng as shown n Fg. 5b, because only one output buer s actve at a tme Supply Optmzaton Fg. 5. Energy prole n SRAM decoder wth a 7 s, b 9 s (d=d mn, L=28, nput actvty s % The supply optmzaton s less eectve n desgns where the peak o consumpton occurs nsde the block. Because o the assumpton that the supply voltage can only decrease rom nput to output, n order or the supply to aect the peak, the delay o all s ater the peak needs to ncrease, thus reducng the margnal return, as shown n Fg. 4b. Szng optmzaton s more eectve than dscrete supply optmzaton because szng can selectvely reduce domnant peaks nsde the block by payng the prce o ncreased delay, n s only rght ater the peak, thereore ncreasng the margnal return. Contrarly, the supply starts rom the output o the block and works backwards Adder O-path Load and Reconvergence More complex desgns may have reconvergent anouts and multple actve outputs qualed by paths wth varous logc depth. As an example, we analyze a 64-bt Kogge-Stone tree (A, B (b S 63 bt slce (a adder []. The structure o ths adder s shown on 6-b example n Fg. 6. There are many paths through an adder, and unlke the decoder, not all o these paths are balanced. To be ar, the ntal szng makes all the paths n the adder equal to the crtcal path. As a result, urther reductons n sze would cause the delay o the adder to ncrease. Snce the paths through an adder roughly correspond to derent bt slces, we allocate each gate n the adder to a bt slce. Ths partton works well or tree adders, and Fg. 7 shows the resultng map or the mnmum delay, as well as the stuaton when a % delay ncrease s allowed [9]. Lke the decoder, the domnant peaks are nternal, whch makes transstor szng more eectve than scalng. The data ndcates that a 68% decrease n s possble usng transstor szng, whle only 32% s saved by usng two supples. Reducng the supply over the whole block yelds only 7% o reducton. In ths type o adder, the swtchng actvty o propagate logc dmnshes rapdly wth the number o s, and most o the swtchng s consumed by the generate logc. Thereore, the peak n Fg. 7a occurs close to the nput o the adder, where the actvty o propagate logc s stll comparable to that o generate logc. Lke n the decoder, the adder maps show that szng optmzaton s very eectve when peaks occur nsde the block. 5. Jont Optmzatons bt slce Fg. 7. Energy map n 64-b adder a d mn desgn, b d nc =%, gate szng (L=32, nput actvty s % To acheve the most -ecent desgn, the reducton potentals o all the tunng varables must be balanced, otherwse one would tune the varable wth low cost rather than the varable wth hgh cost. Optmzaton o and has been explored by many researchers. Here, t s revewed rst, beore lookng at the more general problem. (b 5.. Optmal and (A, B ( a, b k k ( p, g k g j ( p, g c = g + k Fg. 6. Kogge-Stone tree adder k k ( p, g k k ( p, g j j k+ k+ ( p, g p s c j S The nal supply and threshold ( =, gven by the technology, are rarely optmal or all applcatons rom the -throughput standpont. To llustrate ths, one should assume that requred throughput s acheved wth the nal transstor at the nal supply voltage. The same throughput can be acheved wth less by adjustng and [7], [9], [4]. In the nal case, the leakage s not sgncant, so s lowered. Ths, n turn, creates tmng slack that enables the reducton o

6 , whch targets the domnant component o consumpton swtchng. The results ndcate that the values o optmum and depend on nal process parameters, requred throughput, block uncton, and topology. Expressons or optmal and were derved by Nose and Sakura n [4], leadng to optmal rato o leakage and swtchng. Smplyng ther expresson by usng the lnear current model (α d =, we obtan the dependence o optmal leakage-to-swtchng rato n terms o process and archtectural parameters, ELk 2 = (a ESw Opt L ln d K tech α avg 2CV V dd Ktech = ln (b dfo4 I Vth γv dd where α avg s the average block swtchng actvty, L d s logc depth o the crtcal path, d FO4 s the delay o a FO4 nverter at the nal supply V dd and the nal threshold V th, and C s capactance per mcron o gate wdth. swtchng bt slce leakage From the archtectural standpont, logc depth can vary by less than an order o magntude, but average actvty can change by several orders o magntude, dependng on the uncton. As a consequence, n desgns wth smlar actvty, optmal leakage-to-swtchng rato wll be almost constant due to the logarthmc dependence [9]. In our example, the adder crcut has a much hgher average actvty than the decoder. Due to the hgh swtchng actvty n the adder, leakage s small relatve to the swtchng component or the nal case, so the optmzaton lowers the threshold to create tmng slack and then scale down to reduce swtchng, Fg. 8. Ths results n an optmal leakage to swtchng rato o 45% n the adder, compared to 33% n the decoder, matchng the predctons rom [4] o about a 4% rato. Unortunately, the range o threshold adjustment through substrate bas s small, whch oten prevents one rom achevng optmal perormance Other Combnatons and Examples The jont optmzaton has the addtonal degree o reedom to choose a more ecent drecton at each pont toward the optmal soluton. In general, t s very dcult to predct the contrbuton o each tunng varable n a multvarable optmzaton. In cases where senstvty o one tunng bt slce Fg. 8. Energy map n adder, d=d mn ( =, E Lk /E Sw =.45, V opt dd =.78V dd, V opt th =-9mV (L=32, nput actvty s % reducton (% (a Fg. 9. reducton (% (a delay ncrement (% reducton (% (b delay ncrement (% varable s sgncantly larger than those o other varables, the optmzaton trajectory can be approxmated by the trajectory along that varable. hen szng, supply and threshold voltage are used as optmzaton varables, szng has the largest senstvty or small delay ncrements rom the mnmum delay desgn. Threshold senstvty dmnshes qucker than that o supply or szng, leavng the supply senstvty domnant one n the regon o large delay ncrements. Ths s shown or adder and decoder examples, n Fgs. 9a and a, respectvely. Such propertes allow or the analyss o jont optmzatons based on the behavor o sngle-varable optmzatons. Furthermore, the perormance o sngle-varable optmzatons can be predcted rom the topologcal propertes and the prole o a block wthout actually perormng the optmzaton. e begn the jont optmzaton analyss wth a szng and supply example. Snce the reducton potental o szng and supply s not equal at the mn-delay pont, t s possble to save wthout a delay penalty by smply balancng senstvtes. Rasng the supply voltage and changng the szes reduces the power. Due to the large gap between szng and supply senstvty, the ncrease n supply voltage results n the ncrease n, but creates slack, 8 6 Energy reducton technques n 64-b tree adder, (L=32, nput actvty s %, and are adjusted per block, s contnuous delay ncrement (% reducton (% (b delay ncrement (% Fg.. Energy reducton technques n SRAM decoder, (L=28, nput actvty s %, and are adjusted per block, s contnuous Vdd ( V.4 dd (a delay ncrement (% Vth (mv (b delay ncrement (% Fg.. Values o a, and b or cases n Fg.

7 whch s then exploted wth more ecent szng optmzaton or overall reducton. The bgger the ntal gap between the two senstvtes, the greater the reducton that can be obtaned. For example, at mnmum delay, the gap between the szng ( and the threshold ( s the largest, ollowed by that between the szng and the supply (, whle the gap between the supply and the threshold s the smallest. Ths results n the largest ntal reducton when the szng s combned wth threshold (, and the smallest reducton when the supply s combned wth threshold (. By analyzng Fg., we can help better understand the role o the supply and threshold varables n jont optmzatons. Snce the supply has a smaller senstvty than the szng, the supply s ncreased to a create tmng slack whch can be more ecently utlzed by szng, the case n Fg. a. On the other hand, snce the supply has a larger senstvty than the threshold, ts decrease s more ecent whle the threshold reducton serves to preserve tmng, as shown n case n Fg.. In addton to the ntal gap between the senstvtes, whch determnes the reducton at the startng pont, the resultng balanced senstvty value determnes the potental or reducton as the delay s urther ncreased rom the startng pont. Energy savngs o about 6% n the adder and 4% n the decoder are possble wthout any delay penalty by smply choosng approprate values o supply, threshold, and crcut sze, as shown n Fgs. 9b and b. However, ndvdual crcut examples may be msleadng. The margnal costs o the overall system are really what matters, and that s the reason why senstvtes are mportant. For example, adder, or some other unctonal-unt s a much smaller percentage o the total processor than that o latches/clockng, than t mght actually pay o to lower the power o the latches (make the latches slower and ncrease the power o the adder (make the adder aster. 6. Mcro-Archtectural Optmzaton Examples In order to gve an example o the system-level optmzaton, ths secton wll revst the example rom Chandrakasan et al. [6] to compare a ppelned system desgn to a parallel system desgn or mnmzng power. A schematc o the crcut s shown n Fg. 2. The reerence desgn s an Add-Compare unt whch uses the adder descrbed n Sec. 4.3, or both the adder (block A and comparator (block B. The reerence desgn s optmzed or mnmum delay under and. Usng the throughput A A B (a reerence B (c ppelne 2 2 A A B B (b parallel Fg. 2. Mcro-archtecture example: a reerence desgn, b parallel desgn, c ppelne desgn o ths desgn as a constrant and normaton about reducton tradeos o the adder and comparator blocks rom the nner loop, we can estmate the needed or the reerence desgn and ts parallel or ppelned mplementaton. In each o these three desgns, the goal s to nd the optmal value o the supply and the threshold voltage that result n a mnmum or the gven throughput constrant. Ths value s ound by optmzaton, n whch s swept rom to -2mV n steps o 5mV. Each tme s moded, n all three desgns s adjusted to acheve the target throughput wth mnmal, usng the multvarable senstvty normaton rom the lower level blocks. The goals o ths sweep are to nd the optmal (, pont or each mplementaton and to llustrate the trend around the optmal pont, as shown n Fg. 3. For each desgn, optmal (, pont s reached when the voltage and threshold senstvtes o all the underlyng blocks are balanced. As seen n Fg. 3, although the optmal (, ponts are derent or each mplementaton, they all roughly correspond to the same value o leakage-to-swtchng rato. Ths s n lne wth Eq. (, snce the logc depth and actvty n these mplementatons do not vary sgncantly. In ths example, the optmal rato o leakage-to-swtchng s around 4% or all the mplementatons, whch roughly corresponds to that o ts man sub-block the adder. In act, all the curves are very lat around ther optmal pont n a range rom 2% to % o leakage-to-swtchng rato. Energy-per-operaton n all three desgns s compared to the reerence case whch operates at V dd and V th. The swtchng -per-operaton decreases approxmately by the same actor rom voltage scalng n both the parallel and the ppelne desgns. The leakage ncreases rom ncreasng the area o the desgn, and decreases rom scalng down the supply voltage. Thereore, the leakage o the parallel desgn s larger than that o the ppelned desgn because o the larger area. It has been shown that parallelsm s more -ecent than ppelnng when the leakage s about an order o magntude smaller than the swtchng [6]. However, as devces become leaker, the larger area o parallel desgn causes the balance between the swtchng and the leakage to occur at a hgher supply voltage than that or a ppelne desgn. For ths reason, a parallel mplementaton acheves smaller savngs. Equvalently, the ntroducton o parallelsm decreases the amount o tme that a devce spends on computatons, thereby decreasng the rato o useul (swtchng to wasted (leakage. E (re. E Operaton Operaton mV.49-85mV.45-3mV parallel ppelne reerence E / E Leakage Swtchng Fg. 3. Parallel, ppelne, and reerence desgns: -peroperaton vs. leakage-to-swtchng rato

8 Optmzatons o szng, supples, and thresholds have lmted scope due to the physcal or unctonal constrants o these tunng varables. Each topology has a range wthn ts -delay space where the and delay can be traded or each other. At ether extreme, the margnal cost o decreasng the /delay becomes too large. For a specc topology, about a two-tme ncrease n the delay explots almost all the avalable savngs, so the margnal savng or an addtonal delay s very low. Archtectural changes lke parallelsm and ppelnng mplctly ncrease the delay o the underlyng block about two-tmes, leavng lttle space or addtonal optmzatons. Ths s llustrated n Fg. 4, n whch the o the desgn (reerence, parallel and ppelned s shown as a uncton o the delay ncrement rom the nal value, or (a the supply optmzaton, and (b the supply and threshold optmzaton. E Operaton (re. E Operaton optmzaton reerence parallel ppelne 5 2 delay ncrement (% E Operaton (re. E Operaton optmzaton reerence parallel ppelne 5 2 delay ncrement (% Fg. 4. Energy vs. delay ncrement or reerence, parallel and ppelne desgn under a the supply optmzaton, b the supply and threshold optmzaton The throughput requrement set by the applcaton determnes the choce o the most ecent crcut topology (or example, the type o adder. Gven that the scope o optmzaton or each topology s lmted to about a two-tme ncrease n ts delay (rom the mnmum set by technology, t s desrable to choose the crcut topology whose mnmum achevable delay s postoned relatvely close to the throughput requrement determned by the applcaton. Once the topology s chosen, the optmzaton o the szng, supply, and threshold can be ecently exploted. 7. Conclusons Creatng ecent crcuts s becomng an ncreasngly mportant prorty. In order to truly mnmze the power n a chp, t requres that the derent layers o the desgn all work toward achevng the same balance n tradng or perormance. e examned the lowest level optmzaton ssues n ths paper, explorng how optmzng the gate sze, the supply voltage, and the threshold voltage aect crcut perormance. In topologes wth a monotonc ncrease n towards the output (such as an nverter chan, supply reducton acheves the largest savngs, wth szng beng much less eectve. I, however, an o-path load and a reconvergent anout are present, szng optmzaton wll be the most eectve snce the peak o consumpton s nternal to the block. In lookng at a desgn optmzed or speed, the nal clock cycle should be set about % hgher than the theoretcal mnmum, due to the large benet oered by a small delay penalty; but the returns rom szng quckly all o, and above 2% the return s very small. In contrast, a global supply reducton s the least eectve reducton technque or small delay ncrements, but t s qute useul when the delay ncrement s szeable. It s ound that or the crcuts analyzed at a delay ncrement o 2%, at least a 3% savngs can be acheved by szng, and a 3%-6% by supply optmzaton. A combnaton o szng and supply or threshold voltage can provde a 4-7% savngs. Proper balancng o the tunng varables provdes an savngs o about 5%, wth no delay penalty. Future work s needed to see smlar tradeos exst at the block and mcroarchtecture levels. The desgns that are truly power-optmzed wll have hgher leakage current than what s common today. By ncreasng the leakage, ppelnng begns to have advantages over parallel solutons, and has already begun to aect how hgh-perormance chps are desgned. Acknowledgments Ths research s supported n part by MARCO contracts: CMU 2-CT-888, GSRC 98-DT-66, and Georga Tech B- 2-D-S5. Reerences [] P.M. Kogge and H.S. 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