Abstract. 1. Introduction. 2. Control Generated Clocking (CGC) Minimization techniques

Transcription

1 Power Mnmzaton Usng Control Generated Clocks Srkanth Rao M. and S. K. Nandy Supercomputer Educaton and Research Center Indan Insttute o Scence Bangalore, Inda 5600 Abstract In ths paper we descrbe an area ecent power mnmzaton scheme "Control Generated Clockng" that saves sgncant amounts o power n datapath regsters and clock drvers o sequental crcuts. Power savngs are acheved by makng smple changes to the state machnes controllng the datapath. These changes enable the control sgnals rom the state machnes themselves to be used as clocks or the datapath regsters. Use o these control generated clocks makes the statc tmng analyss o desgns mplementng ths scheme smpler when compared to technques such as clock gatng. Ths scheme preserves the cycle boundares on whch regsters load data, thereby allowng reuse o unctonal test cases developed or the orgnal crcut. In ths paper we also descrbe tmng requrements o a desgn n whch ths scheme has been mplemented, cost-benet aspects o ths scheme and an algorthm or the automatc synthess o control generated clocks. Results rom applcaton o ths technque on a complex desgn are then dscussed.. Introducton Hgh levels o ntegraton, hgh operatonal requences and the proleraton o battery operated applcatons has rendered power dsspaton a key parameter n the desgn o present day VLSI crcuts, snce t aects relablty, perormance and cost o the crcut [][8]. In hgh requency CMOS dgtal crcuts, the dynamc power resultng rom chargng and dschargng o parastc capactances domnates over the power dsspated due to leakage currents [][8]. The ocus o most mnmzaton technques s thereore dynamc power. In a sequental crcut, the sources o dynamc power dsspaton and commonly used technques or power mnmzaton are lsted n Table. Clock gatng [][6][8] s an eectve technque or power mnmzaton n crcuts that are dle or long perods o tme. Clock gatng n ts most general orm has some practcal dcultes, vz. Permsson to make dgtal/hardcopy o all or part o ths work or personal or classroom use s granted wthout ee provded that copes are not made or dstrbuted or prot or commercal advantage, the copyrght notce, the ttle o the publcaton and ts date appear, and notce s gven that copyng s by permsson o ACM, Inc. To copy otherwse, to republsh, to post on servers or to redstrbute to lsts, requres pror specc permsson and/or a ee. DAC 000, Los Angeles, Calorna (c) 000 ACM /00/0006..$5.00 Source Clock drvers Mnmzaton technques Clock gatng Regsters Clock gatng Combnatonal logc Precomputaton and guarded evaluaton[9][], Retmng[5], State assgnment n s [] [7] Table. Sources o power dsspaton n sequental crcuts and assocated mnmzaton schemes.. Possblty o gltches on the gated clock sgnal when the gatng sgnal arrves later than the clock.. Dcultes n usng statc tmng analyss eectvely on the desgn when the gatng sgnal s data dependent, whch s usually the case. In ths paper, we descrbe a robust new technque called Control Generated Clockng (CGC) that can be appled to mnmze dynamc power n a synchronous sequental crcut. Ths scheme acheves hgher power savngs compared to clock gatng whle overcomng the drawbacks o clock gatng lsted above. Ths scheme mnmzes the power dsspaton n the datapath regsters and n the clock drvers, wthout aectng the cycle boundares on whch regsters load data. The organzaton o the rest o the paper s as ollows. Secton o the paper provdes an overvew o the proposed scheme. Followng ths, we descrbe the statc tmng analyss o a desgn wth CGC n secton 3. Secton 4 descrbes an algorthm or automatc synthess o CGC and we dscuss the cost-benet aspects o CGC n secton 5. We present results obtaned ater mplementng CGC n a RISC processor n secton 6 and nally conclude n secton 7.. Control Generated Clockng (CGC) Consder a general edge-trggered synchronous sequental crcut shown n gure (a), n whch multple state machnes are shown, sequencng operatons n the datapath. Control sgnals rom the state machnes enable wrtes to regsters n the datapath. The master clock MCLK synchronzes all actvty n the datapath regsters as well as n the controllng state machnes. Note that when wrtes to certan datapath regsters are nrequent, a lot o power s unnecessarly dsspated n the drvers o the clock MCLK and n lp- o the datapath regsters. Fgure (b) shows the tmng dagram or a wrte to a sngle lp n any datapath regster n such crcuts. The gure shows the control sgnal, whch s synchronous to the clock MCLK. The lp- loads the data on the next rsng edge o clock MCLK. Observe that or a sngle wrte operaton, ths also happens to be the allng edge o the control sgnal. Our scheme

2 essentally uses ths control sgnal as the clock or the lp-. The lp- must now respond to the allng edge o the sgnal. Ths smple arrangement does not work when there are back-to-back wrtes to the lp-. In such a scenaro, the sgnal changes only at the end o the last wrte to the lp-. In the CGC scheme descrbed below, ths problem s allevated usng RZ pulse generator crcuts. Master Clock MCLK In CGC, the general system shown n gure (a) s transormed to a system shown n gure (a). Ths scheme ntroduces certan changes to the orgnal crcut lsted below: MCLK Enables Datapath Regsters Datapath Regsters (a) MCLK Flp output Data s loaded on the next rsng edge o MCLK (b) Fgure. (a) A general synchronous sequental crcut. (b) Tmng dagram o a wrte operaton. Re-coded Re-coded Re-coded Enables RZ CCLK CCLK pulse CCLK3 gens. CCLK4 Datapath Regsters MCLK Control clock CCLK Flp- output versons o the control sgnal are created. One s used or the generaton o the control clock, and the other s used to eed any other logc as requred. The latter s not ed to the RZ pulse generator. Addtonally, control sgnals or regsters that are wrtten to by more than one state o the controller may need shadow lp- and retmng. Ths step s descrbed n detal n [0][]. Fgure (b) llustrates the tmng relatonshps between sgnals n an mplementaton o ths scheme. The gure ndcates two backto-back wrtes takng place to a lp-. Note that the sgnal has only one allng edge n ths case. I the sgnal were drectly ed to the clock nput o the lp-, only one wrte would take place. The RZ pulse generator toggles the control clock once every cycle, allowng back to back wrtes to take place. The RZ pulse generaton crcut s not necessary or those lp- that never get updated n a back-to-back ashon. Note rom the tmng dagram that data gets loaded nto the lp at the same cycle boundares as n the orgnal crcut. Ths s desrable, because test cases wrtten or the vercaton o the orgnal crcut can now be reused wthout any changes. 3. Tmng Analyss In ths secton, we descrbe the tmng constrants to successully mplement CGC n a crcut. In a crcut wth CGC, n addton to the orgnal clock doman o MCLK, new clock domans o the control clocks CCLKs are ntroduced. The constrants to be satsed or ensurng relable transers between regsters n derent clock domans are based on the source and the target clock domans. In CGC, the control clocks are derved rom lp outputs, and wll have determnstc delays wth respect to the master clock. To derve the constrants or relable transers between any two lp- n a desgn wth control generated clockng, we assume a model shown n gure 3. For smplcty we assume that RZ pulse generators generate all control clocks. Enables CCLK6 (a) Datapath Regsters (b) Fgure. (a) Crcut wth CGC (b) Tmng dagram o a crcut wth CGC. Source clock Source Target clock Combnatonal path +ve/-ve Delay Target (a) Changes to the datapath regsters: All postve edge trggered lp- n the datapath regsters are replaced by negatve edge trggered ones. Ths s needed n order to preserve tmng relatonshps between sgnals o the orgnal crcut, because wrtes to regsters n the orgnal crcut complete on the allng edges o the control sgnals. (b) Changes to the clocks: Clocks to all datapath regsters n the target logc are replaced by control generated clocks, ndcated as CCLKs n the gure. The control generated clocks are control sgnals that have been condtoned by the RZ pulse generators. The RZ pulse generator crcut s descrbed n [0][]. Step (a) above can be elmnated actve low control clocks are used. (c) Changes to the controllng state machnes: The states o the controllng state machnes are recoded to ensure that each o the control clocks s gltch ree and has mnmum skew wth respect to the master clock MCLK. I a control sgnal s used or any other purpose, besdes enablng the wrte to a regster, two Fgure 3. Model used or tmng calculatons. The gure shows a combnatonal crcut path orgnatng at a lp- output and endng n lp- nput, possbly n another clock doman. The lp- at the target o the combnatonal path sees a skewed clock wth respect to the source. Note that because o the RZ pulse generators, the control clocks wll have the same perod T as the master clock when they are turned on. We assume that the maxmum possble value o the clock skew on the master clock n the desgn s known and ts value s denoted by ± T. skew Table lsts all the tmng paths n a desgn wth CGC and the correspondng allowable maxmum and mnmum delay. In the table,

3 where q α T T and = T T q α = T skew + T su hold T skew q T denotes the output delay o the lp- at the source relatve to ts clock, T su denotes the setup tme o the lp- n the target, T hold ts hold tme, and Trz the propagaton delay through the RZ pulse generator. For transers between an MCLK doman and a CCLK doman, the delay ntroduced by the RZ pulse generator manests tsel as addtonal clock skew. For transers between two derent CCLK domans, ths method can expose alse tmng paths n the orgnal desgn. In table, n ndcates the mnmum path length between set o states that wrte to the source and the set o states that wrte to the target, n the controller state transton dagram. In sum, tmng analyss o a crcut wth control generated clockng s smpler than that o a crcut mplementng clock gatng. Ths s due to the act that ths scheme ntroduces determnstc skews on the control clocks. Path orgnatng n doman Path endng n doman Max. Delay MCLK MCLK MCLK CCLK α + Trz CCLK CCLK Mn. Delay α α α + Trz CCLK α α CCLK j α, n=0 α + n T, n>0 ( ) CCLK MCLK α Trz α, n = 0 0, n>0 α Trz Table. Tmng paths n a crcut wth CGC and ther bounds. 4. Automaton Ths secton descrbes a procedure to automate the nserton o CGC n a crcut. It takes as nput, a descrpton o state machnes controllng the regsters n the datapath along wth a set o target regsters and outputs a re-coded state machne sutable or CGC. Ths procedure also marks those regsters that requre shadow lp- and can be updated n a back-to-back manner. Each state n the state machne descrpton has an attrbute code that represents ts encodng. The set o regsters n the datapath that are to be targeted by ths scheme s speced n the set T. Each regster r k T has an attrbute CS, called the control set, whch s the set o all states whch cause a wrte to r k. The control set o each regster s constructed rom the nput state machne descrpton. Every target regster has two other boolean attrbutes namely, shadow and bb whch respectvely ndcate whether the regster needs a shadow lp- or ts control sgnal and whether t can get updated n a back to back ashon. The attrbute bb s used to nsert an RZ pulse generator or the control sgnal. The algorthm or nsertng CGC s descrbed below. // Man body o the algorthm ; set_o_regsters T; man() { // Read the nput and construct the read_nput(); // Convert the state machne nto Moore requred Procedure // s descrbed n Re [3] ( smealy() ) MealyMoore(); // Identy all those states whch wrte to a regster. Construct // control set or each regster gencontrolset(); // Encode the state machne or CGC Encode(); // Identy those regsters whch get updated n a back to back // ashon,.e., nd states n the control set o any regster //have a path length o exactly. MarkBB(); // Identy all the control sgnals whch need a shadow lp- // These are control sgnals or regsters wth more than one //state n ther control set MarkShadow(); // Wrte the encoded state machne and ts attrbutes to the //output. wrte_output(); } The above algorthm s mplemented as a tool TICTOC. Ths tool accepts a state machne descrpton and outputs syntheszable VHDL code ater nsertng CGC. The tool has been mplemented n Perl and has been wrtten n approxmately 00 lnes o code. 5. Cost benet analyss In ths secton we derve analytcal expressons or the power saved n a crcut wth CGC, and the overheads assocated wth t. Wth CGC, power s saved n the regsters and n the clock drvers. In subsecton 5., we derve an expresson or regster power saved. Followng ths, n subsecton 5., an expresson or the power saved n the clock drvers s derved. In subsecton 5.3, we estmate the overheads n CGC. 5. Power saved n regsters Power dsspated n the target logc wthout CGC s rst computed. We assume that each target lp- n the datapath consumes the same energy E per clock, and the same energy wrte E per wrte. The total dynamc power consumed per lp, wthout CGC s gven by P = E + E wrte wrte where s the requency o the clock, and wrte s the average requency o wrtes to regster. The total dynamc power consumed by regster s then gven by P ) = ( E + E ) wdth reg ( wrte wrte where wdth represents the number o lp- n regster. Hence the total dynamc power dsspaton P o the target crcut s expressed as P = P reg ( ). 3

4 In a crcut wth CGC, the number o clocks to the target lp s the same as the number o wrtes. The power dsspated by regster s now gven by P ) = ( E E ) wdth reg opt ( wrte + wrte wrte The dynamc power dsspaton expressed as P opt = P reg opt Popt o the target logc s now ( ). The power savngs n the regsters can be computed by substtutng or P and P opt n the ollowng expresson. to yeld where x = = P Popt Savng = () P x Regster Power Savng = () + kx wrte N N lp wdth wdth, 0 x and E k = E wrte, and s the number o lp- n the target logc. Here, k s a parameter that s dependent on the crcut desgn o the lp-, and x s a parameter that captures actvty n the regsters. Fgure 4 shows a plot or ths uncton or varous values o k. The maxmum savngs are obtaned when x = 0, or when the crcut s shut o. When the crcut s operatonal, the savngs depend on the value o k and the value o x. For a xed value o x, a larger value o k results n lower power savngs. The eect o k on power saved s low when the value o x s close to 0 or close to. The rato ( wrte ) s a measure o the actvty n the regsters. Ths rato may be computed as the sum o probabltes o the state machne beng n those states that wrte to regster as ollows ( wrte ) = p( s), s CS() s where CS() s the control set o regster, and p(s) s the statc probablty o the controller beng n state s. Ths expresson allows us to estmate the savngs early n the desgn process rom prole normaton. Power savng Actvty actor x Fg 4. Varaton o power saved wth actvty and lp- parameters k= k= k= Power saved n clock drvers We assume that every lp- presents a capactve load C on the clock lne. In a crcut wthout CGC, the total lp capactance load on the clock lne s gven by C = C + N C other where C other represents the load on the clock lne because o logc that s not part o the target logc. Wth CGC, a xed overhead C s added per control clock to the master clock. overhead Ths makes the load on the clock lne C = C + N opt other reg C overhead where s the number o regsters targeted by ths scheme. At the same tme, the regsters targeted by CGC load the control clocks. The load on the control clock lne s gven by Cc ( ) = wdthc Power dsspated n the clock drvers o the crcut wthout CGC s expressed as P = CV, and power dsspated n the clock drvers o the crcut wth CGC s expressed as P opt = C optv + V C c ( ) wrte Power savng n the clock drvers s calculated by substtutng or P and P opt n Eqn (), to yeld where k Clock Power Savng x = (3) + k NregCoverhead k = s a parameter that ndcates the N C ops change n master clock net capactance ater mplementng CGC, C and k other = s a parameter that ndcates the N opsc rato o the loads due to the untargeted logc to the targeted logc. Note that k and k are constants or a gven desgn, but are not ndependent o one another. Unlke the prevous expresson or power savng n regsters, the expresson or power savng n clock power can take on negatve values. When x has ts maxmum possble value o, the savngs n clock power has a k value. Ths means that the crcut wll consume more + k clock power ater optmzaton. By keepng the overhead capactances low, k can be mnmzed sucently to keep the addtonal power mnmal. 5.3 Overheads n CGC The overheads n CGC are n re-codng the state machnes, the RZ pulse generators, and n the shadow lp-. As an estmate or the overhead, we use the number o addtonal lp- that have to be added to the desgn or CGC. The overhead depends on the nature o the state machnes n the desgn beore mplementng ths scheme. I the ntal desgn had a Moore state machne wth N states states as the controller, and n out o these states wrte to at least one regster, then ater re-codng the state 4

5 machnes, the number o lp- needed to mplement the state machnes s gven by N states, n = N states N sm = n + log ( N states n), n < N states For each state that can wrte to at least one regster, we would need an RZ pulse generator and a shadow lp- n the worst case. The total number o lp- N desgn opt n the desgn ater mplementng ths scheme s N = N N desgn opt sm + 3Nstates + N N desgn opt = 3n + log ( Nstates n) + N where N s the number o lp- n the target logc. lp In the orgnal desgn the total number o lp- assumng bnary encodng or the states s gven by N desgn = N lp + log N states The overhead as a racton o the lp- n the orgnal desgn s gven by N desgn opt N desgn Overhead = N 3n + = desgn log( Nstates n) log Nstates N + log Nstates As ndcated by ths expresson, the overhead ncreases roughly lnearly wth the number o states that wrte to at least one regster. Ths expresson also ndcates that ths scheme targets a large number o regsters n the crcut, N n the lp denomnator would be large and the overheads can be kept low. Ths also has the postve eect o ncreasng the power savngs. When the state machnes n the orgnal crcut are Mealy State machnes, the rst step n order to mplement CGC s to convert t nto a Moore State machne. Ths step can ntroduce extra overhead. In general, a Mealy State machne wth N states (4) states and q output symbols can be converted nto a Moore State machne wth N states q + states []. The overhead n ths can be computed as earler. The expresson or the overhead n ths case s gven by 3n + log ( Nstatesq n) ( Nstates ) Overhead + log = (5) N + log( Nstates ) In addton to the area overhead derved above, ths scheme ncurs a small tmng penalty on account o skew ntroduced on each control clock, as descrbed n secton Results In ths secton we dscuss results obtaned ater mplementng CGC n an expermental processor. The processor has an nstructon set based on the DLX descrbed n [4]. The processor s coded n VHDL usng RTL constructs. The processor desgn has been parttoned nto the ollowng blocks: Regster Fle, ALU, Decode, Fetch and Control. The desgn s lp- based and strctly synchronous, wth all lp- clocked by the same clock sgnal. The control state machne has sx man states. A gate level netlst was syntheszed wth a commercal synthess tool Desgn Compler. The target standard cell lbrary has a mnmum eature sze o 0.8 µ. The cells n the lbrary have been characterzed or operatng voltages n the range Volts. Power analyss o ths netlst was done usng a commercal tool DesgnPower wth actvty normaton obtaned rom netlst smulatons. Smulatons were carred out usng a commercal tool Modelsm. The testcases chosen or smulaton had been wrtten so as to cause maxmum or mnmum actvty on the program and data memory paths o the processor. Several nstances o the processor were then syntheszed wth CGC mplemented at the RTL level n each block o the processor. For all nstances o the processor, we used the same tmng constrants or synthess. The operatng voltage was set to.95 Volts (to estmate worst case power) and all desgns were clocked at 00Mhz or power analyss. The same test cases were executed on each nstance o the processor. The average power consumed by each nstance and the gate counts (n terms o equvalent -nput NAND gates) o each nstance are tabulated n gures 5 and 6 respectvely. In these gures, DLX represents the baselne nstance wthout any power mnmzaton. DLXA s an nstance wth CGC mplemented n the regster le. In addton, DLXB mplements CGC n ts decode block. DLXC mplements CGC n ts Fetch and ALU blocks. DLXD mplements CGC aggressvely or ts regster le and DLXE mplements ths n the dvder. DLXF s an nstance obtaned by aggressve use o Desgn Compler s gated clock synthess. For DLXF, we nstructed Desgn Compler to gate clocks or any regster whose wdth exceeded 5. In DLXA-DLXC, a sngle control clock s used or the entre regster le. In DLXD and DLXE, separate control clocks are used or each regster n the regster le From gure 5, t s evdent that wth aggressve applcaton o CGC, n DLXA-DLXE, sgncant amounts o power (upto 73.5% n ths case) can be saved. One may note that the control power s hgher n crcuts n whch CGC has been appled aggressvely. Ths s due to the act that the control block dsspates the clock power o datapath blocks wth CGC. The hgher control power s also due to the ncreased gate count o the control block. It s also observed that the clock power decreases when CGC s aggressvely appled. Ths s because the datapath blocks derve ther clocks rom the control block, lowerng the capactance on the clock lne. In DLXF, we observe that the Decode block power s nearly the same as n DLX. Ths s due to the act that Desgn Compler depends on the HDL descrpton to denty dle condtons. The tool sometmes loses out on opportuntes or mnmzaton dependng on the HDL codng style used. It s observed that Control block consumes very lttle power n DLXF. Ths s due to act that Desgn Compler can gate clocks n the control blocks as well. Internally, the tool does not dstngush between datapath and control. The tool uses the normaton rom the HDL or the generaton o the gated clock. Fnally we observe that aggressve applcaton o CGC can yeld about 6% hgher power savngs than clock gatng. From gure 6 t s evdent that CGC acheves a reducton n the gate count o blocks n whch t s used. Ths s because because CGC elmnates the multplexers used by datapath regsters to recrculate data when dle. It s also observed that the gate count o the control block ncreases due to the overheads assocated wth CGC. Fnally, Comparng DLXE (an aggressve mplementaton o CGC) aganst DLXF (an aggressve 5

6 Power (mw) Regster Fle Decode Control Other ALU Fetch Clock Number o -nput NAND gates Regster Fle Decode Fetch ALU Control 0 Other Clock Control Fetch Decode ALU Regster Fle Instance Fg 5. Power dsspaton proles o varous DLX nstances. 0 Fetch Control Decode ALU Regster Fle Processor Instance Fg 6. Gate counts o varous DLX nstances. mplementaton o clock gatng) reveals that DLXF requres a hgher gate count. 7. Conclusons In ths paper, we descrbe an area ecent power mnmzaton scheme Control generated clockng (CGC) or mnmzng dynamc power dsspaton o regsters and clock drvers n a synchronous sequental crcut. CGC mnmzes power by utlzng control sgnals generated by s as clocks or the regsters. CGC s a robust method n whch power mnmzaton s acheved wthout the possblty o ntroducng gltches on the clocks. Tmng analyss o a crcut wth CGC s smpler than n crcuts wth gated clocks. CGC preserves the cycle boundares on whch regsters load data thereby allowng reuse o test cases developed or the orgnal desgn wthout any modcatons. CGC s a structured method and can be easly ncorporated nto a synthess tool or automaton. The utlty o CGC has been demonstrated wth a complex example. Reerences. Anantha P. Chandrakasan & Robert W. Broderson, Mnmzng Power Consumpton n Dgtal CMOS crcuts, Proceedngs o the IEEE, Vol 83, No. 4, Apr C. Y. Tsu, M. Pedram & A. M. Despan, Low Power State Assgnment targetng Two- and Mult-level Logc Implementaton, Proceedngs o the ICCAD John E. Hopcrot & Jeery D. Ullman, Introducton to Automata theory, Languages, and Computaton, Addson- Wesley Publshers, John Hennesey and Davd Patterson, Computer Archtecture: A quanttatve approach, nd ed., Morgan Kauman Publshers, J. Montero, S. Devadas & A. Ghosh, Retmng Sequental Crcuts or Low Power, Proceedngs o the ICCAD L. Benn, P. Segel, & G. De. Mchel, Automatc Synthess o Gated Clocks or Power reducton n Sequental Crcuts, IEEE Desgn and Test, wnter L. Benn & G. De. Mchel, State Assgnment or Low Power Dsspaton, IEEE JSSC, vol, No. 5, Mar Massoud Pedram, Power Mnmzaton n IC desgn: Prncples and Applcatons, ACM TODAES Vol., No., Jan M. Aldna, J. Montero, S. Devadas & A. Ghosh, Precomputaton based Sequental Logc Optmzaton or Low Power, IEEE transactons on VLSI systems, Dec Srkanth Rao M and S. K. Nandy, Controller redesgn based clock and regster power mnmzaton, Proceedngs o the ISCAS (to appear), May 000, Geneva, Swtzerland.. Srkanth Rao M, Control generated clockng: A technque or mnmzng power n sequental crcuts, MSc(Engg) thess, Research Report RR-CADL-99-08, Apr 000, CAD lab, SERC, Indan Insttute o Scence.. V. Twar, S. Malk & P. Ashar, Guarded Evaluaton: Pushng Power management to Logc Synthess desgn, Proceedngs o the Internatonal Symposum on Low Power Desgn,