Application of ASIP in Embedded Design with Optimized Clock Management

Transcription

1 Proceedngs of the Frst Internatonal Conference on Informaton DOI: /2018KM41 Technology and Knowledge Management pp ISSN ACSIS, Vol. 14 Applcaton of ASIP n Embedded Desgn wth Optmzed Clock Management Mood Venkanna 1, Rameshwar Rao 2, P. Chandra Sekhar 3 Electroncs and Communcaton Engneerng, Unversty College of Engneerng, Osmana Unversty, Inda. 1 venkatmood03@gmal.com, 2 rameshwar_rao@hotmal.com, 3 sekharp@osmana.ac.n Abstract As the demand for hgh performance computng ncreases, new approaches have to be found to automate the desgn of embedded processors. Smultaneously, new tools have to be developed to short the executon tme consumpton, and smpler desgn resultng n tme to market. These are to be appled for the system archtecture to acheve rapd exploraton n on power consumpton, chp area, and performance constrants. Ths enables nterest n Applcaton Specfc Instructon Processors (ASIPs) desgn and applcaton consderably. It has hgher flexblty as compared to dedcated hardware. The current case study focuses on an ASIP desgn methodology consderng the classcal parameters computatonal performance and area as well as energy consumpton smultaneously. In ths paper, the clock gatng s analyzed and desgned. Further t s optmzed usng Fast genetc algorthm (FastGA). The optmzaton result s shown for ICORE (ISS-core) ASIP for DVB-T acquston and trackng algorthms. Observaton shows a potental of about one order of magntude n savngs of energy for optmzaton. Index Terms Embedded Processor, ASIP, Clock, Optmzaton, FastGA A I. INTRODUCTION PPLICATION-specfc processng elements need modern optmzed embedded systems. ASIPs archtecture for mxed control/data-flow orented taskshas been effectve for medum to low data rate. A number of methodologes have been proposed n the last two decades n ths regard. ASIPs are approprate to mplement embedded systems because these offer hgh energy performance wth hgh programmablty. To desgn hgh performance embedded systems, ASIPs wth very Long Instructon Word found sutable [1-3].In ths case, the Desgn Space Exploraton (DSE) helps to determne the optmal parameters of the archtecture. For small embedded systems, small scalar ASIPs wth specfc nstructons need to be desgned based on the characterstcs of the target systems [4-5]. An embedded system s a computer system whch performs a specfc functon accordng to our gven applcaton requrements wth specfc hardware envronment. Some crtcal applcatons such as automotve desgn, controls desgns (robotc machne), ralways, arcraft, aerospace, DNA Sequencng, neural network, Eye lens desgn and fngerprntng currently workng on embedded technology. Effcent co-desgn technology s requred to reduce the operatonal complexty and challenges of applcaton desgnng and effectve memory desgn s requred to reduce the operatonal complexty of the gven applcaton [6-7]. An Embedded processor evoluton mechansm s requred for an ncreasng number of features at lower power and ntegrated nto a sngle chp. The Embedded system challenge s mplemented wth reducton of power consumpton and ntegraton of heterogeneous systems nto the sngle chp to reduce area, power and delay [8]. An Embedded system conssts of ASICs, ASIP and feld programmng gate array as well as the programmng unt such as the DSP and these processor desgns are used n varous stuatons or tme to market [9-10]. The software envronment mplements applcaton developments and complaton process and hardware unts mplement user logc or behavor synthess [11]. The Hardware sde of desgn most lkely conssts of nterconnecton components such as processors, memores and communcaton unts (buses, output/nput devce I/O nterfaces, sensor, RTOS devces etc.) [12-13]. Embedded systems wth specfc constrants need to take care of Cost, Sze, power and hgh Performances for real tme desgn applcatons. An Embedded system has few basc needs for hgh performance as explaned below. Cost reducton for real-tme desgn mplementaton Short tme span for applcaton executon and Complexty reductve archtectures Runtme-aware archtectures and Deployng tme-analyzable Effectve resource management schemes and runtme aware envronments. Effectve smulaton tools that allow us to make desgn space exploratons and are used for comparsons between dfferent hardware/software desgns [14-15]. Embedded desgn requres a temperature- aware OS soluton for real-tme and hgh-performance systems.effectve compler technology Applcable for hgh- c PTI,

2 160 PROCEEDINGS OF ICITKM. NEW DELHI, 2017 performance computng (HPC) and real-tme embedded computng (EC) world [16]. ASIPs found to be performng better n specfc applcaton that ncludesservo motor control, dgtal sgnal processng (DSP), automatc control systems, cellular phones avoncs, etc [19]. It mantans a balance between two extremes such as general programmable processors and ASICs by Lem et al[20].they offer custom secton avalablty for tme crtcal tasks such as thereal tme multply-adder or DSP and also provdes the desred flexblty vathenstructon-set. Complex applcatons requre moreflexbltyto wthstand desgn errors that ncludes specfcaton changes at later stages. However, an ASIC s normally desgned for specfcbehavor;hencemake the desgn dffcult to change afterwards. Inthsstuaton, the ASIPs can offer the ntended flexblty as compared to the conventonal programmable processors at lower cost. Among several ssues pertanng to the ASIP desgn, ths work ntends to classfy the approaches nvolved for dfferent steps. It surveys the work done so far n the feld of ASIP desgn and hghlghts the mportant contrbutons [21]. II. SYSTEM MODEL AND PROBLEM FORMULATION For smlar task, theasip mplementatons consume more power as compared to the dedcated hardware due to nterconnecton structure overhead and to the processor control actvty. However, the processors are enough flexble and can take any software-programmable task. It creates a trade-off between low-power consumpton and the flexblty. There have been several optmzaton optons to reduce theasip power consumpton such as the clockgatng, ISA optmzaton,logc netlst restructurng, nstructon memory power reducton etc. In some cases dedcated coprocessor are also used. The processor unt contans ppelne unt whch s controlled by DMA crcuts. There are two knds of ppelne commonly used n processor arthmetc ppelne and nstructon ppelne. An nstructon ppelne uses the nstructon cycles overlappng fetch, decode, and execute phases for ts operaton. Currently, long nstructon memory plays a domnant role n the ppelne mechansm (Fg. 3). Varous Ppelne mechansms are used by varous processor developer companes such as ARM, Intel and Motorola etc. accordng to ther performance. Instructon set archtecture plays a domnant role n memory storage due to code optmzaton. Fg. 1: Basc unts for embedded system Fg.1 shows the Basc unts for embedded system. Embedded system desgner used varous mechansms for processors developments have dfferent desgn metrcs and analyzed varous processor archtectures whch s used n our real-tme envronments or System on chp such as GPP, DSP, ASIP and ASICs. The clock gatng reduces the power usng the gatng sgnals of regsters n whch the sgnals are obtaneda regster s executon condtons.to ppelne regster power consumpton n Very Long Instructon Word (VLIW) ASIP large-scale data path can be reduced by extractng the mnmum executon condtons automatcally durng ASIP generaton procedures. Results reveal a drastc reducton n VLIW ASIPs power consumpton and wth small clock gatng overheads. Clock gatng reduces the power consumpton because of followng. Frst, t shuts off the supply to flp flops by the redundant clock when not requred n calculaton stages. Second, t reduces the power of clock trees n case the clock gate s placed on hgher level of the tree. But, the placed gates n clock gates results n dffcult clock tree synthess due an ncrease n clock skew. Smlarly, the operand solaton can block unwarranted sgnal swtchng of combnatonal logcs and thus reduces power consumpton although t s assocated wth many crcut overheads. For automatc ASIPs generaton, scalar ASIP and VLIW ASIP methods have been proposed [18]. Wth an ADL also known as the Mcro Operaton Descrpton (MOD), these methods help desgn and development of ASIPs. A. Gatng Methods Currently there are a number of automatc clock gatng nserton technques and tools are avalable. Among these, the Power Compler has been very popular and commercally used tool whch automatcally nserts the desgnated gates nto the regsters clock lnes [22]. Snce, ths tool s unable to extract the regsters gatng sgnals,the clock effcency depends on the desgners. The toolcompels the desgners to derve the gatng sgnals from complex RTL manually for addtonal power reducton whch s tme consumng, as VLIW ASIP has hundreds of ppelne regsters. Ths makes t unsutable to explore the desgn

3 MOOD VENKANNA ET AL.: APPLICATION OF ASIP IN EMBEDDED DESIGN WITH OPTIMIZED CLOCK MANAGEMENT 161 space. Thus, t s essental to extract the gatng sgnals automatcally. Fnte state machne based clock gatng method need feedback-free ppelnes to extracts the regsters gatng sgnals. Snce the method s not sutable for ppelne processors hence are not appled for generaton of VLIW ASIP. B. Clock Desgn Mechansm for Memory Implementaton The system performance s also strongly affected by varous factors besdes ts nstructon set, the tme requred to move nstructon & data between the CPU and memory components. The clock system s desgned for mplementng memory operaton executon. The average cycle s desgned for mplementng the clock cycle requred per machne nstructon s a measure of computer performances. The clock sgnal has varous characterstcs such as clock perod, Clock pulses, leadng and tralng edge. Clock behavor depends on upon the behavor of clock elements wth memory archtecture wth ts schedulng approaches. Clock effect can be analyzed by followng parameters such as Set up tme, Hold tme and Propagaton delay tme. TheASIP desgn wth ADL has four basc functons such as the (a) archtecture exploraton (b) archtecture mplementaton (c) applcaton software desgn (d) system ntegraton and verfcaton. Fg. 2: ASIP Processng Technque The throughput of a system depends on thedelay tme of the slowest sub-crcut whch s decded by the storage regster.in a larger synchronous crcut, the combnatonal logc unt F s connected to two dynamc D-FFs. The nput D-FF supples sequental, clock-synchronous data to the subcrcut. The results of the sub-crcut are accepted by the output D-FF sequentally and clock-synchronously, as wth the nput data, and are then passed on. A dynamc D-FF s a smplfcaton of the quas-statc D-FF of Fg.2. Ths smplfcaton s an approprate soluton for contnuously clocked MOS crcuts wth a clock frequency n the MHZ range. A non-overlappng, two-phase clock s assumed. Such clockng s partcularly safe and s often used wthn ntegrated crcuts [14], [17]. The clock perod must fulfl the followng requrement: CLK ³ D, 2 D, F, D 1 1, 2 T T T T T (1) Here, 2 s the delay tme of a pece of data between the transmsson gate clocked by 2 and the nput of the sub-crcut F. TDF, s the delay tme of the sub-crcut F 1 s the delay tme between the output of F and the nput of the nverter behnd the transmsson gate clocked by, 1. T s the clock pause between 1 and 2. It s to 1 2 be noted that the delay tmes 2 and 1 depend on the characterstcs of the sub-crcut. The nput capactance of F nfluences and the output resstance of F nfluences 1 2.The total delay resultng from the D-FFs s gven by T T T T (2) D, FF D, 2 D, 1 1, 2 A correspondng delay can also be gven for other clock systems. In sngle phase clock systems wth edge trggered FFs, for example, the sum of the hold and set-up tme must be substtuted nto the equaton. In the followng, a smplfed representaton of synchronously clocked functonal unts wll be used. Here, the D-FFs are symbolzed by a smple dot n the wrng. The delay between the nput and the output of the D-FF can be descrbed by a delay operator wth delay D. In case of word orented processng the delay operator represents a regster of D-FFs. The achevable throughput RT of a system n bts per unt tme s proportonal to the clock rate,.e. 1 RT (3) T CLK On the other hand, the clock perod that determnes the maxmal throughout s specfed by the least favorable subcrcut. T max T T (4) CLK D, F D, FF, For hgh throughout, small delays are essental. Modest delays can be acheved through technologcal measures. By shrnkng the geometrc structures (scalng), the capactances can be reduced, thus achevng a reducton n the delay. The effects of such scalng are dscussed n the lterature [15]. Besdes technologcal measures, crcut technques for ncreasng the throughput are also possble. Varous crcut structures for the mplementaton of elementary operatons were presented n [16]. The alternatves shown demonstrate dverse delay characterstcs. Accordng to eq. 4, the maxmal delay of the sub-crcuts s to be mnmzed. Ths means that only the slowest module must be mproved. For example, n a sgnal processng task usng multple addtons and multplcatons, only the multpler would have to be optmzed n ts propagaton delay. Ths would be pontless for the adder. Thus, archtectural measures for ncreasng the throughput are sought wth whch the domnance of the slowest module can be defeated. Power gatng may be used effectvely to mnmze the statc power consumpton or leakage. It helps to Cut-off power supply to nactve unts/components

4 162 PROCEEDINGS OF ICITKM. NEW DELHI, 2017 Reduces leakage Fg. 3: Modfed Clock Gatng Method III. RESULTS AND DISCUSSION We evaluated ths work on a reconfgurable processor presented n Henkel et al. [23] that we extended for executon wth hard real-tme guarantees. In ths the optmzaton of power n ICORE has been ncrementally acheved. Ths allows us to evaluate each optmzaton step quanttatvely. Power compler of Synopsys wth backannotated toggle actvty from gate level smulatonshas been used for measurement.table 1provdes both the area and the tmng delay as the optmzed,unoptmzed, and the orgnal descrpton of ICORE from Infneon and ISS68HC11 from Motorola. Table 1. Performance Comparson Archtecture Type Area n terms of Gates Clock Perod n nsec ISS68HC (unopt.) ISS68HC11 (opt.) Orgnal M68HC11 ICORE (unopt.) ICORE (opt.) ICORE handwrtten Fg. 4: Memory area mplemented wth resources Reducble flow mechansm and operatonal optmal condton Fg. 5:Graph of ftness functon usng FastGA IV. CONCLUSION AND FUTURE WORK In ths work a novel attempt s made to estmate the WCET of a program. In ths process, fve key steps are dentfed for the ASIP desgn. We have surveyed the research done and performed the classfcaton of the approaches n every step durng the synthess process. The estmaton of the performance s based on ether the scheduler based or smulaton based method. Instructon set s generated correspondngly ether usng the synthessor the selecton process. The code has been syntheszed ether usng the retargetable code generator or usng the custom generatedcompler. However, even n case of a number of approaches used n formulaton of every key steps, these methods has the lmt n explorng the target space archtecture. Use of ntegraton may support chp memory herarches and these are not explored n an ntegrated way. Smlarly ssues related to ppelned ASIP desgn and pertanng to low power ASIP desgn has not been matured yet. It has been concluded that the processor synthess problems and retargetable code generaton have been used for solaton process. REFERENCES [1] R. Whte, F. Muller, C. Healy, D. Whalley, and M. Harmon, Tmng Analyss for Data Caches and Set-Assocatve Caches, n Proc. 3rd IEEE Real-Tme Technology andapplcatons Symposum (RTAS 97), Jun 1997, pp [2] J. Engblom and A. Ermedahl, Ppelne Tmng Analyss Usng a Trace-Drven Smulator, n Proc. 6th Internatonal Conference on Real-Tme Computng Systems and Applcatons(RTCSA 99). IEEE Computer Socety Press, Dec1999. [3] M. Arnold and H. Corporaal, Desgnng doman-specfc processors, In Proc. Codesgn Symposum [4] A. Alomaryet al., PEAS-I: A hardware/software co-desgn system for ASIPs, In Proc. EURO-DAC [5] J. Van Praetet al., "Instructon set defnton and nstructon selecton for ASIPs," In Proc. HLS Symposum [6] N. Clark, H. Zhong and S. Mahlke, Processor Acceleraton Through Automated Instructon Set Customzaton. In Proceedngs of the 36th annual IEEE/ACM Internatonal Symposum on Mcroarchtecture (MICRO 36), [7] R. Klemm, J. P. Sabugo, H. Ahlendorf and G. Fettwes, Usng LISATek for the Desgn of an ASIP core ncludngfloatng Pont Operatons, Techncal report, [8] R. R. Hoare et al., Rapd VLIW Processor Customzaton for Sgnal Processng Applcatons Usng Combnatonal Hardware Functons. EURASIP Journal on Appled Sgnal Processng, vol ID 46472,

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