Power-Constrained Test Scheduling for Multi-Clock Domain SoCs

Transcription

1 Power-Constraned Test Schedulng for Mult-Clock Doman SoCs Tomokazu Yoneda, Kmhko Masuda and Hdeo Fujwara Graduate School of Informaton Scence, Nara Insttute of Scence and Technology Kansa Scence Cty, , Japan {yoneda, SHARP CORPORATION Abstract Ths paper presents a wrapper and test access mechansm desgn for mult-clock doman SoCs that conssts of cores wth dfferent clock frequences durng test. We also propose a test schedulng algorthm for mult-clock doman SoCs to mnmze test tme under power constrant. In the proposed method, we use vrtual TAM to solve the frequency gaps between cores and the, and also to reduce power consumpton of a core durng test whle mantanng the test tme of the core. Expermental results show the effectveness of our method not only for mult-clock doman SoCs, but also for sngle-clock doman SoCs wth power constrants. keywords: mult-clock doman SoC, test schedulng, test access mechansm, power consumpton 1 Introducton The systems-on-chp (SoC desgn strateges help us to reduce the tme-to-market and desgn cost for new products sgnfcantly. However, testng of SoC s a crucal and tme consumng problem due to the ncreasng desgn complexty[1]. Therefore, the goal s to develop technques for wrapper desgn, test access mechansm (TAM desgn and test schedule that mnmzes test applcaton tme under gven constrants such as the number of test pns and power consumpton. A number of approaches have addressed wrapper desgn [2, 3, 4] whch are IEEE 15 [5] complant. Smlarly, several TAM archtectures have been proposed such as TestBus [6, 7], TESTRAIL [8], transparency based TAM [9, 1, 11]. Moreover, many approaches for test schedulng problem have been proposed [12, 13, 14, 15, 16, 17]. However, these prevous approaches are applcable only to sngle-clock doman SoCs that consst of embedded cores workng at the same clock frequency durng test. Today s SoC desgns n telecommuncatons, networkng and dgtal sgnal processng applcatons consst of embedded cores workng wth dfferent clock frequences. The clock frequency of some embedded cores durng test s lmted by ts scan chan frequences. On the other hand, other cores may be testable at-speed n order to ncrease the coverage of non-modeled and performance-related defects. The atspeed testable cores mght be non-scan desgned sequental crcuts and requre functonal vectors or ordered test sequence at the rated clock frequency. Moreover, there also exsts a frequency gap between each embedded core and used to test the SoC. From these facts, we conclude that the prevous approaches have the followng two problems: 1 n the case when test clock frequency of a core s hgher than that of, the cannot provde test sequences at the same speed of the test clock frequency of the core, and 2 n the case when test clock frequency of a core s lower than that of, testng of the core by lowerng the frequency of does not make use of capablty effectvely. Therefore, t s necessary to develop a technque that can solve the above problems for the mult-clock doman SoCs. Recently, vrtual TAM based on bandwdth matchng [18] has been proposed n [19] to ncrease capablty when the clock frequency of a core s lower than that of. Xu et al. extended the vrtual TAM technque to the mult-frequency TAM desgn to reduce the test tme for the sngle-clock doman SoCs n [22]. Moreover, a wrapper desgn for cores wth multple clock domans was proposed n [2, 21] to acheve at-speed testng of the cores by usng vrtual TAM technque. However, the test schedulng problem for the mult clock doman SoCs s not addressed n these lteratures. To the best of our knowledge, ths paper gves a frst dscusson and a formulaton of the test schedulng problem for mult-clock doman SoCs. We present a wrapper and TAM desgn for mult-clock doman SoCs and propose a test schedulng algorthm to mnmze test tme under power constrant. In the proposed method, we use vrtual TAM for each core to solve a frequency gap between each core and a gven whle the approach n [22] uses a vrtual TAM for each test bus (.e., all the cores assgned to the same test bus must be tested at the same frequency. Therefore, the proposed method n ths paper has more flexblty for the test schedulng. Moreover, we also use vrtual TAM n order to reduce the power consumpton of the cores durng test. Therefore, the proposed method s effectve for the powerconstraned test schedulng. Expermental results show the effectveness of our method not only for mult-clock doman SoCs, but also for sngle-clock doman SoCs wth power constrants. The rest of ths paper s organzed as follows. We dscuss mult-clock doman SoCs n Secton 2. Secton 3 shows a power-conscous vrtual TAM technque. After formulatng /D6 26 EDAA

2 test source wrapper core 1 (c 1 scan-chan1 scan-chan2 f = 25MHz test snk wrapper (c 3 freq(c f f m bts m bts freq(c core c freq(c 1 =25MHz atspeed(c 1 = no wrapper (c 2 freq(c 2 =5MHz atspeed(c 2 = yes scan-chan1 scan-chan2 scan-chan3 scan-chan4 freq(c 3 =5MHz atspeed(c 3 = no MCDS n bts f TDM (a f < freq(c f n freq(c freq(c bts core c Fgure 1. Mult-clock doman SoC. a test schedulng problem for mult-clock doman SoCs n Secton 4, we present a power-constraned test schedulng algorthm n Secton 5. Expermental results are dscussed n Secton 6. Fnally, Secton 7 concludes ths paper. 2 Mult-Clock Doman SoCs Ths secton descrbes the formal notaton we use to model the mult-clock doman SoC under test. An example of an SoC s shown n Fgure 1 where each core s wrapped to ease test access. Test pattern source and test response snk are mplemented off-chp as an. The SoC can be modeled as a mult-clock doman SoC, MCDS =(C, R, P max, where: C = {c 1,c 2,..., c n } s a set of cores; Each core c s characterzed by: freq(c : maxmum test frequency of core c C; power(c : power consumpton of core c C at test frequency freq(c ; atspeed: C {yes, no}: at-speed test requrement R = {R 1,R 2,..., R n } s a set of wrapper lsts; Each wrapper lst R s characterzed by: R = {r 1,r 2,..., r j } s a set of wrapper desgns for core c ; Each wrapper desgn r j s characterzed by: pn(r j : number of pns to test core c wth j- th wrapper desgn ; cycle(r j : number of clock cycles to test core c wth j-th wrapper desgn; P max : maxmum allowed power at any tme; We consder that an SoC conssts of the maxmum allowed power consumpton and cores workng at dfferent test frequences. However, we assume that each core has been desgned wth sngle-clock doman durng test. For each core, a maxmum test frequency and a power consumpton at the gven maxmum frequency are gven. Each core also has an nformaton about the requrement of at-speed testng. atspeed(c =yes means that c must operate at freq(c durng test (.e., we cannot change the test frequency of c for test schedulng. atspeed(c =no means that c can be tested at lower frequences than freq(c (.e., we can decrease the test frequency of c for test schedulng. Moreover, each core has a wrapper lst that conssts of possble wrapper desgns for the core. Each wrapper de- TDdeM (b f > freq(c Fgure 2. Test data multplexng/de-multplexng. sgn has a number of test pns and a number of clock cycles requred to test the core wth the wrapper desgn. The test tme for c workng at freq(c can be calculated as cycle(c / freq(c. 3 Vrtual TAM for Power Mnmzaton The frequency gaps between and cores can be solved by usng vrtual TAM technques based on bandwdth matchng. When freq(c (clock frequency of core c durng test s hgher than f AT E (clock frequency of (Fg. 2(a, we nsert a TDM (test data multplexng crcut between outputs and the core nputs, and multplex freq(c /f AT E m TAM wres at f AT E nto m vrtual TAM wres at freq(c. On the other hand, when freq(c s lower than f AT E (Fg. 2(b, we nsert a TDdeM(test data de-multplexng crcut between output and the core nputs, and de-multplex n TAM wres at f AT E nto n f AT E /freq(c vrtual TAM wre at freq(c.to observe test responses, we need to nsert TDM/TDdeM between the core output and nputs n the smlar fashon. In ths paper, we also utlze vrtual TAM technque to reduce power consumpton of a core whle mantanng the same test tme of the core. The dynamc power P (k (whch s the domnant source of power consumpton n CMOS crcuts consumed n the crcut on applcaton of consecutve two test vectors (V k 1,V k s as follows [23]. P (k =1/2 f VDD 2 C S (k (1 Here, f s the clock frequency, V DD s the power supply voltage, C s the output capactance at node and S (k s the number of swtchngs provoked by V k at node. From the equaton(1, we observe that the power consumpton of a core durng test can be reduced by lowerng ts test frequency. However, ths ncreases test tme of the core proportonally to the power reducton rato. Here, we nsert TDdeM crcut between the outputs and the core nputs. Then, more vrtual TAM wres become avalable for the core, and test tme can be reduced. In the best case, we can acheve the same test tme wth 5% reducton of power consumpton for a core by usng the above power-conscous vrtual TAM technque. For example, we consder the wrap-

3 Table 1. Power-conscous vrtual TAM for core7 n d695. frequency(mhz # vrtual TAM wres test tme(µs # cycles per desgn for core7 n d695 from ITC 2 SoC benchmarks [24]. Table 1 shows that we can acheve a 5% power reducton wth an 1.4% test tme overhead by decreasng the frequency from 5MHz to 25MHz and ncreasng the number of vrtual TAM wres from 1 to 2. 4 Problem Formulaton We formulate the power-constraned test schedulng problem for mult-clock doman SoCs P mcds that we address n ths paper as follows. Defnton 1 P mcds : Gven a mult-clock doman SoC MCDS, the number of avalable test pns and the clock frequency of f AT E, s there a test schedule for MCDS that satsfes all the followng condtons? 1. the total number of test pns used at any moment does not exceed, 2. the total power consumpton used at any moment does not exceed P max, 3. each core satsfes at-speed test requrement (.e., f atspeed(c = yes, c must be tested at freq(c. Otherwse, c can be tested at frequences lower than freq(c, 4. the overall SoC test tme s mnmzed If there s such a test schedule, determne a wrapper desgn and test frequency of each core for the test schedule. 5 Schedulng Algorthm Ths secton presents a heurstc algorthm for P mcds that conssts of the followng three stages: 1 testablty analyss, 2 test schedulng at tme for cores wth large amount of test data, and 3 test schedulng based on Best Ft Decreasng (BFD heurstc [25] for remanng cores. The example of the generated test schedule s shown n Fgure 3. The shaded cores and the unshaded cores n Fgure 3 are scheduled n stage 2 and stage 3, respectvely. The followng subsectons descrbe the detals of each stage. 5.1 Testablty Analyss (Stage 1 If MCDS cannot satsfy the followng two condtons for the gven parameters: f AT E and, then there s no soluton for P mcds. For each c C such that atspeed(c =yes, [power lmtaton] P max power(c (2 [pn lmtaton] mn(pn(r j freq(c /f AT E (3 j For a core c such that atspeed(c =yes, we cannot change the test frequency freq(c and power consumpton power(c durng test. Therefore, the core that can- #pn cores : scheduled n Stage 2 W cores : scheduled n Stage 3 max core 1 core 5 c o r e 8 core 1 core 7 test tme Fgure 3. A test schedule example. not satsfy equaton(2 exceeds a gven power lmtaton even f t s tested alone. Moreover, as explaned before, TDM/TDdeM crcuts can be unquely determned when f AT E, a wrapper desgn r j and a test frequency for c are gven. Therefore, the core that doesn t satsfy equaton(3 cannot be assgned enough wrapper pns to acheve at-speed test at freq(c. 5.2 Test schedulng at tme wth mnmum test frequency (Stage 2 Ths stage conssts of the followng three steps. Step 1: determne a wrapper desgn and test frequency for each core Man dea n ths step s to ncrease test concurrency for power-constraned test schedulng by lowerng the test frequences of cores whch do not requre at-speed test. For each core c, we determne a wrapper desgn r test and a multplcty m c such that 1. T cycle(r test /(freq(c /m c, 2. pn(r test f AT E /(freq(c /m c, 3. pn(r test s maxmzed, and 4. m c s maxmzed. Here, lower bound T on the SoC test tme s defned as follows. T =max{max(t c,totaldata/(wmax fat E} (4 Lower bound T c on the core test tme and TotalDateare defned as follows. T c = cycle(r j/freq(c s.t. 1. pn(r j s maxmzed, and 2. pn(r j f AT E /freq(c. (5 TotalData = pn(r j cycle(r j s.t. pn(r j s mnmzed. (6 Then, we determne test frequency fc test for c as follows. { fc test freq(c /m = c f atspeed(c =no (7 freq(c f atspeed(c =yes Step 2: determne cores whch start ther tests at tme Frst, we sort cores n the descendng order based on ts T c. Then, we schedule a core c n the above order at tme wth wrapper r test and test frequency fc test. Ths process repeats untl 1 the power consumpton at tme (P does not exceed P max, 2 the pn usage at tme (W does not

4 power P max power P max T test tme (a power vs test tme #pn T test tme (b pn vs test tme Fgure 4. Test schedule after Step 2. #pn T test tme (a power vs test tme after re-calculatng test frequences T test tme (b pn vs test tme after re-desgn wrappers Fgure 5. Test schedule after Step 3. exceed, and 3 T c s less than T / C. Here, C denotes the number of cores n the SoC. The thrd condton can prevent us from schedulng cores wth small amount of test data to tme. Instead of schedulng such small cores at tme, Step 3 re-desgns wrappers and re-calculates test frequences for the cores scheduled n ths step to reduce the overall test tme of the SoC. Fgure 4 shows a current test schedule generated after Step 2. In Fgure 4(a, the horzontal axs denotes the test tme, and the vertcal axs denotes the power consumpton used n each test tme. In Fgure 4(b, the horzontal axs denotes the test tme, and the vertcal axs denotes the number of test pn used n each test tme. Step 3: re-calculate test frequences and re-desgn wrappers for cores scheduled at tme There exsts a case where P (power consumpton at tme does not reach P max after Step 2 (Fg. 4(a snce Step 2 stops the above three condtons. In ths case, we fnd a core c that satsfes all the followng condtons. 1. cycle(r test /fc test s maxmzed (8 2. m c > 1 (9 3. P max P power(c {1/m c +1/(m c 1}(1 4. P max /2 power(c /(m c 1 (11 If there exsts such a core c, we update m c to m c 1, and reduce the test tme of c by ncreasng f test c accordng to equaton (7. The fourth condton (equaton(11 can prevent one core from domnatng power consumpton, and help us to ncrease the test concurrency at tme. Ths process repeats untl 1 P does not exceed P max and 2 there exsts a core that satsfes the above condtons. Fgure 5(a shows a result where we apply ths process to the current schedule generated after Step 2 corresponds to Fgure 4. In ths fgure, frequences for, 3, 4 and 6 are ncreased. Consequently, the test tme for these cores are reduced. #pn s 1 s 2 t 5,3 t 5,1 t 5,2 s 3 core 5 test r schedule based on BFD 5,4 s 4 s t 5,4 5 t 5,5 test tme Fgure 6. An example of test schedulng for core 5. Smlarly, there exsts a case where W (pn usage at tme does not reach after Step 2. In ths case, we fnd a core c wth maxmum test tme, then assgn 1 test pn to c. Ths process repeats untl W does not exceed. Fgure 5(b shows a result where we apply ths process to the current schedule correspondng to Fgure 5(a. 5.3 Test schedulng for remanng cores based on BFD (Stage 3 In ths stage, we determne a test schedule for the remanng cores based on BFD heurstc. Frst, we pck a core c n the descendng order based on T c. Then, we fnd the best start tme, wrapper desgn and test frequency for c such that the total test tme of the gven SoC s mnmzed as follows. 1. Let S be a set of start tme canddates that conssts of the end tme of scheduled cores n the current schedule. For each canddate s S, we calculate avalable power consumpton P s and avalable test pn W s from the current schedule. 2. For each canddate s S, (a Determne a maxmum test frequency fc test,s such that power(c fc test,s /freq(c does not exceed P s. (b Determne a wrapper desgn r,s test such that 1 pn(r,s test does not exceed W s f AT E /fc test,s and 2 pn(r,s test s maxmzed. (c Calculate the end tme t,s when c starts ts test at tme s wth wrapper r,s test at frequency fc test,s. at frequency fc test,s such that 1 t,s s mnmzed and 2 the test of c does not overlap the tests of cores already scheduled n the current schedule. Fgure 6 shows an example of the test schedulng for core 5. Here, a set of start tme canddates S conssts of fve elements: s 1,s 2,s 3,s 4,s 5. For each canddate s S, we calculate a end tme t 5,s by determnng a test frequency 3. Schedule c at tme s wth wrapper r test,s fc test 5,s and a wrapper desgn r5,s test shown as a rectangle n Fgure 6. In ths example, core 5 s scheduled to start ts test at tme s 4 wth a wrapper r5,4 test at frequency fc test 5,4 snce the end tme t 5,4 has a mnmum value. Ths process repeats untl all the remanng cores are scheduled n the descendng order based on T c. Through the above processes, we can generate a fnal test schedule.

5 6 Expermental Results In Secton 6.1, we show expermental results for a multclock doman SoC wth power constrant. Secton 6.2 presents expermental results for sngle-clock doman SoCs wth power constrant ( d695 and h953 from ITC 2 SoC benchmarks [24] n order to show the effectveness of our approach compared to prevous works. All the expermental results can be obtaned wthn.1 sec. on a SunBlade 2 workstaton (1.5 GHz wth 8GB RAM. 6.1 Results for a mult-clock doman SoC Snce there exsts no approach that has tackled the test schedulng problem for mult-clock doman SoCs, t s dffcult to compare wth prevous works. We have decded to analyze the trade-offs of the proposed method n terms of the number of avalable test pn, the clock frequency of, maxmum allowed power consumpton and test tme for a hypothetcal mult-clock doman SoC. Table 2 shows the mult-clock doman SoC MCDS 1 used n ths experment. Ths SoC conssts of 14 cores. Frst 1 cores are from d695 n ITC 2 SoC benchmarks. flexble( 2 n column wrapper lst denotes that we can desgn any wrapper (wrapper wth any number of test pns by the procedure proposed n [2, 3]. We use the same power consumpton shown n [15], and assume that freq(c =5 MHz and atspeed(c =no for these 1 cores. The wrappers for core 11 and core 12 are already desgned (.e., 64 pns, 32 pns, respectvely. We assume that these two cores are tested at hgher frequences than other cores, and atspeed(c =yes. Core 13 and core 14 are copes of core 7 and core 5, respectvely. However, we assume that these two cores are tested at lower frequences than other cores. For ths SoC, Table 3 shows test tme results when f AT E = 2MHz, 1MHz and 5MHz. In ths table, the test tme results are shown as µsec., and untestable denotes that there exsts no soluton for the gven parameters. In ths SoC, snce core 11 should be tested at 1MHz wth 64 pns, we observe that there exsts no soluton for three cases: 1 f AT E = 1MHz and = 32, 2f AT E = 5MHz and = 32, and 3 f AT E = 5MHz and = 64. We also observe that test tme depends on the product of f AT E and. Therefore, when we use a hgh speed, we can test SoCs wth small number of test pns. On the other hand, even when we use a low speed, we can acheve the same test tme by usng more test pns. From ths results, the desgner can decde the number of test pns and the speed of the test pn consderng the total cost for them. 6.2 Comparson wth other approaches The proposed test data de-multplexng technque s also effectve for the power-constraned test schedulng of the sngle-clock doman SoCs as well as for that of the multclock doman SoCs. In order to show the effectveness of Table 2. An mult-clock doman SoC MCDS 1. core at-speed wrapper lst test freq. power requrement (pns (MHz (unt 1 no flexble( no flexble( no flexble( no flexble( no flexble( no flexble( no flexble( no flexble( no flexble( no flexble( yes fxed ( yes fxed ( no flexble( no flexble( our approach compared to prevous works, we present expermental results for the sngle-clock doman SoCs wth power constrant. We use d695 and h953 from ITC 2 SoC benchmarks [24] as the sngle-clock doman SoCs by assumng that f AT E =5MHz, and freq(c =5MHz and atspeed(c = no for all core c C. Ths s because only these two SoCs have power nformaton n the benchmarks (for d695, we use the same power consumpton shown n [15]. Table 4 shows the test tme results of the proposed method and the prevous power-constraned approaches [15, 16] whch are applcable only to the sngleclock doman SoCs. In ths table, test tme results are shown as the number of clock cycles. NA denotes that the approach s not applcable for the constrant. - denotes that no result s shown for the constrant n the approach. For d695, we observe that the proposed approach can acheve a 6.9% reducton n average test tme compared to [15]. Moreover, for h953, we observe that the proposed approach can acheve the lower bound ( on the SoC test tme [14] under all power constrants. From these results, we conclude that the proposed power-conscous vrtual TAM technque and test schedulng algorthm are also effectve for sngle-clock doman SoCs. 7 Conclusons Ths paper has presented a power-conscous wrapper and TAM desgn for mult-clock doman SoCs, and proposed a test schedulng algorthm to mnmze test tme under power constrant. To the best of our knowledge, a test schedulng problem for mult-clock doman SoCs has been addressed and formulated for the frst tme n ths paper. Moreover, we have presented a technque to reduce power consumpton of a core durng test whle mantanng the test tme by utlzng vrtual TAM technque whch s applcable to both sngle and mult clock doman SoCs. Acknowledgments Ths work was supported n part by Japan Socety for the Promoton of Scence (JSPS under Grants-n-Ad for Scentfc Research B(2(No The authors would lke to thank Prof. Kewal K. Saluja, Mchko Inoue, Dr.

6 Table 3. Test tme results [µs] for mult-clock doman SoC MCDS 1. f AT E = 2MHz f AT E = 1MHz f AT E = 5MHz P max 32 pn 64 pn 128 pn 32 pn 64 pn 128 pn 32 pn 64 pn 128 pn untestable untestable untestable untestable untestable untestable untestable untestable untestable Table 4. Test tme results (# cycles for sngle-clock doman SoCs. SoC P max 32 pn 64 pn 128 pn 3D[15] EA[16] proposed 3D[15] EA[16] proposed 3D[15] EA[16] proposed d695 1 NA NA NA NA NA NA h NA NA NA NA NA NA Satosh Ohtake and members of Fujwara Laboratory (Nara Insttute of Scence and Technology for ther valuable comments. References [1] Y. Zoran, E. J. Marnssen and S. Dey, Testng embedded-core based system chps, Proc Int. Test Conf., pp , Oct [2] V. Iyengar, K. Chakrabarty and E. J. Marnssen, Test Wrapper and test access mechansm co-optmzaton for system-on-chp, Journal of Electronc Testng: Theory and Applcatons, pp , Apr. 22. [3] W.Zou,S.R.Reddy,I.Pomeranz and Y.Huang, SOC Test Schedulng Usng Smulated Annealng, Proc. 21th VLSI Test Symp.,pp ,May 23. [4] E. J. Marnssen, S. K. Goel, and M. Lousberg, Wrapper Desgn for Embedded Core Test, Proc. IEEE Internatonal Test Conference (ITC, pp , Oct. 2. [5] E.J. Marnssen, R. Kapur, M. Lousberg, T. McLaurn, M. Rcchett and Y. Zoran, On IEEE P15 s Standard for Embedded Core Test, Journal of Electronc Testng: Theory and Applcatons, pp , Aug. 22. [6] T. Ono, K. Waku, H. Hkma, Y. Nakamura and M. Yoshda, Integrated and automated desgn-for-testablty mplementaton for cellbased ICs, Proc. 6th Asan Test Symp., pp , Nov [7] P. Varma and S. Bhata, A structured test re-use methodology for core-based system chps, Proc Int. Test Conf., pp , Oct [8] E. Marnssen, R. Arendsen, G. Bos, H. Dngemanse, M. Lousberg and C. Wouters, A structured and scalable mechansm for test access to embedded reusable cores, Proc Int. Test Conf., pp , Oct [9] M. Nouran and C. A. Papachrstou, Structural fault testng of embedded cores usng ppelnng, Journal of Electronc Testng:Theory and Applcatons 15(1-2, pp , Aug. Oct [1] S. Rav, G. Lakshmnarayana, and N. K. Jha, Testng of core-based systems-on-a-chp, IEEE Trans. on CAD, Vol. 2, No. 3, pp , Mar. 21. [11] T. Yoneda, T. Uchyama and H. Fujwara, Area and tme cooptmzaton for system-on-a-chp based on consecutve testablty, Proc. 23 Int. Test Conf., pp , Sep. 23. [12] Y.Huang et al., Resource allocaton and test schedulng for concurrent test of core-based SOC desgn, Proc. Asan Test Symposum(ATS, pp265-27, 21. [13] V. Iyengar, K. Chakrabarty and E. J. Marnssen, On usng rectangle packng for SOC wrapper/tam co-optmzaton, Proc. 2th VLSI Test Symp., pp , Apr. 22. [14] S. K. Goel and E. J. Marnssen, Effectve and Effcent Test Archtecture Desgn for SOCs, Proc. IEEE Internatonal Test Conference(ITC, pp , 22. [15] Y. Huang, N. Mukherjee, S. Reddy, C. Tsa, W. Cheng, O. Samman, P. Reuter and Y. Zadan, Optmal core wrapper wdth selecton and SOC test schedulng based on 3-dmensonal bn packng algorthm, Proc. 22 Int. Test Conf., pp , Oct. 22. [16] Y. Xa, M. C. Jeske, B. Wang and M. Jeske, Usng Dstrbuted Rectangle Bn-Packng Approach for Core-based SoC Test Schedulng wth Power Constrants, ICCAD 3, pp.1 15, Nov. 23. [17] E. Larsson, K. Arvdsson, H. Fujwara and Z. Peng,, Effcent Test Solutons for Core-based Desgns, IEEE Trans. on CAD, Vol. 23, No. 5, pp , May 24. [18] A.Khoche, Test resource parttonng for scan archtectures usng bandwdth matchng, Dgest of Int. Workshop on Test Resource Parttonng,pp , 21. [19] A.Sehgal,V. Iyengar,M.D.Krasnewsk and K. Chakrabarty, Test Cost Reducton for SOCs Usng Vrtual TAMs and Lagrange Multplers, In Proc.IEEE/ACM Desgn Automaton Conference,pp ,Jun.23. [2] Q.Xu and N.Ncolc, Wrapper Desgn for Testng IP Cores wth Multple Clock Domans, In Proceedngs of the 24 Desgn,Automaton and Test n Europe(D,pp ,Feb.24. [21] Q. Xu, N. Ncolc and K. Chakrabarty, Mult-frequency wrapper desgn and optmzaton for embedded cores under average power constrants, Proc. IEEE/ACM Desgn Automaton Conference, pp , 25. [22] Q.Xu and N.Ncolc, Mult-frequency Test Access Mechansm Desgn for Modular SOC Testng, Proc. of IEEE the 13th Asan Test Symposum, pp.2 7, Nov. 24. [23] P. Grard, Survey of low-power testng of VLSI crcuts, IEEE Desgn & Test of Computers, Vol. 19, No. 3, pp , May June 22. [24] E. J. Marnssen, V. Iyengar and K. Chakrabarty, A Set of Benchmarks for Modular Testng of SOCs, Proc. IEEE Internatonal Test Conference (ITC, pp , Oct. 22. [25] M. R. Garey and D. S. Johnson, Computers and Intractablty: A Gude to the Theory of NP-Completeness, San Francsco, CA: W. H. Freeman and Co., 1979.