Power and Area Efficient VLSI Architectures for Communication Signal Processing

Transcription

1 and rea Ecent VLSI rchtectures or Communcaton Sgnal Processng Dejan Markovc, Borvoje kolc, Robert W. Brodersen Berkeley Wreless Research Center, Unversty o Calorna at Berkeley 108 llston Way, Sute 00, Berkeley, C 94704, US bstract methodology or VLSI realzaton o sgnal processng algorthms or wreless communcatons s presented that optmzes archtecture or reduced power and area. When power s lmted, optmal archtecture represents a pont on the best power-area tradeo curve that s obtaned by balancng the algorthm throughput wth the power-perormance tradeo o the underlyng buldng blocks. rchtectural optmzaton s done n the graphcal Matlab/Smulnk envronment, whch s also used or algorthm vercaton. Hardware descrpton language produced by Smulnk enables algorthm emulaton on the FPG and also serves as desgn entry or the chp realzaton. Ths s llustrated on complex mult-dmensonal algorthms such as wdeband MIMO channel decouplng through sngular value decomposton (SVD) usng 16 sub-carrers. Keywords Crcut synthess, desgn methodology, archtecture, adaptve sgnal processng, matrx decomposton, MIMO systems. I. ITRODUCTIO The growng demand or data-centrc wreless connectvty has nspred the development and realzaton o complex sgnal processng algorthms such as those used n multplenput multple-output (MIMO) communcaton. t the same tme, complexty o the devces has been steadly growng due to a need or mult-mode, mult-standard unctonalty. In the past, the growth o complexty o practcally mplemented wreless algorthms has tracked the mprovements provded through the technology scalng. The recent need to support MIMO algorthms has ncreased the need or more power and cost ecent rados. The goal o mplementng a communcatons chp s to meet the unctonalty, throughput and latency o the underlyng standard wth mnmum power and area cost. Most common technques to mnmze power or area (as a domnant measure o cost) are archtectural. However, these technques have been largely heurstc, and there s no establshed systematc way or tradng o throughput, power and area. Wth technology scalng, desgners have more optons n selectng supply voltages and transstor thresholds n addton to varous crcut desgn technques such as the use o sleep modes. ll these technques present some power-perormance tradeo, whch makes archtecture selecton more complcated and also more nterestng. The goal s thereore to develop a methodology that smultaneously mnmzes power and area or gven throughput and latency constrants. In ths paper, varous archtectural technques n the energyarea-perormance space are evaluated n order to mnmze power and area. Pror work appled smlar technques to smple buldng blocks such as FIR lters, [1], n standard VLSI desgn envronment. The methodology presented n ths paper s scalable to large degrees o complexty. Ths work uses the Matlab/Smulnk envronment amlar to both theorsts and mplementers, thus gvng practcal nsght to algorthm developers as well as better understandng o the algorthms by VLSI archtects. II. CHOOSIG OPTIML RCHITECTURE Optmal VLSI archtecture s technology dependent, whch requres characterzaton o man unctonal blocks or speed, power, and area. Ths normaton s used to navgate the archtectural optmzaton procedure that s based on balancng the algorthm throughput requrement wth the capablty o the underlyng basc buldng blocks. Data throughput and latency are man constrants n chp realzatons. Data throughput s nterestng or optmzaton snce, or a gven archtecture, the throughput can be related to the requency o operaton. The key normaton that provdes bass or optmzaton s technology specc energy-delay tradeo n datapath logc as shown n Fg. 1. Ths tradeo exsts because the energy needed to operate dgtal logc gates s related to ther speed. The tradeo s obtaned by adjustng desgn parameters such as gate sze, supply and threshold voltage. Introducng a new technology shts the entre E-D tradeo curve toward lower energy and delay. The archtecture s energy optmal ts E- D tradeo curve has the same slope as the underlyng datapath logc. good tradeo pont s ndcated n Fg. 1. Otherwse the desgn would have a hgh cost n terms o energy or delay. By usng basc concepts o parallelsm and tme multplexng an algorthm can be mapped nto a range o archtectures wth wdely varyng throughput and latency. rchtectural transormatons such as data-stream nterleavng, loop retmng and oldng support more complex operatons wth concurrent or tme-seral executon, whch may also nvolve eedback loops. Energy hgh Energy cost parallelsm good E-D tradeo tme-multplexng hgh Delay cost Delay (~1/Throughput) Fg. 1. Energy-delay tradeo n dgtal crcuts /06/$0.00 (c) 006 IEEE Ths ull text paper was peer revewed at the drecton o IEEE Communcatons Socety subject matter experts or publcaton n the IEEE ICC 006 proceedngs.

2 B (a) reerence B B (c) ppelne (d) reerence or tme-mux. Parallelsm and Tme Multplexng The concepts o parallelsm and tme-multplexng are wellknown n archtecture desgn. Parallelsm combned wth adjustment n supply voltage mproves the energy by slowng down the clock and dstrbutng computaton over several parallel branches. lternatvely, when usng constant clock requences, parallelsm trades o the ncrease n area or hgher throughputs, Fg. (b), []. Tme-multplexng as shown n Fg. (d)-(e) does the opposte: t reduces the area by repeatng computaton on the same hardware unt, but needs a hgher clock rate and hgher supply voltage to mantan the throughput. lternatvely, t can reduce perormance by mantanng the clock rate. Smlar tradeos as that rom parallelsm are avalable through ppelnng, e.g. by nsertng extra ppelne regster between logc blocks and B, Fg. (c). Ppelnng has much smaller area overhead than parallelsm, but s generally more dcult to mplement snce t requres desgn re-parttonng. Basc energy-perormance tradeo n Fg. 1 provdes good nsghts nto technques o ntroducng parallelsm and tmemultplexng. Startng rom a good E-D tradeo pont and movng toward hgher speed (lower delay), we observe a steep ncrease n requred energy. To conserve the energy, parallelsm shts the curve to the let, whch can also mprove the perormance. Tme-multplexng reduces the area when crcut blocks can provde excess perormance. It eectvely shts the curve to the rght, mantanng a good E-D tradeo. B. Data-Stream Interleavng Data-stream nterleavng s another technque to mprove area ecency. In essence t s a way o tme multplexng the data. The case when the algorthm contans a recurson s analyzed as descrbed wth the smple derence equaton: z(k) = x(k) + c z(k 1). (1) The sgnal processng representaton o the derence equaton above s shown n Fg. 3(a). lgorthmc latency o one symbol perod s represented wth explct regster between z(k) and multply block. Symbol rate s dened by clock requency Clk. Ths smple model abstracts away any B (b) parallel (e) tme-multplex Fg.. Basc mcro-archtectural technques: reerence archtecture (a), and ts parallel (b) and ppelned (c) equvalents. Reerence archtecture (d) or tme-multplexng (e). rea overhead s ndcated by shaded blocks. extra latency n add and multply blocks. From the technology perspectve, an bt add operaton s less complex n terms o the number o gates and area than an -by- multplcaton. In order to balance the complexty o datapath logc blocks, add and multply operatons need to have derent latency. more realstc model o Eq. (1) that captures the derent latency o addton and multplcaton s shown n Fg. 3(b). number o a and m ppelne regsters has been assgned to the adder and the multpler, respectvely, to balance the throughput by ncreasng latency. By gong around the loop, the eedback sgnal y(k 1) wll have an ncreased latency o a + m. By ncreasng the clock rate by a actor a + m, the same algorthmc latency can be mantaned. In order to ll the added ppelne wth useul computaton, multple ndependent sgnal streams can be nterleaved onto the same hardware. I the number o ndependent sgnals s greater than a + m, then b = a m o addtonal ppelne regsters s requred to mantan the latency. Interleavng eectvely mproves the area ecency by sharng data-path logc across ndependent streams o data. practcal use o carrer nterleavng s n mult-carrer communcatons, where the ndependent narrow-band subcarrer streams can be tme-nterleaved. C. Foldng x(k) tme ndex k x x x 1 y(k-1) (a) smple model a c Foldng, smlarly to data-stream nterleavng, reduces the area. ssume serally ordered executon o some algorthmc operaton lg as shown n Fg. 4(a). The rst block n the chan takes ndependent data samples y 1 (k), all other blocks take the result rom the prevous block. The concept o oldng s shown n Fg. 4(b), [4]. Input to lg s provded by m a+m+b= * y 1 y y Clk tme ndex k-1 (b) data-stream nterleavng k-a/ z(k) z z z 1 Fg. 3. Concept o data-stream nterleavng (eedback example). y 1 (k) (a) reerence y 1 (k) (b) oldng lg Clk lg lg lg n y (k-1) lg 4 y 3 (k-) y 4 (k-3) y 3 (k-) c y 4 (k-3) b y 1 (k) y (k-1) Fg. 4. Concept o oldng: (a) tme-seral computaton, (b) operaton oldng. Block lg perorms some algorthmc operaton. n z 34 Ths ull text paper was peer revewed at the drecton o IEEE Communcatons Socety subject matter experts or publcaton n the IEEE ICC 006 proceedngs.

3 a multplexer, whch selects external data y 1 or nternally generated results y, y 3, y 4. Durng the rst quarter o the symbol perod, up-sampled and nterleaved data y 1 s used. The output o lg s then olded over n tme, back to ts nput, to compute y, y 3, and y 4. Re-orderng o y 1 samples s needed to algn data at nput n, as shown n the le-chart n Fg. 4(b). Up-samplng the clock n block lg s necessary to sustan external (y 1 ) throughput rate. I lg s a smple eed-orward unt, no addtonal ppelne regsters are needed. In case lg block has nternal eedback loops, addtonal ppelnng s necessary to keep the nternal states. Ths rases the ssue o how to optmally dstrbute ppelne regsters around the loop to maxmze throughput, whch s addressed next. D. Loop Retmng Loop retmng s a technque o dstrbutng ppelne regsters around recursve loops. The goal s to assgn the rght amount o latency to basc unctonal buldng blocks and then dstrbute the ppelne regsters nsde the blocks such that all nternal datapath logc blocks lay at the same pont (shown n Fg. 1) n the energy-delay space. Ths guarantees top-level optmalty. s n the case o nterleavng, addtonal balancng regsters may be needed to ensure equal loop latency n all recursve loops. The approach o loop retmng s llustrated n Fg. 5 on the example o teratve dvder. Ths s a smple example wth two nested loops, but the concepts are general. In a data-low graph representaton o a uncton, a, m, u are the latency o pre-characterzed lbrary blocks. Ths case uses adder (a), multpler (m), and multplexer (u). For each o the loops, the loop constrants are ormulated as n Eq. (). L1 : m + u + b1 = () L : m + a + u + b = For a gven throughput constrant, the soluton o Eq. () s a set o postve ntegers (m, a, u) that corresponds to equal clock perod, addng b 1 and b balancng regsters as needed to satsy loop latency. ccountng or derent latency o lbrary blocks ncely extends the retmng algorthm rom [5]. Retmng strategy can be easly expanded to traverse the layers o herarchy. Each block s characterzed wth latency rom ts prmary nputs () to ts prmary outputs (o) as well as loop constrants nsde the block. Ths normaton s used to derve /o latences and loop constrants at the next level o herarchy. t the top-level, loop constrants rom all lower levels are thus consdered. E. Delayed Iteraton Delayed teraton occurs when majorty o loops have smlar latency, whle only a ew loops need to compute longer. ddng balancng regsters to all the non-crtcal loops to compensate or ths eect would solve the problem, but n a very power and area necent way. The dea s to use delayed teraton n those ew loops and take delayed sample at tme nstant k 1 nstead o takng t at tme nstant k. I ths s algorthmcally possble, requrements or power and area can be much mproved. III. SIMULIK-BSED DESIG FRMEWORK We use Matlab/Smulnk envronment to avod desgn reentry, whch s a standard practce today. desgn s entered n varous orms by derent engneerng teams, resultng n heterogeneous desgn descrptons. lgorthm developers tend to work n Matlab envronment, whch has an array o bult-n unctons convenent or quck algorthm vercaton. C code s another sequental processng entry, whch requres more sophstcated codng sklls. Stll, nether o the representatons captures the archtecture and normaton about samplng rate. The archtectural descrpton s then created by hardware desgners who have to completely re-enter the desgn n HDL. Matlab/Smulnk desgn envronment enables theorsts and mplementers to work together. n algorthm s entered only once s a graphcal block orm, whch provdes tmed datalow representaton o the desgn and abstract vew o desgn archtecture. Wth technology-specc data or speed, power, and area o unctonal blocks, algorthm desgners can explore the mplementaton space whle remanng n Smulnk envronment to very the algorthm. For practcal realzaton, algorthm unctonalty s entered usng hardware-equvalent blocks rom Xlnx lbrary as shown n Fg. 6. Ths lbrary has basc arthmetc operators such as add, multply, sht, mux etc. wth noton o hardware parameters such as latency and word-lengths. The Smulnk descrpton o the block nterconnects s used to generate hardware descrpton or mappng the desgn onto an FPG or hardware emulaton or used by SIC place and route tools or an SIC. Test vectors generated n Smulnk are used or unctonal vercaton n both FPG and SIC lows.. Chp-n-a-Day Desgn Flow Our chp-n-a-day desgn low s llustrated n Fg. 7. We start wth Smulnk desgn descrpton usng Xlnx block-set. ter unctonal vercaton o the desgn, we use an n-house tool or wordlength reducton to reduce area. The loatng-toxed pont converson (FFC) tool mnmzes hardware cost (FPG utlzaton) subject to user dened perormance measures such as MSE error due to quantzaton. Integer part s extracted rom node prolng and range detecton, whle ractonal word-sze optmzaton s done by perturbaton L 1 m a m u Hardware cost estmaton For FFC L Fg. 5. Data-low graph model o teratve dvson. (m, a, u ndcate latency) Fg. 6. Illustraton o FFC-enhanced Smulnk model. 35 Ths ull text paper was peer revewed at the drecton o IEEE Communcatons Socety subject matter experts or publcaton n the IEEE ICC 006 proceedngs.

4 Tech Lb Smulnk/XSG XSG Model Wordlength Opt ISECT HDL Translaton Logc Synthess HDL Smulaton Synopsys Reg Retmng Floorplanng Place & Route Behavoral HDL Mapped HDL behavoral logcal physcal rchtectural Feedback Pre-layout rea Re- synthess Post-layout rea Fg. 7. Smulnk-based Chp-n-a-Day desgn low. theory, [6]. Once bt-true cycle-accurate behavor s obtaned, hardware descrpton language (HDL) or technology mappng s then created usng Xlnx System Generator (XSG) netlst utlty. Ths HDL code can be used or FPG emulaton. To avod re-entry at the HDL level, an n-house tool translates FPG dalect nto ormat supported by commercal mplementaton tools (Synopsys). ter logc synthess that perorms technology mappng, the resultng mapped netlst s vered or unctonalty usng test vectors rom Smulnk. The netlst can be urther optmzed to do regster retmng and logc szng, beore gong to the nal stage o physcal layout synthess, whch s hghly automated. Ths s where desgners oten stop ater obtanng unctonally correct behavor. Makng correct archtectural decsons n Smulnk reles on archtectural eedback rom synthess. Ths s needed as early n the low as possble to avod unnecessary teratons. Frst estmates or area, speed, and power are ed back ater ntal logc synthess, Fg. 7. These results can be rened desred by more accurate estmates rom physcal layout synthess. Ecent algorthm mplementaton s possble wthout requrng much post synthess normaton n Smulnk, wth extensve characterzaton o basc buldng blocks. B. Characterzaton Methodology The goal n characterzaton s to augment XSG block-set wth technology-dependent normaton or speed, power, and area. The complexty o basc and most commonly used lbrary blocks s very low (granularty o add, multply, sht, mux, regster etc.), so ull characterzaton over a range o latency and word-sze parameters s possble. pproach to block-level characterzaton s llustrated n Fg. 8 or cases o add and multply operatons. These two blocks der n arthmetc complexty (relected n latency), so we characterze the speed n terms o cycle tme, whch s a global parameter. Equal cycle tme means that complexty o logc blocks between two ppelne regsters has to be the same n all blocks, whch allows herarchcal expanson around ths block-set. Each pont along the latency vs. cycle tme curve s also characterzed or power and area. Estmates rom Smulnk RTL Synopsys netlst HSPICE Swtch-level accuracy physcal synthess can be urther rened wth swtch-level accuracy, whch s very tme-consumng. Ths s usually done or just a ew blocks, wth results extrapolated to other ponts. The Smulnk block lbrary s also characterzed or area utlzaton o regular FPG abrc (look-up tables, lp-lops), so users can obtan quck estmate o hardware cost n terms o FPG resources. Translatng nto SIC termnology, 10,000 FPG slces 1mm o layout area (~80% layout densty) n 90nm CMOS. Ths relatonshp s obtaned rom lnear extrapolaton o area estmates or several examples that are about an order o magntude apart rom each other n terms o complexty rangng rom smple arthmetc operatons such as add and multply, to complex matrx algorthms. Ths way, we can obtan early estmate o chp area at the Smulnk level. It s common practce n IC desgn to normalze slcon area to the area o a gate rom standard cell lbrary (e.g. -nput D). t hgher levels o granularty, we can also scale the area by the area o some basc operaton such as addton. C. rchtectural Transormatons rea rchtectural optmzaton approach s llustrated n Fg. 9. The goal s to drve the desgn to a desred E-D tradeo pont (e.g. reerence pont), whle mnmzng the area. Ths s done manually by the desgner usng transormatons shown n Fg. 9. For example, tme-multplexng saves the area, but requres ncreased supply voltage whch results n an ncrease n energy per operaton. Parallelsm and ppelnng save the energy through supply voltage scalng, but ncrease the area. It s mportant to realze that there s no unque archtectural soluton snce energy-ecency can be traded or area. latency add rea mult cycle tme (norm.) Fg. 8. Block-level characterzaton (add, mult examples). parallel reerence tme-mux ntl, old ppelne E ntl, old V DD scalng tme-mux reerence ppelne, parallel Fg. 9. rchtectural transormatons n rea-energy-delay space. D 36 Ths ull text paper was peer revewed at the drecton o IEEE Communcatons Socety subject matter experts or publcaton n the IEEE ICC 006 proceedngs.

5 When power s lmted, whch s oten the case n practcal desgns, the area can be mnmzed as ollows. Gven power lmt, desred power ecency s calculated rom the requred amount o unctonalty, usng a known relatonshp between the energy per operaton and supply voltage. Ths determnes the desred operatng pont on E-D lne. Optmzaton procedure then apples approprate transormatons as n Fg. 9 to reach the desred pont. IV. EXMPLES The use o archtectural technques s llustrated on ew examples. We rst look at smple teratve square rootng and dvson, then analyze more complex vector-based operatons ncludng Grahm Schmdt orthogonalzaton procedure and egen-mode decomposton.. Iteratve Square Rootng and Dvson Square rootng and dvson are operatons common to many wreless communcaton algorthms, [7]. Computng the norm requres nverse square rootng, or example. More speccally, n adaptve algorthms nput argument changes relatvely slowly, whch s oten the case n wreless channels. The slow-varyng condton makes the teratve approach attractve or practcal realzaton. mong the algorthms or teratve square rootng and dvson, a method based on ewton-rhapson ormulas s attractve because o ts avorable convergence propertes. Survey o these algorthms can be ound n [8]. Equatons (3) and (4) descrbe nverse square rootng and dvson: xs ( k) xs( k + 1) = (3 xs( k) ), (3) x ( k + 1) = x ( k) ( x ( k)), (4) d d where s the nput argument, x s descrbes nverse square rootng, and x d descrbes dvson. nalyss o error dynamcs reveals quadratc convergence: e s (k+1)= 0.5e s (k) (3 + e s (k)), e d (k+1) = e d (k). In mplementaton terms, ths means that each teraton resolves two bts o accuracy, [8]. The number o teratons requred or algorthms to converge s a uncton o ntal condton and error dynamcs. Table 1 summarzes convergence propertes or a 5% and 50% ntal error, or varous accuraces o the nal answer. Even or very large ntal error o 50%, only ve teratons are needed to acheve accuracy wthn 0.1%. The results n Table 1 also suggest that the error quckly decreases n every teraton. So, the result o current teraton s taken as the ntal condton or the next teraton, under slow-varyng nput the answer can be obtaned n only one teraton. Man archtectural technques appled n ths example are loop retmng (the model n Fg. 5 llustrates dvson) and data-stream nterleavng or multple operands. Loop constrant s equal to the number o nterleaved operands. TBLE I COVERGECE SPEED OF ITERTIVE SQRT D DIV LGORITHMS Target relatve error (%) 0.1% 1% 5% 10% e 0: 50%, # ter (sqrt / dv) 5 / 4 5 / 3 4 / 3 3 / e 0: 5%, # ter (sqrt / dv) 3 / 3 3 / / / 1 d v 1 v v 3 v 4 v 1 v v 3 v 4 (a) drect mappng p/s control memory s/p (b) tme-multplexng usng memory For the case wth 64 narrow-band 1MHz wde sub-carrers, requred throughput s 64MHz. The total (power, area) s estmated at (180µW, 0.07 mm ) or nverse square rootng and (10µW, 0.05mm ) or dvson. Ths example llustrated an archtecture or scalar operatons. In the next example, we analyze vector arthmetc. B. Grahm-Schmdt Orthogonalzaton nother common technque n communcaton sgnal processng s the projecton o a set o vectors onto an orthogonal base. popular approach s the method o Grahm Schmdt orthogonalzaton (GSO). In practce, t s also possble that durng adaptaton, phase shts and magntude changes cause vectors to loose orthogonalty. GSO s then perodcally appled to recty ths. The concept o GSO s llustrated n Fg. 10. Two basc operatons are ndcated n boxes and. In the gure, v 1 -v 4 are complex nput vectors, and v 1o -v 4o s ther orthogonal orm. Due to repettve use o operatons and, ths algorthm s sutable or tmemultplexng the requred data rate s low. Regular tme-multplexng rom Fg. s possble, but ths would result n a szeable nterconnect overhead. Each o the lnes n Fg. 10 represents a complex vector wth bts. For example, a vector o dmenson 4 wth 16 bts or n-phase and quadrature components would mean 4 16 = 18 bts, and ths number s urther multpled by the level o tmemultplexng (4 or block, 6 or block ). So, tradtonal tme-multplexng s not avorable n terms o nterconnect complexty. To reduce wre complexty, tme-multplexng can be mplemented usng memory, as shown n Fg. 10(b). Only 18 bts now need to be exchanged between memory and processng blocks, reducng the routng overhead. Summary o slcon area and routng complexty s gven n Table or cases o drect mplementaton, regular tme-multplexng, and memory based tme-multplexng. Savngs n routng complexty drectly translate to power reducton snce power spent n swtchng o nterconnect wres s also reduced. v 1o v o v 3o v 4o v 1o v o v 3o v 4o 1/sqrt(x x) mult-mult-add Fg. 10. Grahm Schmdt Orthodonalzaton: (a) drect mapped archtecture, (b) memory based tme-multplexng approach. TBLE II SUMMRY OF GSO IMPLEMETTIO FETURES rchtecture Drect mapped Tme-mux (TM) TM w/ memory rea (slcon / FPG).6 mm / 60k 1. mm / 14k 1.0 mm / 14k Total wre length 6.6 m 3. m. m 37 Ths ull text paper was peer revewed at the drecton o IEEE Communcatons Socety subject matter experts or publcaton n the IEEE ICC 006 proceedngs.

6 y (k) de w ( k + 1) = w ( k) + µ [ r r' w ( k) λ w ( k)] λ ( k + 1) = w '( k + 1) w ( k + 1) u ( k + 1) = w ( k) / λ ( k) r out de C. Sngular Value Decomposton s a nal example, we analyze archtecture or estmaton o ndoor wreless channels through adaptve Sngular Value Decomposton (SVD), [9]. The core o the SVD algorthm s n estmaton o U and Σ matrces, summarzed n Fg. 11. s llustrated on practcal example o a 4 4 MIMO system, the algorthm extracts egen-pars (u, λ ) through successve rank reducton, where u s th egen-vector, and λ s th egenvalue, =1-4. Delaton (de) block does successve rank reducton; block computes the egen-pars. Each spatal subchannel ntroduces a par o LSM-de processng elements. Wthn and de blocks there s the nverse square rootng operaton rom the earler example. Step sze µ nsde the block s adaptvely adjusted based on estmated egenvalues, µ 1/λ. Snce egen-values are slowly changng over tme, teratve dvson s employed or adaptve gear-shtng. Ths example s an nterestng case rom the archtectural standpont, as dscussed below. concept o loop retmng n square rootng block s herarchcally expanded to nclude the whole algorthm. arrow-band algorthm descrbed n [9] s extended to wde-band MIMO case by ntroducng multple sub-carrers. Each sub-carrer perorms the same operaton, so data-stream nterleavng s appled to sub-carrers. In ths example, the case wth 16 sub-carrers s assumed (usually not all sub-carrers are needed or channel estmaton; other subchannels can be estmated usng nterpolaton), wth a 1 Msymbol/s data rate on each sub-carrer. The organzaton n Fg. 11 s also convenent or oldng over the antennas or urther area reducton as shown n Fg. 9. By sharng logc blocks common to operatons ndcated n Fg. 11, the algorthm s syntheszed n only 3.5mm o area n a 90nm CMOS technology (or comparson, Smulnk block model takes 35k FPG slces). The arthmetc complexty o ths algorthm s 70 GOPS (1-bt equvalent add). Estmated power consumpton rom logc synthess s 1mW, wth an achevable 50Mbps throughput usng adaptve PSK modulaton. Ths algorthm s relatvely new, so no exstng VLSI realzatons exst or comparson purposes. = r [ w '( k + 1) r w ( k + 1)] / λ ( k) n de n ant-1 ant- ant-3 ant-4 Fg. 11. Egen-mode decomposton algorthm rom [9]. V. COCLUSIO Ths paper presented archtectural technques or power and area ecent VLSI realzaton o sgnal processng algorthms or wreless communcatons. The choce o archtecture s hghly nluenced by the energy-delay tradeos o underlyng technology and data throughput o the algorthm. Hghly automated algorthm mplementaton s possble startng wth the algorthm descrpton n a smple graphcal Matlab/Smulnk envronment. The algorthm can be rapdly evaluated on an FPG or realzed n SIC. Characterzaton o ew basc blocks rom Smulnk hardware lbrary provdes much needed normaton or archtectural desgn early at the Smulnk level, wthout the need or extra teratons. Ths provdes a uned ramework or algorthm developers and mplementers. Several examples o varyng complexty are dscussed to llustrate the methodology or power and area mnmzaton. Lookng orward, t s nterestng to consder the cost o addng lexblty. Two possble drectons are the ollowng: nvestgate lexblty requred or the executon o common operatons across multple standards, and study lexblty o havng mult-unctonalty on a sngle hardware unt. CKOWLEDGMET Ths research s supported n part rom "Robust, Rapd and Wreless Chp Desgn" project sponsored by MRCO on contract #0919 va Carnege Mellon Unversty. The authors acknowledge technology support rom ST Mcroelectroncs and members o the BWRC. REFERECES [1] T. Gemmeke, M. Gansen, H.J. Stockmanns, and T.G. oll, Desgn Optmzaton o Low- Hgh-Perormance DSP Buldng Blocks, IEEE J. Sold-State Crcuts, vol. 39, no. 7, pp , July 004. [].P. Chandrakasan, S. Sheng, and R.W. Brodersen, Low-power CMOS dgtal desgn, IEEE J. Sold-State Crcuts, vol. 7, no. 4, pp , pr [3] D. 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Communcatons, vol. 51, no. 13, pp , ov Ths ull text paper was peer revewed at the drecton o IEEE Communcatons Socety subject matter experts or publcaton n the IEEE ICC 006 proceedngs.