AN1277 MOTOROLA SEMICONDUCTOR TECHNICAL DATA

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1 SEMICONDUCTOR TECHNICAL DATA Order ths document y /D Prepared y: Morrs Smth INTRODUCTION Frequency synthess y use o two loops, wth reerence requences oset rom each other, can provde much ner resoluton or aster hoppng than a sngle loop. Dual PLL ICs are avalale to make compact low current syntheszers usng the technque. Alternatve technques wll e dscussed, the desgn method descred, and examples provded. Ths technque has een used successully wth the Motorola MC dual PLL, provdng 10 Hz step sze, 30 MHz requency range, and swtchng tme o 30 ms. ALTERNATIVE TECHNIQUES DIRECT DIGITAL SYNTHESIS Drect Dgtal Synthess (DDS) composes a sne wave rom dscrete dgtzed samples. Sometmes they are called Numercally Controlled Oscllators (NCOs). Samples or one complete sne wave are stored n read only memory (ROM). A clock outputs a sample every perod. At some requency every sne wave sample wll e used. At a hgher requency every second or thrd sample mght e used. Dgtal to analog converson produces analog levels correspondng to sample codes. The output s low pass ltered. Below 1 Hz resoluton and mcro second swtchng are the advantages o DDS. Spurous sgnal levels and hgh current are the weaknesses. Currently avalale dgtal to analog converters have spurous levels greater than 76 db n the VHF and hgher requency range. Sometmes manuacturers o DDS devces that do not nclude a D/A converter wll gve specs that are computed assumng the D/A s perect. Spurous o 96 db could e quoted under these condtons. Spurous sgnal levels make DDS unsutale or most recever and many transmtter applcatons. Current consumpton s greater than 100 ma. FRACTIONAL N It s possle to have PLL output ncrements smaller than the step sze y use o a ractonal N dvder n the eedack loop. Avalale ractonal N ICs cannot acheve 1000 tmes rato o loop step sze to output ncrement. The oset reerence technque can do t. Fractonal N synthess produces spurous sgnals at the ncrement oset rom the carrer. Oset reerence does not do ths. TRIPLE LOOP PLLs Trple loop PLLs are the most common technque used to otan an output that ncrements n steps much smaller than the step sze o the ndvdual loops. An example s shown n Fgure 1. The output tunes MHz n 10 Hz steps to convert the 0 30 MHz HF spectrum onto a 45 MHz IF. An oset loop operates MHz n 100 khz steps. The ne tune loop covers MHz. A MHz s phase locked to the sum requency o the oset and ne tune PLLs. Fne tune loop requency range s always equal to the step sze o the oset loop. Phase lock n the output loop depends on phase lock n the two other loops, the mxer output eng ntally wthn the lter passand, and output loop eng at a hgher requency than the oset loop. Two stuatons can cause the output loop to latch up wth the other two loops locked. I the s too hgh n requency ntally, lter output s not enough to drve the phase detector. Phase detector output (PDout) goes hgh and pulls the urther rom lock. I the ntally s elow the oset loop, the PDout lne tunes t away rom lock. Lock detect (LD) rom the output loop detects latch up. I the loop hasn t locked wthn a set amount o tme, the sweep crcut moves the through ts operatng range. Durng requency changes, all our transent phenomena can occur. The trple loop PLL s not smple to desgn and produce. OFFSET REFERENCE PLL ADVANTAGES The oset reerence PLL (Fgures 2 and 3) use two loops mxed together to produce an output wth a smaller step sze than the ndvdual loops. The reerence requency derence etween the two phase detectors s the output step sze. Compared to the trple loop, t avods loop latch up, uses one less PLL, and can e desgned wth each PLL operatng ndependently. REV 0 7/96 Motorola, Inc

2 REFERENCE 10 MHz SWEEP LOCK DETECT FILTER 100 khz R 100 OFFSET PLL COARSE TUNE MHz LO OUTPUT PLL MHz RF RF OUTPUT IF N FILTER MHz V R khz MHz R LD FINE TUNE FINE TUNE PLL N MHz (10 Hz STEPS) Fgure MHz Trple PLL Syntheszer R + 1 Hz L H PLL N REFERENCE 2 + Hz MIXER ( ) ( + ) FILTER PLL N OUTPUT R + Hz L H Fgure 2. Output Mxed PLLs 2

3 Varale COMMON CHARACTERISTICS Tale 1. Varale Dentons Denton Step Sze o PLL Base Step Sze Step Sze o Syntheszed Output ( ), ( +), or, Dependng on Conguraton + C ( ) ( + ) Step Sze o PLL Reerence Frequency Mxer Derence Frequency Output Mxer Sum Frequency Output ( )L Low Frequency Lmt o ( ) ( )H Hgh Frequency Lmt o ( ) ( + )L Low Frequency Lmt o ( + ) ( + )H Hgh Frequency Lmt o ( + ) R, R Reerence Dvder Values N, N PLL, PLL Feedack Dvder Values N L, N H N max Lowest and Hghest N Dvder Values Numer o N Dvder Values Used n Addton to N L,, Frequency L, L H, H, Lowest Frequency, Hghest Frequency N, N COUNT SEQUENCE EXCEPT FEEDBACK SUM CONFIGURATION At any output requency that s an nteger multple o the ase step sze (), = L. As the output s stepped up n requency y ncrement (), the N counter s ncremented y one n the sequence N L...N H. N H s the counter value one ncrement () elow the next output requency, whch s an nteger multple o (). Through the N L...N H count sequence, N ether ncrements or decrements y one each tme the output requency s stepped up y (). The term n the output requency equaton whch s multpled y () wll e held constant. At the same tme, the term multpled y () wll e ncreased. N, N COUNT SEQUENCE FEEDBACK SUM CONFIGURATION At any output requency that s an nteger multple o the ase step sze (), = H. As the output s stepped up n requency y ncrement (), the N counter decrements y one n the sequence N H...N L. N L s the counter value one ncrement () elow the next output requency, whch s an nteger multple o (). Through the N H...N L count sequence, N decrements y one each tme the output requency s stepped up y (). The term n the output requency equaton whch s multpled y () wll e held constant. At the same tme, the term multpled y () wll e ncreased. FORMULA LIMITATIONS There are a ew restrctons on PLL and PLL requences whch were made only to smply the ormulas. Both the output and eedack mxed derence requency conguratons requre L > H so that as the output ncreases n requency, the N counter value ncrements. Output requency endponts and ether L or H are nteger multples o the ase step sze (). Ths ensures that at the endponts, s at L or H. s also at L or H or any output requency etween the endponts that can e evenly dvded y (). I the condtons were not met, N could e anywhere n ts count cycle at endponts. Addng terms to the equatons or the two tunng ranges would allow endponts to e multples only o the ncremental step sze (). Reerence requency C s gven or the lowest requency that can produce oth step szes y nteger dvson. The R dvde value wll e one greater than the R dvder. Any reerence requency can e used that s a multple o the C value rom the tale. Snce ether L or H and C dvde y oth step szes, L or H wll e an nteger multple o C. Varale C Tale 2. Formulas For All Conguratons C = R R = 2 R R = N max Desgn Equatons + or C = + 1 N max = 1 N H N H = N L + N max = N ( + ) H L H H L = 2 H = L + 2 ( + ) 3

4 Varale ( ) ( )L ( )H L L H H L OUTPUT MIXED PLLs Tale 3. Output Mxed ( ) Formulas ( ) = (N N) + N Desgn Equatons ( )L = L H + N max ( )H = L L Any requency or whch L > H and L s an nteger multple o C = N L = L ( )H H = L ( )L + N max H L = ( )H ( )L + N max OUTPUT ( ) KEY POINTS (a) RF output s ( ) wth L > H. () C and L dvde evenly y oth step szes. (c) L, H, ( )L, ( )H dvde evenly y. OUTPUT ( ) EXAMPLE The desred requency range s MHz n 0.5 MHz steps usng PLLs wth 2.0 MHz and 2.5 MHz step szes. Reerence requency: C = 2 + = The reerence dvder values are: R = R = + 2 = 10 MHz + 1 = = 5 = = 4 The numer o N counter values used n addton to N L s: N max = 1 = = 3 The requency range o s: H L = 2 = The requency range o s: H L= ( )H ( )L + N max = (2) = 10 MHz 0.5 = 7.5 MHz L and H requences depend on each other. To select values, the equaton or H s solved n terms o L: H = L ( )L + N max = L (2) = L 144 Frequences used or L and H are a tradeo etween phase nose and ease o lterng the mxer products. As L and H ncrease, lterng o mxer products mproves. However, the nose ncreases. The same resonator Q at a hgher requency results n hgher nose or the same oset requency. PLL ICs also produce more nose wth ncreasng requency. L o 500 MHz s chosen. The requency range o s MHz. The requency range o s MHz. To check results, all dvde values and requences are n Tale 4. Tale 4. Output Mxed ( ) Example ( ) MHz N N MHz MHz

5 Varale ( + ) ( + )L ( + )H L L H H L Tale 5. Output Mxed ( + ) Formulas ( + ) = (N + N) + N Desgn Equatons ( + )L = L + L + N max ( + )H = H + L Any requency L whch s an nteger multple o C = N L = ( + )L L N max H = ( + )H L H L = ( + )H ( + )L + N max OUTPUT ( + ) KEY POINTS (a) RF output s ( + ). () C and L dvde evenly y oth step szes. (c) L, H, ( + )L, ( + )H dvde evenly y. OUTPUT ( + ) EXAMPLE The desred requency range s MHz n 125 khz steps usng PLLs wth 500 khz and 625 khz step szes. Reerence requency: C = 2 + = The reerence dvder values are: R = R = = 2.5 MHz + 1 = = 5 = = 4 The numer o N counter values used n addton to N L s: N max = 1 = = 3 The requency range o s: H L = 2 = The requency range o s: H L = ( + )H ( + )L + N max = (0.5) = 2.5 MHz 125 = MHz L and H requences depend on each other. To select values, the equaton or H s solved n terms o L: H = ( + )H L or H = 801 L Frequences used or L and H are a tradeo etween phase nose and ease o lterng the undesred mxer products. The est lterng o spurous mxer products occurs oth s are operatng at aout hal the desred output requency. Ths ncreases the requency separaton o the sum and derence products. nose ncreases wth requency. The same resonator Q at a hgher requency results n hgher nose or the same oset requency. PLL ICs also produce more nose wth ncreasng requency. L o 400 MHz s chosen. The requency range o s MHz. The requency range o s MHz. To check results, all dvde values and requences are n Tale 6. Tale 6. Output Mxed ( + ) Example ( + ) MHz N N MHz MHz

6 Varale L ( )L ( )H ( )H ( )L FEEDBACK MIXED PLLs Tale 7. Feedack ( ) Formulas = (N N) + N Desgn Equatons Any requency or whch L > H and L s an nteger multple o C ( )L = L H ( )H = L L + N max ( )H ( )L = H L + N max FEEDBACK ( ) KEY POINTS (a) RF output s wth L > H. () C and L dvde evenly y oth step szes. (c) L, H, ( )L, ( )H dvde evenly y. (d) Feedack mxer output s ( ). FEEDBACK ( ) EXAMPLE The desred requency range s MHz n 100 khz steps usng PLLs wth 500 khz and 600 khz step szes. Reerence requency: C = 2 + = The reerence dvder values are: R = R = = 3 MHz + 1 = = 6 = = 5 The numer o N counter values used n addton to N L s: N max = The requency range o s: H L = 2 1 = = 4 1 = = 2.4 MHz The requency range o s the output requency range, whch s MHz. L s selected such that L > H and L s an nteger multple o C. I the requency ranges or and are close together, sum and derence products rom the mxer wll e urther apart and easer to lter. I oth s operate at close to the output requency, they mght overlap. Mxer output could e ( ) and would e pulled n the wrong drecton. L o 66 MHz s chosen. The requency range o s MHz. N counter nput requency range s: ( )L = L H = = 2 MHz ( )H = L L + N max = (0.5) = 5 MHz To check results, all dvde values and requences are n Tale 8. Tale 8. Feedack ( ) Example ( ) MHz N N MHz MHz

7 Varale H ( + )L ( + )H ( + ) Tale 9. Feedack ( + ) Formulas = (N N ) N Desgn Equatons H s an nteger multple o C ( + )L = L + L + N max ( + )H = H + H ( + ) = N FEEDBACK ( + ) KEY POINTS (a) RF output s. () C and H dvde evenly y oth step szes. (c) L, H, ( + )L, ( + )H dvde evenly y. FEEDBACK ( + ) EXAMPLE The desred requency range s MHz n 100 khz steps usng PLLs wth 500 khz and 600 khz step szes. Reerence requency: C = 2 + = The reerence dvder values are: R = R = = 3 MHz + 1 = = 6 = = 5 The numer o N counter values used n addton to N H s: N max = The requency range o s: H L = 2 1 = = 4 = = 2.4 MHz The requency range o s the output requency range, whch s MHz. H s selected to e an nteger multple o C. I the requency ranges or and are close together, sum and derence products rom the mxer wll e urther apart and easer to lter. H o 66 MHz s chosen. The requency range o s MHz. The requency lmts o the nput to the N counter are: ( + )L = L + L + N max = (0.1) = 127 MHz ( + )H = H + H = = 130 MHz To check results, all dvde values and requences are n Tale 10. Tale 10. Feedack ( + ) Example ( + ) MHz N N MHz MHz R + 1 Hz L H OUTPUT REFERENCE 2 + Hz R PLL PLL + Hz N N FILTER ( ) ( + ) L H MIXER Fgure 3. Feedack Mxed PLLs Output 7

8 DESIGN TRADEOFFS The total numer o N counter values used s: LIMITATIONS OF FEEDBACK SUM N Total = Feedack sum output causes the N counter to operate at a hgher requency than the desred output. Phase nose wthn the loop andwdth could e up to 8 9 db worse than the eedack derence crcut. The worst case or phase nose s the est case or spurous product suppresson rom the mxer. (Both s operate at aout the same requency.) OUTPUT MIXED DIFFERENCE At least one wll operate at requences aove the desred output. Ths s most useul where the output tunng range s a hgh percentage o the center requency. Frequences o DC 100 MHz, or example, would e smple to mplement n ths conguraton. I the eature s not needed, phase nose wll e hgher than necessary. FEEDBACK DIFFERENCE Ths technque results n low phase nose and avods mxer products eng n the output. It works well when oth s can tune the ranges needed wthout range swtchng. Output mxed sum should also e consdered. OUTPUT MIXED SUM I the output s etween 400 MHz and 800 MHz, t may e etter to use two JFET s and sum the outputs. Two polar s comned usng eedack derence mght have hgher phase nose. The loops also uncton ndependently. OUTPUT VS. FEEDBACK MIXING Output mxng allows oth PLLs to operate ndependently. Spurous mxer products wll e present on the output. Feedack mxng results n the products eng on the PLL nput where they wll need much less lterng. Also the swtchng tme and dampng may depend on oth PLLs. Due to N Total, t s qute lkely that the tunng range o s much smaller than that o. would then requency hop much more quckly. The requency swtchng characterstcs o PLL usng eedack mxng mght not e dependent on PLL. FREQUENCY RANGE EXTENSION Both the output mxed sum and eedack mxed derence PLLs can extend the requency range o the PLL ICs they are used wth y approxmately two tmes. Both s would need to e on aout the same requency. SUMMARY A seres o examples and equatons has een descred to llustrate a technque that, though not commonly appled, s an elegant way to acheve ne resoluton and aster swtchng. Oset reerence PLLs have ecome much easer to mplement snce the ntroducton o dual loop PLL ICs such as the Motorola MC145220, whch operates rom 40 MHz 1.1 GHz. Phase detector and reerence dvder maxmum nput requences are the major lmtaton on () to () rato. The MC EVK (Evaluaton Kt) mplements the output mxed derence technque to acheve 30 ms swtchng rom MHz. Ater the swtchng tme has elapsed, the output s wthn 1 khz o nal requency. PLL has 10 khz steps and PLL has khz steps. Output ncrement sze s 10 Hz. 10 khz sdeand levels are 80 db. ACKNOWLEDGEMENT 1. Jm Irwn o Motorola Semconductor Products Sector provded many examples o alternatve multple loop schemes. REFERENCE 2. Communcatons Devce Data (DL136/D Rev. 4), page 2 605, Motorola, Fgure 11 s a sample PLL y John Hatchett usng the oset reerence technque. Motorola reserves the rght to make changes wthout urther notce to any products heren. Motorola makes no warranty, representaton or guarantee regardng the sutalty o ts products or any partcular purpose, nor does Motorola assume any lalty arsng out o the applcaton or use o any product or crcut, and speccally dsclams any and all lalty, ncludng wthout lmtaton consequental or ncdental damages. Typcal parameters whch may e provded n Motorola data sheets and/or speccatons can and do vary n derent applcatons and actual perormance may vary over tme. All operatng parameters, ncludng Typcals must e valdated or each customer applcaton y customer s techncal experts. Motorola does not convey any lcense under ts patent rghts nor the rghts o others. Motorola products are not desgned, ntended, or authorzed or use as components n systems ntended or surgcal mplant nto the ody, or other applcatons ntended to support or sustan le, or or any other applcaton n whch the alure o the Motorola product could create a stuaton where personal njury or death may occur. Should Buyer purchase or use Motorola products or any such unntended or unauthorzed applcaton, Buyer shall ndemny and hold Motorola and ts ocers, employees, susdares, alates, and dstrutors harmless aganst all clams, costs, damages, and expenses, and reasonale attorney ees arsng out o, drectly or ndrectly, any clam o personal njury or death assocated wth such unntended or unauthorzed use, even such clam alleges that Motorola was neglgent regardng the desgn or manuacture o the part. Motorola and are regstered trademarks o Motorola, Inc. Motorola, Inc. s an Equal Opportunty/Armatve Acton Employer. How to reach us: USA / EUROPE / Locatons Not Lsted: Motorola Lterature Dstruton; JAPAN: Nppon Motorola Ltd.; Tatsum SPD JLDC, 6F Seu Butsuryu Center, P.O. Box 20912; Phoenx, Arzona or Tatsum Koto Ku, Tokyo 135, Japan MFAX: RMFAX0@emal.sps.mot.com TOUCHTONE ASIA/PACIFIC: Motorola Semconductors H.K. Ltd.; 8B Ta Png Industral Park, INTERNET: NET.com 51 Tng Kok Road, Ta Po, N.T., Hong Kong /D

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