A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator
|
|
- Mavis Paul
- 6 years ago
- Views:
Transcription
1 A Low Power Dgtal Phase Locked Loop Wth ROM-Free Numercally Controlled Oscllator M. Saber Department o Inormatcs Kyushu Unersty 744 Motooka, Nsh-ku, Fukuoka-sh,89-395,Japan Y. Jtsumatsu jtsumatsu@n.kyushu-u.ac.jp Department o Inormatcs Kyushu Unersty 744 Motooka, Nsh-ku, Fukuoka-sh,89-395,Japan M. T. A. Khan tahr@apu-u.ac.jp Rtsumekan Asa Pacc Unersty, College o Asa Pacc Studes - Jumonjbaru, Beppu, Ota, , Japan Abstract Ths paper analyzes and desgns a second order dgtal phase-locked loop (DPLL), and presents low power archtecture or DPLL. The proposed archtecture reduces the hgh power consumpton o conentonal DPLL, whch results rom usng a read only memory (ROM) n mplementaton o the numercally controlled oscllator (NCO). The proposed DPLL utlzes a new desgn or NCO, n whch no ROM s used. DPLL s desgned and mplemented usng FPGA, consumes 37 mw, whch means more than 5% sang n power consumpton, and works at aster clock requency compared to tradtonal archtecture. Keywords: Dgtal Phase locked loop (DPLL), Feld Programmable Gate Array (FPGA), Sotware Dened Rado (SFDR), Read Only Memory (ROM), Spurous Free Dynamc Range (SFDR).. INTRODUCTION Sotware Dened Rados (SDRs) are leadng the ntegraton o dgtal sgnal processng (DSP) and rado requency (RF) capabltes. Ths ntegraton allows sotware to control communcatons parameters such as the requency range, lterng, modulaton type, data rates, and requency hoppng schemes. SDR technology can be seen n wreless deces used or derent applcatons n mltary, cl applcatons, and commercal network. Compared to conentonal RF transceer technologes, the adantage o SDR s ts lexblty. SDR prodes the ablty to recongure system perormance and unctons on the ly []. In order to take adantage o such dgtal processng, analog sgnals must be conerted to and rom the dgtal doman. Ths s done usng analog-to-dgtal (ADC) and dgtal-to-analog (DAC) conerters. To take ull adantage o dgtal processng, SDRs keep the sgnal n dgtal doman as much as possble, dgtzng and reconstructng as close as possble to the antenna. Despte an ADC or DAC connected drectly to an antenna s a requred end goal, there are ssues wth selectty and senstty that need an analog ront []. Phase-locked loop (PLL) s one o the most mportant buldng blocks necessary or modern dgtal communcatons, whch s used as a requency syntheszer n RF crcuts, or to recoer tme and carrer n the baseband dgtal sgnal processng. A complete understandng o the concept o PLL ncludes many study areas such as RF crcuts, dgtal sgnal processng, dscrete tme control systems, and communcaton theory [3]. Tradtonal PLL conssts o three parts; phase requency detector (PFD), loop lter, and oltage controlled oscllator (VCO). Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 4
2 The tradtonal analog PLL aces many desgn problems such as oltage supply nose, temperature nose, and large area consumed by loop lter components lke resstors and capactors. On the other hand DPLL, ormed o all dgtal components, prodes a hgh mmunty to supply oltage nose and temperature araton. Moreoer, DPLL can be desgned by usng hardware descrpton language (HDL) wth any standard cell lbrary. Thus, the tme or redesgn and check or errors s reduced. Thereore, DPLL prodes a good soluton to analog PLL desgn problems. Unortunately, DPLL has a crtcal dsadantage,.e., hgh power consumpton resultng rom the numercally-controlled oscllator (NCO) [4]. The hgh power consumpton o NCO s the result o usng ROM, whch contans the sampled ampltudes o a snusodal waeorm. As accuracy o the generated sgnal ncreases, the sze o ROM ncreases, whch causes hgh power consumpton and reduces the speed o the crcut. We propose a DPLL archtecture n whch the tradtonal NCO s replaced by a crcut whch generates a cosne waeorm usng a pecewse-lnear approxmaton. In secton, PLL operaton s explaned. The tradtonal NCO s descrbed n secton 3. Secton 4 llustrates a moded NCO whch can sole the problems o tradtonal NCO. In secton 5 mathematcal model o DPLL n both Z-doman and S-doman s llustrated. In secton 6 smulaton results. In secton 7 hardware mplementaton o moded NCO and moded DPLL s presented and n the end some conclusons are gen.. PHASE LOCKED LOOP PLL s an mportant component n many types o communcaton systems. It works n two derent manners; to synchronze a carrer n requency and phase or to operate as a syntheszer. The block dagram o DPLL s shown n Fg.. It conssts o three man blocks, phase/requency detector (PD), loop lter and NCO. Input sgnal (n), ω (n), θ (n) Phase/ Frequency Detector (n), ω ± ω, θ ± θ d Loop Flter Generated synchronzed sgnal (n), ω, θ NCO (n), ω ω, θ θ FIGURE : Dgtal phase locked loop n dscrete tme doman. The operaton o DPLL s as ollows: wthout nput sgnal appled to the system, NCO generates a sgnal wth a center requency ( c ), whch s called the ree runnng requency. The nput sgnal appled to the system s (n) = A sn( ω n + θ ), () where A s the ampltude, ω s the angular requency, and θ s the phase o the nput sgnal. Feedback loop mechansm o PLL wll orce NCO to generate a snusodal sgnal (n) (n) = A sn( ω n + θ ), () o Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 43
3 where Ao s the ampltude, θ generated by NCO. s gen by N = ω s the angular requency and θ s the phase o the sgnal θ (n) = k (), (3) where k s the NCO gan constant and (n) s the lter output. I k m denotes the phase detector (multpler) gan, then output o the phase detector s kmaao d(n) = sn( ω n + θ )cos( ω n + θ ) kmaa o [sn(( ) n ) sn(( ) n ], = ω + ω + θ + θ + ω ω + θ θ (4) The rst term n (4) corresponds to hgh requency component, and the second term corresponds to the phase derence between (n) and (n). Loop lter wll remoe the rst term n (4). I ω = ω, then phase derence can be obtaned as (n) = k [sn( θ θ )], (5) d where k k A A m o d =. I ( θ θ ), then V (n) s approxmated by kdaao (n) ( θ θ ). (6) Ths derence oltage s appled to the NCO. Thus, the control oltage (n) orces the NCO output requency to change up or down to reduce the requency derence between ω and ω. The equaton o the generated requency o NCO s ω (n) = ω + (n), (7) c where ωc s the center requency o NCO. I the nput requency ω s close to ω, the eedback manner o PLL causes NCO to synchronze or lock wth the mng sgnal. Once t s locked, the generated sgnal o NCO wll synchronze the nput sgnal n phase and requency. 3. TRADITIONAL NCO Voltage Controlled Oscllator (VCO), whch s used n analog PLL generates a snusodal waeorm whose requency depends on the nput oltage. NCO, whch s used n DPLL, generates a dgtal (sampled) snusodal waeorm wth a undamental requency determned by the dgtal nput alue (n-bts). As shown n Fg., NCO conssts o ROM, and accumulator. The output sgnal o the accumulator s used as address to the ROM. The nput sgnal to the accumulator conssts o the sum o an oset ( ω c ) correspondng to the ree runnng requency, and whch s the output o the loop lter [5]. The general equaton o generated requency rom NCO s = ( + ω j c ) clk. (8) where s the generated requency, ω c s the center requency, s an nteger alue and les n j j the range ( ), j s number o bts or wdth o the accumulator, whch s 6 bts, and s the clock requency. clk Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 44
4 The operaton o NCO s as ollows: rst assumng that the system clock requency s 5MHz, j=6 and ω c = 3, the ree runnng requency s MHz. Then, as shown n Fg. 3 there are 5 samplng ponts n one cycle o MHz snusodal waeorm. NCO generates exactly one cycle o snusodal waeorm when the nput alue ( ) s equal to zero. Snce the oset alue s 3, eery clock cycle the accumulator accumulates the oset alue. Then n 5 cycles the accumulated alue wll ncrease by one. The accumulator output wll address ths alue to the ROM and extract the cosne ampltudes alues stored n t. When the nput alue s greater than zero, the accumulaton speed becomes hgher. Thus n less than 5 cycles o clock requency the accumulator ncreases by, ths wll generate a hgher requency than MHz. When the nput alue s less than, a requency lower than MHz s generated. The problem wth usng a ROM s that, ts sze ncreases to achee a hgh spectral purty o the generated waeorm. Ths leads to hgh power consumpton and slow operaton o the system. Cos Waeorm Cos ROM ω c D Q Clock Delay Accumulator FIGURE : Numercally controlled oscllator structure. Samplng requency 5MHz.5 Ampltude samples n one cycle.5 Tme (s).5 x -6 FIGURE 3: Output waeorm o NCO. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 45
5 3. Preous Work NCO whch generates sne or cosne output as shown n Fg. ders mostly n the mplementaton o ROM block. Ths block s the slowest and consumes hgh power. The problem o ROM s that, ts sze grows exponentally wth the wdth o the phase accumulator. Snce one normally desres a large number o bts to achee ne requency tunng and hgh spectral purty, seeral technques hae been nented to lmt the ROM sze whle mantanng sutable perormance. One technque uses the quarter wae symmetry o sne uncton to reduce the number o saed samples by 4, n whch ROM saes only the ampltudes o rst quarter and through addtonal hardware the other quarters are generated [6]. Truncatng accumulator output (remoe number o most sgncant bts (MSBs)) s a common method to reduce the sze o ROM but ths method ntroduces spurous harmoncs [7]. Derent angular decomposton technques proposed to reduce the ROM sze consst o splttng the ROM nto a number o smaller ROMs, each ROM s addressed by a porton o truncated accumulator output. Generated samples o each ROM are added to orm a complete snusodal waeorm. In order to ntroduce more reducton n the ROM sze, many technques hae been proposed to make an ntal approxmaton o the sne ampltude rom the alue o the phase angle, and to use the ROM or a combnaton o ROMs to store correcton alues [8:]. Although these methods reduce the power consumpton but they stll use ROM whch causes a resdual o hgh power consumpton. Many other technques hae been proposed usng pecewse contnuous polynomals to approxmate the rst quadrant o the sne uncton. One o them s based on a Taylor-seres expanson [], a smpled 4th degree polynomal [3] and 4th degree Chebyshe polynomals [4]. The drawbacks o the aboe technques are that they requre addtonal hardware to make extra computatons whch ncrease the complexty o the crcut. The addtonal hardware consumes power consumpton whch supposed to reduce. 4. MODIFIED NCO 4. Proposed Archtecture In proposed archtecture no ROM s used, to prode ast swtchng, and less power consumpton. Instead o usng a ROM a pecewse lnear approxmaton s used, that s representng the rst quarter o the cosne waeorm as lnear lnes, each lne ts a lnear equaton wth slope and bas. Dependng on the symmetry o the cosne waeorm (hae 4 quarters), t can easly deduce the other 3 quarters o the cosne waeorm rom only the rst quarter. The rst quarter o the cosne uncton s dded nto eght pecewse lnear segments o equal length o the orm: + cos(t) a t + b, π t < π, =,,...7, 6 6 (9) where a s the segment slope and s lmted to 4 bts, and b s the constant or bas lmted to 8 bts. Slopes and bases are chosen usng the mnmum mean square error (MMSE) crteron, that mnmzes the ntegrated mean square error between the deal cos(t) and the approxmated cosne unctonp (t). π/ mmse = [cos(t) p(t)] dt. () t= Fg. 4 shows a comparson between deal and approxmated cosne waeorms. It seems to be the same except the top and bottom o the waeorm, that s because o the lnear segments. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 46
6 .5 Ampltude -.5 cos(t) p(t) Tme (s) FIGURE 4: Approxmated and Ideal cosne waeorms. The moded NCO conssts o two man components and two negaton unts. Fg. 5 shows the block dagram o each component and the correspondng waeorm. Accumulator recees the nput sgnal (n) whch represents the phase derence between θ and θ. The accumulator works as a crcular counter. A complete rotaton o the accumulator represents one cycle o the output waeorm. The accumulator recees a sgnal wth eght bts-length, and the wdth o the accumulator s j=6 bts, so truncaton s done to the output sgnal o the accumulator to be X sgnal wth L= bts length. The rst two most sgncant (MSBs) bts o the accumulator are used to control the operaton o NCO. nd MSB controls the sgn o sgnal X beore perormng the pecewse lnear calculaton. Ths negate sgn s needed to substtute n the lnear uncton to generate all quarters o the cosne waeorm. Second negaton s done at the output stage to correct poston o second and thrd quarters. Ths negaton s controlled usng XOR uncton between st, and nd MSB. st MSB nd MSB nd, and 3 rd quarters cos( ω n) (n) Accumulator (j bts) X (L bts) Negaton X or -X Pecewse lnear uncton Negaton Clock X output sgnal rom accumulator output sgnal rom st negaton output sgnal rom lnear uncton output sgnal rom NCO Ampltude L Ampltude Ampltude Ampltude Tme Tme Tme Tme FIGURE 5: Structure o moded NCO. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 47
7 4. Spurous Free Dynamc Range (SFDR) SFDR s dened as the rato between the RMS alue o the undamental requency (maxmum sgnal component) and the RMS alue o the next largest nose or harmonc dstorton component, (whch s reerred to as a spurous or a spur ) at ts output. SFDR s usually measured n dbc (.e. wth respect to the carrer requency ampltude) or n dbfs (.e. wth respect to the ADC's ull-scale range). Dependng on the test condton, SFDR s obsered wthn a predened requency wndow or rom DC up to Nyqust s requency o the conerter (ADC or DAC). Fg. 6 shows how SFDR s measured [5]. Snce the moded NCO depends on lnear approxmaton to generate dgtal samples o cosne waeorm, the spectrum o the generated waeorm contans spurs at all the spectrum requences, and SFDR s used to measure the spectral purty o the generated requences. Ampltude (db) Fundamental SFDR Largest Frequency / s FIGURE 6: SFDR measure. 5. DPLL MATHEMATICAL MODEL A mathematcal model or DPLL s bult n z-doman, and s-doman to study the ablty o the system to mantan phase trackng when exted by phase steps, requency steps, or other exctaton sgnals. Fg. 7 and Fg. 8 shows mathematcal model o the system n both Z-doman and S-doman respectely. (z) θ (z) Phase Detector θ (z) d d(z) k d Loop Flter.65 (z + ) F(z) = z.9375 θ (z) NCO z + G(z) = 64 (z ) (z) FIGURE 7: DPLL n Z-doman. (s) θ (s) Phase Detector θ (s) d k d d(s) Loop Flter F(s) = 5.5 s+.5 NCO θ (s) G(s) = 64 s (s) FIGURE 8: DPLL n S-doman. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 48
8 The phase transer uncton o the system n Z-doman s θ(z) k d F(z) G(z) + z + z = = θ (z) + K F(z) G(z) 5 98 z + 96 z d. () To get the step response o the system a relaton between (z) and (z) s needed. Assumng the nput sgnal s a unt step o requency at constant phase (z) F(z) 64 ( z ) = = (z) + F(z) G(z) 5 98 z + 96 z. () Usng blnear transormaton, the preous equatons are obtaned n S-doman θ (s) k F(s) G(s) = = d θ(s) + k d F(s) G(s) 99 s + 3 s + (3) (s) F(s) 64 s = = (s) + G(s) F(s) 99 s + 3 s + (4) In the test or stablty, DPLL s subjected to a test sgnal representng a unt step o requency at constant phase usng (4) wth s = 5 MHz [6-7]. As shown n Fg. 9, the system s stable wth oershoots at the transent state.. Step Response.8 Ampltude Tme (sec) x SIMULATION RESULTS FIGURE 9: DPLL n S-doman. 6. SFDR o Moded NCO To measure the SFDR a dscrete Fourer transorm (DFT) s done or a long repetton perod o the generated sgnal rom moded NCO. Derence between the ampltude o the undamental output requency and the ampltude o the largest spurs n the dynamc range s noted. Fg. shows the output spectrum or nput word o alue 37 representng (n), at a clock requency Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 49
9 o 5 MHz and an accumulator wdth j=6. The undamental requency s approxmately MHz wth db, and the spurous appears at 4.46 MHz wth db, so SFDR= dbc Power (db) Frequency (MHz) FIGURE : SFDR or undamental requency o MHz. 6. DPLL Synchronzaton In ths secton, we nestgate the perormances o proposed DPLL s usng computer smulatons. The proposed DPLL has the ollowng parameters: s = MHz, km =, k 4, = o A = A =, ω = MHz, and θ =. Two types o smulatons are done. In the rst one, DPLL recees a sgnal wth phase derence ( ω = MHz, θ = π / 4 ), DPLL response s shown n Fg.. In the second case nput sgnal has both phase derence and requency derence ( ω =. MH z, θ = π / 4 ), DPLL response s shown n Fg....5 F Tme (s) x -5 FIGURE : DPLL response n case o phase derence. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 5
10 V F Tme (s) x -5 FIGURE : DPLL response n case o phase and requency derence. 6.3 Proposed DPLL s. Tradtonal DPLL The man objecte o ths smulaton s to compare the perormance o the proposed DPLL wth tradtonal DPLL; to be sure that replacng ROM wth lnear approxmaton dd not aect the operaton o DPLL. In ths smulaton both archtectures hae the same parameters. s = MHz, km =, k = 4, A = Ao =, ω = MHz, and θ =. An nput sgnal wth ω =. MHz and θ = π /. s appled to both archtectures. Both responses are shown n Fg.3 whch ndcates that the perormance o the proposed DPLL s not aected by the moded NCO..e. the ablty o lockng phase or requency o the nput sgnal s not aected. Ths means the proposed DPLL saes power consumpton compared to tradtonal DPLL wthout aectng the perormance o DPLL V F.5 V F Tme (s) x -5 a) Tme (s) x -5 b) FIGURE 3: DPLL response n case o phase and requency derence a) Response o tradtonal DPLL. b) Response o proposed DPLL. 7. HARDWARE IMPLEMENTATION Hardware mplementaton o moded NCO, and moded DPLL s done usng VHDL code usng Xlnx system generator Smulnk tool [8:]. The archtecture o moded NCO s shown n Fg. 4. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 5
11 FIGURE 4: Moded NCO model Implementaton o lnear segments requres slopes and constants. The slopes are chosen usng MMSE as mentoned beore and the slopes accuracy s lmted to a racton our bts. m represents the ull truncated output rom the accumulator, m s hal m, m4 s hal m (quarter m) and m8 s hal m4 (eghth m). The rst three MSBs generated rom the accumulator are used to control three multplexers. The rst two multplexers are ormng the slope alue, and the thrd multplexer orm the constant alue. Accordng to the selected sgnal, the lnear equatons are chosen through the multplexers to orm the complete lnear equaton. The archtecture o moded DPLL s shown n Fg. 5; the archtecture uses the moded NCO nstead o tradtonal NCO. The smulaton s done at clock requency 5 MHz. All sgnals are bnary sgnals wth derent wdths. The nput sgnal s a bnary sgnal o 8 bts wdth representng a snusodal sgnal at requency MHz. Fg.6 shows the smulaton waeorms as an analog sgnal, the nput sgnal (nput) o requency MHz s multpled by the moded NCO sgnal (nput), and the output sgnal s passed through the dgtal lter. The nal output shows that dgtal mplementaton agrees wth the smulaton waeorm. FIGURE 5: Moded DPLL model. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 5
12 nput sgnal Output sgnal Multpler o/p x -5 x -5 Flter o/p x Tme (s) x -5 FIGURE 6: VHDL smulatons o DPLL. To recognze how much the moded NCO reduces the power consumpton, logc elements and operaton wth aster requency. A comparson between tradtonal NCO, whch uses ROM block and moded NCO, s done by mplementng both archtectures on the same FPGA dece (Xlnx- Spartan-3A DSP Xc3d34a-5g676). Ths comparson ges an dea o how much could be the mproements n power consumpton, reducton n the occuped number o logc elements and aster requency. As llustrated n Table, the moded NCO reduces about 4% o total logc elements used n tradtonal NCO, and dd not use memory bts, whch leads to sae the power consumpton by about 5% and operaton at a aster requency about.8 tmes the speed o tradtonal NCO. Comparson s also done wth the tradtonal DPLL (whch uses a tradtonal NCO) and moded DPLL (whch uses moded NCO). Table shows the result o comparson; t s clear that the moded DPLL consumed less power, occuped less area and worked aster than the tradtonal DPLL, wth no degradaton n system operaton such as lockng range. Tradtonal NCO Moded NCO Slces 8 64 Flp Flops 7 Block RAMs 6 Look up table (LUT) 6 IOBs 4 4 Maxmum Frequency 5.46 MHz MHZ Power consumpton.64 Watt.97 Watt TABLE : Implementaton results comparson o NCO. Tradtonal DPLL Moded DPLL Slces 6 64 Flp Flops 37 7 Block RAMs 6 Look up table (LUT) 99 6 IOBs 4 4 Maxmum Frequency.4 MHz 5.79 MHZ Power consumpton.34 Watt.37 Watt TABLE : Implementaton results comparson o DPLL. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 53
13 8. CONCLUSION Second order DPLL archtecture has been descrbed, analyzed and mplemented to be sutable or any applcaton. The problem o hgh power consumpton o DPLL has been soled by replacng the tradtonal NCO (the man component n DPLL) wth a moded ROM. The tradtonal NCO uses ROM, whch results n hgh power consumpton as well as slower operaton. The proposed archtecture reduces power consumpton, area consumpton and works at a hgher requency than the tradtonal one. 9. ACKNOWLEDGEMENT Ths research s partally supported by Grant-n-Ad or Scentc Research (B) no.3674, and the Ahara Project, the Frst program rom JSPS, ntated by CSTP.. REFERENCES [] M. Dllnger. K. Madan, N. Alonstot. Sotware Dened rado: Archtectures, systems, and unctons. John Wlley & Sons Inc., 3. [] T. J. Rouphael. RF and Dgtal Sgnal Processng For Sotware-Dened Rado: A Mult standard Mult-Mode Approch. John Wlly & Sons Inc., 8 [3] R. E. Best. Phase-Locked Loops: Desgn, Smulaton, and Applcaton. 6 th ed, McGraw-Hll, 7. [4] S. Goldman. Phase Locked-Loop Engneerng Hand Book o Integrated Crcut. Artech House Publshers, 7 [5] B. Goldberg. Dgtal Frequency Synthess Demysted: DDS and Fractonal-N PLLs. Newnes,999. [6] V.F. Kroupa, Ed. Drect Dgtal Frequency Syntheszers. IEEE Press,999. [7] V.F. Kroupa, V. Czek, J. Stursa, H. Sandoa. Spurous sgnals n drect dgtal requency syntheszers due to the phase truncaton. IEEE Transactons on Ultrasoncs, Ferroelectrcs, and Frequency Control, ol. 47, no. 5, pp. 66-7, September. [8] H.T. Ncholas III, H. Samuel and B. Km. The optmzaton o drect dgtal requency syntheszer perormance n the presence o nte word length eects, n Proc. o the 4nd Annual Frequency Control Symposum, 988, pp [9] A. Yamagsh, M. Ishkawa, T. Tsukahara, and S. Date. "A -V, -GHz low-power drect dgtal requency syntheszer chpset or wreless communcaton." IEEE Journal o Sold- State Crcuts, ol. 33, pp.-7, February 998. [] A. M. Sodagar, G. R. Lahj, Mappng rom phase to sne-ampltude n drect dgtal requency syntheszers usng parabolc approxmaton. n IEEE Transactons on Crcuts and Systems-II: Analog and Dgtal Sgnal Processng, ol. 47, pp , December. [] J.M.P. Langlos, D. Al-Khall. ROM sze reducton wth low processng cost or drect dgtal requency synthess, n Proc. o the IEEE Pacc Rm Conerence on Communcatons, Computers and Sgnal Processng, August, pp [] L.A. Weaer, R.J. Kerr. Hgh resoluton phase to sne ampltude conerson. U.S. patent , Feb. 7,99. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 54
14 [3] A.M. Sodagar, G.R. Lahj. A noel archtecture or ROM-less sne-output drect dgtal requency syntheszers by usng the nd-order parabolc approxmaton, n Proc. o the IEEE/IEA Internatonal Frequency Control Symposum and Exhbton, 7-9 June, pp [4] K.I. Palomak, J. Ntylaht. Drect dgtal requency syntheszer archtecture based on Chebyshe approxmaton, n Proc. o the 34th Aslomar Conerence on Sgnals, Systems and Computers, Oct. 9th No. st.,, pp [5] J. Rudy. CMOS Integrated Analog-to-Dgtal and Dgtal-to-Analog Conerters. Sprnger, 3. [6] J. G. Proaks, G. Dmtr, Manolaks. Dgtal Sgnal Processng. Prentce Hall,996. [7] Naresh K. Snha. Lnear Systems. John Wley & Sons Inc.,99. [8] Xlnx Inc. system generator or DSP user gude. Xlnx, 9. [9] W.Y. Yang. Matlab/Smulnk or Dgtal Communcaton. A-Jn, 9. [] P. Chu. FPGA Prototypng by VHDL Examples: Xlnx Spartan-3 Verson. Wley-Interscence, 8. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 55
Design and Implementation of DDFS Based on Quasi-linear Interpolation Algorithm
Desgn and Implementaton of DDFS Based on Quas-lnear Interpolaton Algorthm We Wang a, Yuanyuan Xu b and Hao Yang c College of Electroncs Engneerng, Chongqng Unversty of Posts and Telecommuncatons, Chongqng
More informationSection 5. Signal Conditioning and Data Analysis
Secton 5 Sgnal Condtonng and Data Analyss 6/27/2017 Engneerng Measurements 5 1 Common Input Sgnals 6/27/2017 Engneerng Measurements 5 2 1 Analog vs. Dgtal Sgnals 6/27/2017 Engneerng Measurements 5 3 Current
More informationHigh Speed, Low Power And Area Efficient Carry-Select Adder
Internatonal Journal of Scence, Engneerng and Technology Research (IJSETR), Volume 5, Issue 3, March 2016 Hgh Speed, Low Power And Area Effcent Carry-Select Adder Nelant Harsh M.tech.VLSI Desgn Electroncs
More informationDigital Transmission
Dgtal Transmsson Most modern communcaton systems are dgtal, meanng that the transmtted normaton sgnal carres bts and symbols rather than an analog sgnal. The eect o C/N rato ncrease or decrease on dgtal
More informationWalsh Function Based Synthesis Method of PWM Pattern for Full-Bridge Inverter
Walsh Functon Based Synthess Method of PWM Pattern for Full-Brdge Inverter Sej Kondo and Krt Choesa Nagaoka Unversty of Technology 63-, Kamtomoka-cho, Nagaoka 9-, JAPAN Fax: +8-58-7-95, Phone: +8-58-7-957
More informationHarmonic Balance of Nonlinear RF Circuits
MICROWAE AND RF DESIGN Harmonc Balance of Nonlnear RF Crcuts Presented by Mchael Steer Readng: Chapter 19, Secton 19. Index: HB Based on materal n Mcrowave and RF Desgn: A Systems Approach, nd Edton, by
More informationNATIONAL RADIO ASTRONOMY OBSERVATORY Green Bank, West Virginia SPECTRAL PROCESSOR MEMO NO. 25. MEMORANDUM February 13, 1985
NATONAL RADO ASTRONOMY OBSERVATORY Green Bank, West Vrgna SPECTRAL PROCESSOR MEMO NO. 25 MEMORANDUM February 13, 1985 To: Spectral Processor Group From: R. Fsher Subj: Some Experments wth an nteger FFT
More informationBiomedical Instrumentation
Bomedcal Instrumentaton Amplers & Wnter 1393 Bonab Unersty Applcatons o Operatonal Ampler (In Bologcal s and Systems) The three major operatons done on bologcal sgnals usng OpAmp: 1) Amplcatons and Attenuatons
More informationComparison of Reference Compensating Current Estimation Techniques for Shunt Active Filter
Comparson of Reference Compensatng Current Estmaton Technques for Shunt Acte Flter R.SHANMUGHA SUNDARAM K.J.POORNASEVAN N.DEVARAJAN Department of Electrcal & Electroncs Engneerng Goernment College of Technology
More informationChapter 13. Filters Introduction Ideal Filter
Chapter 3 Flters 3.0 Introducton Flter s the crcut that capable o passng sgnal rom nput to output that has requency wthn a speced band and attenuatng all others outsde the band. Ths s the property o selectvty.
More informationTo: Professor Avitabile Date: February 4, 2003 From: Mechanical Student Subject: Experiment #1 Numerical Methods Using Excel
To: Professor Avtable Date: February 4, 3 From: Mechancal Student Subject:.3 Experment # Numercal Methods Usng Excel Introducton Mcrosoft Excel s a spreadsheet program that can be used for data analyss,
More informationA High-Sensitivity Oversampling Digital Signal Detection Technique for CMOS Image Sensors Using Non-destructive Intermediate High-Speed Readout Mode
A Hgh-Senstvty Oversamplng Dgtal Sgnal Detecton Technque for CMOS Image Sensors Usng Non-destructve Intermedate Hgh-Speed Readout Mode Shoj Kawahto*, Nobuhro Kawa** and Yoshak Tadokoro** *Research Insttute
More informationA study of turbo codes for multilevel modulations in Gaussian and mobile channels
A study of turbo codes for multlevel modulatons n Gaussan and moble channels Lamne Sylla and Paul Forter (sylla, forter)@gel.ulaval.ca Department of Electrcal and Computer Engneerng Laval Unversty, Ste-Foy,
More informationHigh Speed ADC Sampling Transients
Hgh Speed ADC Samplng Transents Doug Stuetzle Hgh speed analog to dgtal converters (ADCs) are, at the analog sgnal nterface, track and hold devces. As such, they nclude samplng capactors and samplng swtches.
More informationantenna antenna (4.139)
.6.6 The Lmts of Usable Input Levels for LNAs The sgnal voltage level delvered to the nput of an LNA from the antenna may vary n a very wde nterval, from very weak sgnals comparable to the nose level,
More informationScilab/Scicos Modeling, Simulation and PC Based Implementation of Closed Loop Speed Control of VSI Fed Induction Motor Drive
16th NATIONAL POWER SYSTEMS CONFERENCE, 15th-17th DECEMBER, 2010 453 Sclab/Sccos Modelng, Smulaton and PC Based Implementaton of Closed Loop Speed Control of VSI Fed Inducton Motor Dre Vjay Babu Korebona,
More informationRejection of PSK Interference in DS-SS/PSK System Using Adaptive Transversal Filter with Conditional Response Recalculation
SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol., No., November 23, 3-9 Rejecton of PSK Interference n DS-SS/PSK System Usng Adaptve Transversal Flter wth Condtonal Response Recalculaton Zorca Nkolć, Bojan
More informationMicroelectronic Circuits
Mcroelectronc Crcuts Slde 1 Introducton Suggested textbook: 1. Adel S. Sedra and Kenneth C. Smth, Mcroelectronc Crcuts Theory and Applcatons, Sxth edton Internatonal Verson, Oxford Unersty Press, 2013.
More informationPOLYTECHNIC UNIVERSITY Electrical Engineering Department. EE SOPHOMORE LABORATORY Experiment 1 Laboratory Energy Sources
POLYTECHNIC UNIERSITY Electrcal Engneerng Department EE SOPHOMORE LABORATORY Experment 1 Laboratory Energy Sources Modfed for Physcs 18, Brooklyn College I. Oerew of the Experment Ths experment has three
More informationACTIVE RESISTANCE EMULATION IN THREE-PHASE RECTIFIER WITH SUBOPTIMAL CURRENT INJECTION
6 th INTNTIONL SYMPOSIUM on POW ELECTRONICS - Ee NOVI SD, REPULIC O SI, October 6 th - 8 th, CTIVE RESISTNCE EMULTION IN THREE-PHSE RECTII WITH SUOPTIML CURRENT INJECTION Mlan Darjeć, Predrag Pejoć, Yasuyuk
More informationCalculation of the received voltage due to the radiation from multiple co-frequency sources
Rec. ITU-R SM.1271-0 1 RECOMMENDATION ITU-R SM.1271-0 * EFFICIENT SPECTRUM UTILIZATION USING PROBABILISTIC METHODS Rec. ITU-R SM.1271 (1997) The ITU Radocommuncaton Assembly, consderng a) that communcatons
More informationNovel Techniques of RF High Power Measurement
Novel Technques o RF Hgh Power Measurement Ovdu D. Stan Department o Electrcal and Computer Engneerng COLORADO STATE UNIVERSITY EE PhD Dssertaton Deense 2007 Why s RF Hgh Power Measurement s Important?
More informationThe Performance Improvement of BASK System for Giga-Bit MODEM Using the Fuzzy System
Int. J. Communcatons, Network and System Scences, 10, 3, 1-5 do:10.36/jcns.10.358 Publshed Onlne May 10 (http://www.scrp.org/journal/jcns/) The Performance Improvement of BASK System for Gga-Bt MODEM Usng
More informationDesign of Digital Band Stop FIR Filter using Craziness Based Particle Swarm Optimization (CRPSO) Technique
Internatonal Journal o Scentc Research Engneerng & Technology (IJSRET), ISSN 78 088 Volume, Issue 5, May 05 6 Desgn o Dgtal Band Stop FIR Flter usng Crazness Based Partcle Swarm Optmzaton (CRPSO) Technque
More informationAN1277 MOTOROLA SEMICONDUCTOR TECHNICAL DATA
SEMICONDUCTOR TECHNICAL DATA Order ths document y /D Prepared y: Morrs Smth INTRODUCTION Frequency synthess y use o two loops, wth reerence requences oset rom each other, can provde much ner resoluton
More informationTECHNICAL NOTE TERMINATION FOR POINT- TO-POINT SYSTEMS TN TERMINATON FOR POINT-TO-POINT SYSTEMS. Zo = L C. ω - angular frequency = 2πf
TECHNICAL NOTE TERMINATION FOR POINT- TO-POINT SYSTEMS INTRODUCTION Because dgtal sgnal rates n computng systems are ncreasng at an astonshng rate, sgnal ntegrty ssues have become far more mportant to
More informationBit Error Probability of Cooperative Diversity for M-ary QAM OFDM-based system with Best Relay Selection
011 Internatonal Conerence on Inormaton and Electroncs Engneerng IPCSIT vol.6 (011) (011) IACSIT Press, Sngapore Bt Error Proalty o Cooperatve Dversty or M-ary QAM OFDM-ased system wth Best Relay Selecton
More informationDesign of an FPGA based TV-tuner test bench using MFIR structures
ANNUAL JOURNAL OF ELECTRONICS, 3, ISSN 34-78 Desgn of an FPGA based TV-tuner test bench usng MFIR structures Jean-Jacques Vandenbussche, Peter Lee and Joan Peuteman Abstract - The paper shows how Multplcatve
More informationCharacteristics of New Single Phase Voltage Doubler Rectifier Circuit using the Partial Switching Strategy
IEEE PEDS 217, Honolulu, USA 12 15 December 217 Characterstcs of New gle Phase Voltage Doubler Rectfer Crcut usng the Partal Swtchng Strategy Kenj Ame Akto Kumaga Takahsa Ohj Kyohe Kyota Masaak Saku Unersty
More informationAnalysis, Design, and Simulation of a Novel Current Sensing Circuit
Analyss, Desgn, and Smulaton of a Noel Current Sensng Crcut Louza Sellam Electrcal and Computer Engneerng Department US Naal Academy Annapols, Maryland, USA sellam@usna.edu obert W. Newcomb Electrcal and
More informationIntroduction to Amplifiers
Introducton to Amplfers Dad W. Graham West Vrgna Unersty Lane Department of Computer Scence and Electrcal Engneerng Dad W. Graham, 07 Small Wggles To Bg Wggles Amplfcaton s extremely mportant n electroncs
More informationEE 330 Lecture 22. Small Signal Analysis Small Signal Analysis of BJT Amplifier
EE Lecture Small Sgnal Analss Small Sgnal Analss o BJT Ampler Revew rom Last Lecture Comparson o Gans or MOSFET and BJT Crcuts N (t) A B BJT CC Q R EE OUT R CQ t DQ R = CQ R =, SS + T = -, t =5m R CQ A
More informationCHAPTER 4 INSTANTANEOUS SYMMETRICAL COMPONENT THEORY
74 CHAPTER 4 INSTANTANEOUS SYMMETRICAL COMPONENT THEORY 4. INTRODUCTION Ths chapter deals wth nstantaneous symmetrcal components theory for current and oltage compenton. The technque was ntroduced by Forteue.
More informationOperation of Shunt Active Power Filter Under Unbalanced and Distorted Load Conditions
Operaton of Shunt Acte Power Flter Under Unbalanced and Dstorted Load Condtons Metn Kesler 1, Engn Özdemr 1, Kocael Unersty, Techncal Educaton Faculty, Electrcal Educaton Department, 4138 Umuttepe, TURKEY
More informationIEE Electronics Letters, vol 34, no 17, August 1998, pp ESTIMATING STARTING POINT OF CONDUCTION OF CMOS GATES
IEE Electroncs Letters, vol 34, no 17, August 1998, pp. 1622-1624. ESTIMATING STARTING POINT OF CONDUCTION OF CMOS GATES A. Chatzgeorgou, S. Nkolads 1 and I. Tsoukalas Computer Scence Department, 1 Department
More informationPassive Filters. References: Barbow (pp ), Hayes & Horowitz (pp 32-60), Rizzoni (Chap. 6)
Passve Flters eferences: Barbow (pp 6575), Hayes & Horowtz (pp 360), zzon (Chap. 6) Frequencyselectve or flter crcuts pass to the output only those nput sgnals that are n a desred range of frequences (called
More informationAnalysis of Time Delays in Synchronous and. Asynchronous Control Loops. Bj rn Wittenmark, Ben Bastian, and Johan Nilsson
37th CDC, Tampa, December 1998 Analyss of Delays n Synchronous and Asynchronous Control Loops Bj rn Wttenmark, Ben Bastan, and Johan Nlsson emal: bjorn@control.lth.se, ben@control.lth.se, and johan@control.lth.se
More informationAN ALL DIGITAL QAM MODULATOR WITH RADIO FREQUENCY OUTPUT
AN ALL DIGITAL QAM MODULATOR WITH RADIO FREQUENCY OUTPUT Zhuan Ye (Motorola Labs, 131 E. Algonqun Rd., Schaumburg, IL 6196 zhuan.ye@motorola.com); John Grosspetsch (Motorola Labs, Schaumburg, IL 6196 john.grosspetsch@motorola.com)
More informationPRACTICAL, COMPUTATION EFFICIENT HIGH-ORDER NEURAL NETWORK FOR ROTATION AND SHIFT INVARIANT PATTERN RECOGNITION. Evgeny Artyomov and Orly Yadid-Pecht
68 Internatonal Journal "Informaton Theores & Applcatons" Vol.11 PRACTICAL, COMPUTATION EFFICIENT HIGH-ORDER NEURAL NETWORK FOR ROTATION AND SHIFT INVARIANT PATTERN RECOGNITION Evgeny Artyomov and Orly
More informationCONCERNING THE NO LOAD HIGH VOLTAGE TRANSFORMERS DISCONNECTING
CONCERNING THE NO LOAD HIGH VOLTAGE TRANSFORMERS DISCONNEING Mara D Brojbou and Vrgna I Ivanov Faculty o Electrcal engneerng Unversty o Craova, 7 Decebal Blv, Craova, Romana E-mal: mbrojbou@elthucvro,
More informationMultiple Error Correction Using Reduced Precision Redundancy Technique
Multple Error Correcton Usng Reduced Precson Redundancy Technque Chthra V 1, Nthka Bhas 2, Janeera D A 3 1,2,3 ECE Department, Dhanalakshm Srnvasan College of Engneerng,Combatore, Tamlnadu, Inda Abstract
More informationLow Switching Frequency Active Harmonic Elimination in Multilevel Converters with Unequal DC Voltages
Low Swtchng Frequency Actve Harmonc Elmnaton n Multlevel Converters wth Unequal DC Voltages Zhong Du,, Leon M. Tolbert, John N. Chasson, Hu L The Unversty of Tennessee Electrcal and Computer Engneerng
More informationRC Filters TEP Related Topics Principle Equipment
RC Flters TEP Related Topcs Hgh-pass, low-pass, Wen-Robnson brdge, parallel-t flters, dfferentatng network, ntegratng network, step response, square wave, transfer functon. Prncple Resstor-Capactor (RC)
More informationControl of Chaos in Positive Output Luo Converter by means of Time Delay Feedback
Control of Chaos n Postve Output Luo Converter by means of Tme Delay Feedback Nagulapat nkran.ped@gmal.com Abstract Faster development n Dc to Dc converter technques are undergong very drastc changes due
More informationEfficient Large Integers Arithmetic by Adopting Squaring and Complement Recoding Techniques
The th Worshop on Combnatoral Mathematcs and Computaton Theory Effcent Large Integers Arthmetc by Adoptng Squarng and Complement Recodng Technques Cha-Long Wu*, Der-Chyuan Lou, and Te-Jen Chang *Department
More informationDWA TECHNIQUE TO IMPROVE DAC OF SIGMA-DELTA FRACTIONAL-N FREQUENCY SYNTHESIZER FOR WIMAX
Journal of Al-Nahran Unversty Vol.12 (2), June, 2009, pp.93-100 Scence DWA TECHNIQUE TO IMPROVE DAC OF SIGMA-DELTA FRACTIONAL-N FREQUENCY SYNTHESIZER FOR WIMAX H. T. Zboon* and H.M. Azzaw *Department of
More informationFigure.1. Basic model of an impedance source converter JCHPS Special Issue 12: August Page 13
A Hgh Gan DC - DC Converter wth Soft Swtchng and Power actor Correcton for Renewable Energy Applcaton T. Selvakumaran* and. Svachdambaranathan Department of EEE, Sathyabama Unversty, Chenna, Inda. *Correspondng
More informationECEN 5014, Spring 2013 Special Topics: Active Microwave Circuits and MMICs Zoya Popovic, University of Colorado, Boulder
ECEN 514, Sprng 13 Specal Topcs: Acte Mcrowae Crcuts and MMICs Zoya Popoc, Unersty of Colorado, Boulder LECTURE 4 BROADBAND AMPLIFIERS L4.1. INTRODUCTION The challenge n desgnng a broadband mcrowae amplfer
More informationGraph Method for Solving Switched Capacitors Circuits
Recent Advances n rcuts, ystems, gnal and Telecommuncatons Graph Method for olvng wtched apactors rcuts BHUMIL BRTNÍ Department of lectroncs and Informatcs ollege of Polytechncs Jhlava Tolstého 6, 586
More informationActive Damping of LCL-Filter Resonance based on Virtual Resistor for PWM Rectifiers Stability Analysis with Different Filter Parameters
Acte Dampng o Flter Resonance based on Vrtual Resstor or PWM Recters Stablty Analyss wth Derent Flter Parameters hrstan Wessels, Jörg Dannehl, student member, IEEE and Fredrch W. Fuchs, senor member, IEEE
More informationFPGA Implementation of Fuzzy Inference System for Embedded Applications
FPGA Implementaton of Fuzzy Inference System for Embedded Applcatons Dr. Kasm M. Al-Aubdy The Dean, Faculty of Engneerng, Phladelpha Unversty, P O Box 1, Jordan, 19392 E-mal: alaubdy@gmal.com Abstract:-
More informationHIGH PERFORMANCE ADDER USING VARIABLE THRESHOLD MOSFET IN 45NM TECHNOLOGY
Internatonal Journal of Electrcal, Electroncs and Computer Systems, (IJEECS) HIGH PERFORMANCE ADDER USING VARIABLE THRESHOLD MOSFET IN 45NM TECHNOLOGY 1 Supryo Srman, 2 Dptendu Ku. Kundu, 3 Saradndu Panda,
More informationTunable Wideband Receiver (TWB) Data Processing Description December, 2013
Page 1 of 5 Tunable Wdeband Recever (TWB) Data Processng Descrpton December, 2013 The tunable wdeband recever (TWB) can be manually tuned to any frequency of nterest between 17 and 33 MHz. The recever
More information1. Introduction. Key words: FPGA, Picoblaze, PID controller, HDL, Simulink
FPGA Desgn and Implementaton of Dgtal PID Controller based on floatng pont arthmetc Pourya Alnezhad 1, Arash Ahmad 1- M.Sc. student of Electrcal and communcaton engneerng Shahd Bahonar Unversty, Iran palnezhad@eng.uk.ac.r
More informationVoltage Quality Enhancement and Fault Current Limiting with Z-Source based Series Active Filter
Research Journal of Appled Scences, Engneerng and echnology 3(): 246-252, 20 ISSN: 2040-7467 Maxwell Scentfc Organzaton, 20 Submtted: July 26, 20 Accepted: September 09, 20 Publshed: November 25, 20 oltage
More informationA Current Differential Line Protection Using a Synchronous Reference Frame Approach
A Current Dfferental Lne rotecton Usng a Synchronous Reference Frame Approach L. Sousa Martns *, Carlos Fortunato *, and V.Fernão res * * Escola Sup. Tecnologa Setúbal / Inst. oltécnco Setúbal, Setúbal,
More informationTuned PI Controller using Zeigler-Nichols Method for Power Quality Enhancement for linear and non linear loads
Tuned PI Controller usng Zegler-Nchols Method for Power Qualty Enhancement for lnear and non lnear s Rtu Sharma Department of Electrcal Engneerng, Gurgaon Insttute of Technology & Management, Gurgaon Emal:
More informationMitigation of Harmonics in Micro Grid using Photo Voltaic cell interfaced Shunt Active Power Filter
Mtgaton of Harmoncs n Mcro Grd usng hoto Voltac cell nterfaced Shunt Acte ower Flter Selakumar.S 1, Aruna.V 2, Jagan.R 3, UG scholar, Department of EEE, SMVEC 1, 2, 3. ondcherry, Inda. Abstract: - Ths
More informationFPGA Implementation of Ultrasonic S-Scan Coordinate Conversion Based on Radix-4 CORDIC Algorithm
IACSIT Internatonal Journal of Engneerng and Technology, Vol. 7, No. 3, June 25 FPGA Implementaton of Ultrasonc S-Scan Coordnate Converson Based on Radx-4 CORDIC Algorthm Ruobo Ln, Guxong Lu, and Wenmng
More informationA High-Speed Multiplication Algorithm Using Modified Partial Product Reduction Tree
World Academy of Scence, Engneerng and Technology Internatonal Journal of Electrcal and Computer Engneerng Vol:4, No:, 200 A Hgh-Speed Multplcaton Algorthm Usng Modfed Partal Product educton Tree P Asadee
More informationPERFORMANCE EVALUATION OF BOOTH AND WALLACE MULTIPLIER USING FIR FILTER. Chirala Engineering College, Chirala.
PERFORMANCE EVALUATION OF BOOTH AND WALLACE MULTIPLIER USING FIR FILTER 1 H. RAGHUNATHA RAO, T. ASHOK KUMAR & 3 N.SURESH BABU 1,&3 Department of Electroncs and Communcaton Engneerng, Chrala Engneerng College,
More informationFigure 1. DC-DC Boost Converter
EE46, Power Electroncs, DC-DC Boost Converter Verson Oct. 3, 11 Overvew Boost converters make t possble to effcently convert a DC voltage from a lower level to a hgher level. Theory of Operaton Relaton
More informationDesign of Practical FIR Filter Using Modified Radix-4 Booth Algorithm
Desgn of Practcal FIR Flter Usng Modfed Radx-4 Booth Algorthm E Srnvasarao M.Tech Scholar, Department of ECE, AITAM. V. Lokesh Raju Assocate Professor, Department of ECE, AITAM. L Rambabu Assstant Professor,
More informationReactive power compensation for nonlinear loads using Fuzzy controller
NT J CU SC 07, 0(4: E 0-9 ESEACH ATCE SSN 50-770 eacte power compensaton or nonlnear loads usng Fuzzy controller Sreedhar K, SS Deeksht and D. Nagendra* Department o EEE, ATS ajampet, Kadapa, A.P. nda
More informationShunt Active Filters (SAF)
EN-TH05-/004 Martt Tuomanen (9) Shunt Actve Flters (SAF) Operaton prncple of a Shunt Actve Flter. Non-lnear loads lke Varable Speed Drves, Unnterrupted Power Supples and all knd of rectfers draw a non-snusodal
More informationECE315 / ECE515 Lecture 5 Date:
Lecture 5 Date: 18.08.2016 Common Source Amplfer MOSFET Amplfer Dstorton Example 1 One Realstc CS Amplfer Crcut: C c1 : Couplng Capactor serves as perfect short crcut at all sgnal frequences whle blockng
More informationPhasor Representation of Sinusoidal Signals
Phasor Representaton of Snusodal Sgnals COSC 44: Dgtal Communcatons Instructor: Dr. Amr Asf Department of Computer Scence and Engneerng York Unversty Handout # 6: Bandpass odulaton Usng Euler dentty e
More informationDesign of Shunt Active Filter for Harmonic Compensation in a 3 Phase 3 Wire Distribution Network
Internatonal Journal of Research n Electrcal & Electroncs Engneerng olume 1, Issue 1, July-September, 2013, pp. 85-92, IASTER 2013 www.aster.com, Onlne: 2347-5439, Prnt: 2348-0025 Desgn of Shunt Actve
More informationDESIGN OF OPTIMIZED FIXED-POINT WCDMA RECEIVER
DESIGN OF OPTIMIZED FIXED-POINT WCDMA RECEIVER Ha-Nam Nguyen, Danel Menard, and Olver Senteys IRISA/INRIA, Unversty of Rennes, rue de Kerampont F-3 Lannon Emal: hanguyen@rsa.fr ABSTRACT To satsfy energy
More informationImplementation of Fan6982 Single Phase Apfc with Analog Controller
Internatonal Journal of Research n Engneerng and Scence (IJRES) ISSN (Onlne): 2320-9364, ISSN (Prnt): 2320-9356 Volume 5 Issue 7 ǁ July. 2017 ǁ PP. 01-05 Implementaton of Fan6982 Sngle Phase Apfc wth Analog
More informationTHE USE OF CONVOLUTIONAL CODE FOR NARROWBAND INTERFERENCE SUPPRESSION IN OFDM-DVBT SYSTEM
THE USE OF CONVOLUTIONAL CODE FOR NARROWBAND INTERFERENCE SUPPRESSION IN OFDM-DVBT SYSTEM Azura Abdullah, Muhammad Sobrun Jaml Jamal, Khazuran Abdullah, Ahmad Fadzl Ismal and An Lza Asnaw Department of
More informationA MODIFIED DIFFERENTIAL EVOLUTION ALGORITHM IN SPARSE LINEAR ANTENNA ARRAY SYNTHESIS
A MODIFIED DIFFERENTIAL EVOLUTION ALORITHM IN SPARSE LINEAR ANTENNA ARRAY SYNTHESIS Kaml Dmller Department of Electrcal-Electroncs Engneerng rne Amercan Unversty North Cyprus, Mersn TURKEY kdmller@gau.edu.tr
More informationSmart Grid Technologies for Reactive Power Compensation in Motor Start Applications
1 Smart Grd Technologes for Reacte Power Compensaton n Motor Start Applcatons Maryclare Peterson, Member, IEEE and Brj N. Sngh, Member, IEEE Abstract Seeral major power outages hae been attrbuted to nsuffcent
More informationParameter Free Iterative Decoding Metrics for Non-Coherent Orthogonal Modulation
1 Parameter Free Iteratve Decodng Metrcs for Non-Coherent Orthogonal Modulaton Albert Gullén Fàbregas and Alex Grant Abstract We study decoder metrcs suted for teratve decodng of non-coherently detected
More informationChaotic Filter Bank for Computer Cryptography
Chaotc Flter Bank for Computer Cryptography Bngo Wng-uen Lng Telephone: 44 () 784894 Fax: 44 () 784893 Emal: HTwng-kuen.lng@kcl.ac.ukTH Department of Electronc Engneerng, Dvson of Engneerng, ng s College
More informationCMOS Implementation of Lossy Integrator using Current Mirrors Rishu Jain 1, Manveen Singh Chadha 2 1, 2
Proceedngs of Natonal Conference on Recent Advances n Electroncs and Communcaton Engneerng CMOS Implementaton of Lossy Integrator usng Current Mrrors Rshu Jan, Manveen Sngh Chadha 2, 2 Department of Electroncs
More informationPower and Area Efficient VLSI Architectures for Communication Signal Processing
and rea Ecent VLSI rchtectures or Communcaton Sgnal Processng Dejan Markovc, Borvoje kolc, Robert W. Brodersen Berkeley Wreless Research Center, Unversty o Calorna at Berkeley 108 llston Way, Sute 00,
More informationDevelopment of Algorithm, Architecture and FPGA Implementation of Demodulator for Processing Satellite Data Communication
IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 37 Development of Algorthm, Archtecture and FPGA Implementaton of Demodulator for Processng atellte Data Communcaton K..
More informationECE 2133 Electronic Circuits. Dept. of Electrical and Computer Engineering International Islamic University Malaysia
ECE 2133 Electronc Crcuts Dept. of Electrcal and Computer Engneerng Internatonal Islamc Unversty Malaysa Chapter 12 Feedback and Stablty Introducton to Feedback Introducton to Feedback 1-4 Harold Black,
More informationLecture 30: Audio Amplifiers
Whtes, EE 322 Lecture 30 Page 1 of 9 Lecture 30: Audo Amplfers Once the audo sgnal leaes the Product Detector, there are two more stages t passes through before beng output to the speaker (ref. Fg. 1.13):
More informationRevision of Lecture Twenty-One
Revson of Lecture Twenty-One FFT / IFFT most wdely found operatons n communcaton systems Important to know what are gong on nsde a FFT / IFFT algorthm Wth the ad of FFT / IFFT, ths lecture looks nto OFDM
More informationIIR Filters Using Stochastic Arithmetic
IIR Flters Usng Stochastc Arthmetc Naman Saraf, Ka Bazargan, avd J Llja, and Marc Redel epartment of Electrcal and Computer Engneerng Unversty of Mnnesota, Twn Ctes Mnneapols, MN, USA {saraf012, ka, llja,
More informationMASTER TIMING AND TOF MODULE-
MASTER TMNG AND TOF MODULE- G. Mazaher Stanford Lnear Accelerator Center, Stanford Unversty, Stanford, CA 9409 USA SLAC-PUB-66 November 99 (/E) Abstract n conjuncton wth the development of a Beam Sze Montor
More informationLatency Insertion Method (LIM) for IR Drop Analysis in Power Grid
Abstract Latency Inserton Method (LIM) for IR Drop Analyss n Power Grd Dmtr Klokotov, and José Schutt-Ané Wth the steadly growng number of transstors on a chp, and constantly tghtenng voltage budgets,
More informationUncertainty in measurements of power and energy on power networks
Uncertanty n measurements of power and energy on power networks E. Manov, N. Kolev Department of Measurement and Instrumentaton, Techncal Unversty Sofa, bul. Klment Ohrdsk No8, bl., 000 Sofa, Bulgara Tel./fax:
More informationDynamic Modeling and Optimum Load Control of a PM Linear Generator for Ocean Wave Energy Harvesting Application
Dynamc Modelng and Optmum Load Control o a PM Lnear Generator or Ocean Wave Energy Harvestng Applcaton Haoe Luan, Omer C. Onar, and Alreza Khalgh Energy Harvestng and enewable Energes Laboratory, Electrc
More informationKeywords LTE, Uplink, Power Control, Fractional Power Control.
Volume 3, Issue 6, June 2013 ISSN: 2277 128X Internatonal Journal of Advanced Research n Computer Scence and Software Engneerng Research Paper Avalable onlne at: www.jarcsse.com Uplnk Power Control Schemes
More informationDESIGN OF OPTIMIZED FIXED-POINT WCDMA RECEIVER
7th European Sgnal Processng Conference (EUSIPCO 9) Glasgow, Scotland, August -8, 9 DESIGN OF OPTIMIZED FIXED-POINT WCDMA RECEIVER Ha-Nam Nguyen, Danel Menard, and Olver Senteys IRISA/INRIA, Unversty of
More informationDual Functional Z-Source Based Dynamic Voltage Restorer to Voltage Quality Improvement and Fault Current Limiting
Australan Journal of Basc and Appled Scences, 5(5): 287-295, 20 ISSN 99-878 Dual Functonal Z-Source Based Dynamc Voltage Restorer to Voltage Qualty Improvement and Fault Current Lmtng M. Najaf, M. Hoseynpoor,
More informationResearch of Dispatching Method in Elevator Group Control System Based on Fuzzy Neural Network. Yufeng Dai a, Yun Du b
2nd Internatonal Conference on Computer Engneerng, Informaton Scence & Applcaton Technology (ICCIA 207) Research of Dspatchng Method n Elevator Group Control System Based on Fuzzy Neural Network Yufeng
More informationResearch on Peak-detection Algorithm for High-precision Demodulation System of Fiber Bragg Grating
, pp. 337-344 http://dx.do.org/10.1457/jht.014.7.6.9 Research on Peak-detecton Algorthm for Hgh-precson Demodulaton System of Fber ragg Gratng Peng Wang 1, *, Xu Han 1, Smn Guan 1, Hong Zhao and Mngle
More informationKey-Words: - MPPT, Sliding mode control, Battery charger, Lyapunov function, Boost converter
Research on MPPT and Sngle-Stage Grd-Connected or Photovoltac System Department o Electrcal Engneerng Natonal Chang-hua Unversty o Educaton Bao-Shan Campus, Address: No.2, Sh-Da Road, Changhua Cty 520
More informationAn Improved Active Filter Technique for Power Quality Control under Unbalanced Dynamic Load Condition
Amercan Journal of Engneerng Research (AJER) e-issn: -847 p-issn : -96 Volume-5, Issue-, pp-97-5 www.ajer.org Research Paper Open Access An Improved Actve Flter Technque for Power Qualty Control under
More informationEnergy Comparison of MPPT Techniques Using Cuk Converter
Internatonal Journal of Innoate Research n Adanced Engneerng (IJIRAE) ISSN: 23492163 Volume 1 Issue 6 (July 214) Energy Comparson of MPPT Technques Usng Cuk Conerter R.B.Wankhede 1 PROF.U.B.Vadya 2 1 Student
More informationSpace Time Equalization-space time codes System Model for STCM
Space Tme Eualzaton-space tme codes System Model for STCM The system under consderaton conssts of ST encoder, fadng channel model wth AWGN, two transmt antennas, one receve antenna, Vterb eualzer wth deal
More informationSTUDY OF MATRIX CONVERTER BASED UNIFIED POWER FLOW CONTROLLER APPLIED PI-D CONTROLLER
Journal of Engneerng Scence and Technology Specal Issue on Appled Engneerng and Scences, October (214) 3-38 School of Engneerng, Taylor s Unversty STUDY OF MATRIX CONVERTER BASED UNIFIED POWER FLOW CONTROLLER
More informationAC-DC CONVERTER FIRING ERROR DETECTION
BNL- 63319 UC-414 AGS/AD/96-3 INFORMAL AC-DC CONVERTER FIRING ERROR DETECTION O.L. Gould July 15, 1996 OF THIS DOCUMENT IS ALTERNATING GRADIENT SYNCHROTRON DEPARTMENT BROOKHAVEN NATIONAL LABORATORY ASSOCIATED
More informationINSTANTANEOUS TORQUE CONTROL OF MICROSTEPPING BIPOLAR PWM DRIVE OF TWO-PHASE STEPPING MOTOR
The 5 th PSU-UNS Internatonal Conference on Engneerng and 537 Technology (ICET-211), Phuket, May 2-3, 211 Prnce of Songkla Unversty, Faculty of Engneerng Hat Ya, Songkhla, Thaland 9112 INSTANTANEOUS TORQUE
More informationDIMENSIONAL INSPECTION OF SAMPLES IN THE NANOMETER SCALE BY MEANS OF THE SUPERCONTINUUM LIGHT
DIMENSIONAL INSPECTION OF SAMPLES IN THE NANOMETER SCALE BY MEANS OF THE SUPERCONTINUUM LIGHT Ondřej ČÍP, Radek ŠMÍD, Břetslav MIKEL, Martn ČÍŽEK, Bohdan RŮŽIČKA and Jose LAZAR Insttute o Scentc Instruments,
More informationTransistor Characterization and Modeling and the Use of Embedding Device Models for the Design of Microwave Power Amplifiers
Transstor Characterzaton and Modelng and the Use of Embeddng Dece Models for the Desgn of Mcrowae Power Amplfers Patrck Robln, Francsco J. Martnez-Rodrguez,, Hsu Chen Chang, Chenggang Xe and Jose I. Martnez-opez
More information