Development of Algorithm, Architecture and FPGA Implementation of Demodulator for Processing Satellite Data Communication

Transcription

1 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 37 Development of Algorthm, Archtecture and FPGA Implementaton of Demodulator for Processng atellte Data Communcaton K.. Natara *, Dr. amachandran** and Dr B.. Nagabushan *** * M. G... Unversty, Chenna, Inda ** Natonal Academy of Excellence, Bangalore, 566, Inda *** anlab Technologes, Bangalore, 5638, Inda ummary Ths paper proposes a novel VLI archtecture for the demodulator for processng satellte data communcaton. The overall recever algorthm s dvded nto two parts: one to be mplemented on an FPGA and the other on a DP processor. A new dstrbuted arthmetc based archtecture for mplementng a amplng ate Converter s also proposed. The man advantage of ths archtecture s that t does not employ any MAC unt, whose operatonal speed s, generally, a bottleneck for hgh flter throughput. Instead, t makes extensve use of LUTs and hence s deally suted for FPGA mplementaton. Archtecture for Dgtal Frequency yntheszer, whch gves 6 db spectral purty, s also presented. The developed FPGA core conssts of a mxer and two numbers of 93 tap, C flters to accept modulated, -bt, sgned ADC output at a samplng frequency of.536 MHz and convert t nto In-phase (I) and Quadrature-phase (Q) channel outputs, each of sze 6 bts, sgned, at half the samplng frequency. The man desgn goals n ths work were to mantan low system complexty and reduce power consumpton and chp area requrements. These archtectures were coded n Verlog HDL and mplemented on Xlnx FPGA. The desgn was syntheszed wth XCV6-4 FPGA and occupes about 36 slces wth an equvalent gate count of about 45 and operatng at a maxmum frequency of 9.8 MHz. The entre modulator and demodulator have been coded n Matlab n order to valdate the hardware results. The hardware and MATLAB results compare favorably. Key words: Algorthm, Demodulator, Lnear algebra, Dstrbuted Arthmetc Archtecture, amplng ate Converter, Dgtal Frequency yntheszer, Feld Programmable Gate Arrays.. Introducton World demand for communcaton facltes carryng many dfferent types of real-tme and non-real-tme sgnals such as voce, data, facsmle, and vdeo has been growng by leaps and bounds durng the past few decades. The ncreasng demand and the resultng large amount of world-wde communcaton traffc naturally calls for lnks wth very large transmsson bandwdth. A number of demodulator algorthms for data communcaton have been reported by researchers [- ]. Dgtal Frequency yntheszer (DF) Algorthm and Archtecture developed are avalable n the lterature [3-5]. FPGA mplementatons of some of these archtectures were also reported [6-8]. A two stage estmaton scheme for demodulator for processng satellte data was proposed n our earler work [9], where carrer frequency estmaton was followed by tmng recovery under tranng. Theren the recever algorthm was parttoned nto two parts, one to be mplemented on FPGA and the other on DP. An overvew of the whole system archtecture was also presented and ts performance was evaluated. In ths paper, we revew the basc theory of dstrbuted arthmetc and ts modfed versons to acheve a trade off between chp area and throughput. Then we present new archtectures for samplng rate converter and dgtal frequency syntheszer, whch results n the use of reduced memory. However, the DP mplementaton of the remanng part, namely, frequency and tmng offset, carrer recovery and LM are out of scope of the present work. The rest of ths paper s organzed as follows: In the next secton, samplng rate converter theory and optmzaton technques for OM are presented. Ths s followed by the detaled archtecture of samplng rate converter. The DF archtecture s developed n ecton 3. ecton 4 presents the mplementaton of mxer and C flters usng Verlog targeted on Xlnx FPGA. o also the results. Conclusons are presented n the last secton.. Implementaton of amplng ate Converter. Word-length ssues Eye patterns are often employed n the qualtatve evaluaton of recever performance. These patterns may be Manuscrpt receved July 5, 9 Manuscrpt revsed July, 9

2 38 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 obtaned usng the BPK system. The output of the matched flter n the recever s fed to the vertcal nput of an osclloscope and the symbol clock s fed to the external trgger of the osclloscope. The transmtted dgtal sgnal s recovered by samplng the receved analog sgnal and then makng a threshold decson. In the optmal case, the decson pont or samplng pont s the pont where the eye s most open. Whle mplementng the flter n a fxedpont platform such as an FPGA, the effect of fnte word length on the flter performance needs to be consdered. Excessve word length ncreases the hardware cost and reduces the speed, whereas smaller word length reduces the precson of flter coeffcents. For the present case of an C flter, we need to select the word length of the flter coeffcents such that we get mnmum nter-symbol nterference at the output of matched flter at the recever. The effects of the truncaton of flter coeffcents can be llustrated by way of an example. In ths example there s no nose n the channel and a roll-off factor of.4 s used. The sample pont s at t =.5. Fg. a shows the eye pattern obtaned usng MATLAB, for nfnte precson of C flter coeffcents. It may be noted that at the samplng pont, the II s neglgble. We also plot the eyepatterns for flter coeffcent word lengths of bts. For 8 bts and bts, there exsts a large amount of II at the samplng ponts. Ths s due to the presence of large quantzaton nose, whch manfests tself n the form of II, n the present case. Also, due to the fnte. Dstrbuted Arthmetc (DA) Dstrbuted Arthmetc s used to desgn bt-level archtectures for vector to vector multplcatons. In dstrbuted arthmetc, each word n the vector s represented as a bnary number; the multplcatons are reordered and mxed, such that the arthmetc becomes dstrbuted throughout the structure [, ]. Dstrbuted arthmetc s commonly used for mplementaton of convoluton operatons and dscrete cosne transform (DCT)... Convolutonal Dstrbuted Arthmetc Let us consder the nner product of two length-n vectors C and X: N Y = c x () = { } { } where, c ' s are M bt cons tan ts, No x ' s are coded as W bt ' s complement numbers. w, x can be wrtten as W x = x x, W, W = () ampltude Eye pattern for nfnte precson tme (second) a ampltude Eye pattern for wordlength = bts tme (second) Fgure Effect of flter coeffcent word length on eye-pattern a Eye-Pattern for nfnte precson b Eye-Pattern for -bt precson word length of flter coeffcents, the attenuaton of the flter response n the stop-band reduces. As the word length for flter coeffcents s ncreased, the II at the samplng ponts reduces. It may be noted that as the number of bts s ncreased from to 6 bts, the II at the samplng ponts remans approxmately constant, close to that due to nfnte precson n Fg. a. Thus, no maor gan s evdent n ncreasng the word length beyond bts. Therefore, we desgn our flter wth the coeffcent word length of bts. b ubsttutng () n (), we get W Y = CW (3) = Therefore, by nterchangng the summng order of and, the ntal multplcatons n equaton () are dstrbuted to another computaton pattern. nce the term C depends upon x,, whch has only N possble values, t s possble to pre-compute them and store them n a read only memory (OM). An nput set of N bts ( x,,x,,..., xn, ) s used as the address to retreve the correspondng C values. These ntermedate results are accumulated n W clock cycles to produce one Y value. Ths leads to multpler-free realzaton of vector multplcaton. Table shows the contents of the OM for N = 4. Fg. shows a typcal archtecture for the computaton of the nner product of two length-n vectors. The shft accumulator s a bt-parallel carry propagate adder that adds the OM contents to the prevously accumulated result. The nverter and the MUX are used for nvertng the output of the OM n order to compute C W. The control sgnal s when

3 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 39 = W and, otherwse. The computaton runs from = to = W and the result s avalable n bt parallel form after W clock cycles. Ths approach corresponds to bt-seral dstrbuted arthmetc. Table Contents of OM for N = 4 x, x, x, x 3, Contents of OM c c c c c c c c c c c c c c c c c c c c c c c c where W x = x x, W, W = ( W ) Defnng x, x,, for W d, = ( x W, x W, ), for = W and d, {, }. Equaton (4) can be rewrtten as W [ ( ), W x = d W ] (5) = Usng (5), () can be rewrtten as = W N N ( W ) ( cd, W ) ( c) = = = Now defnng N = D cd and we have, D, = N extra = c =, for W x, x, OM N wth words xn, D shft rght Y W ( W ) W extra (6) = Y = D D Equatons (4) to (6) characterze the OBC scheme. It was observed that the contents of the OM are mrrored across the lne between the eghth and the nnth rows n the OM table. Therefore, t s possble to reduce the OM sze by a factor of two. Table llustrates the new OM table. Fgure Archtecture for computng nner product of two length - N vectors usng Dstrbuted Arthmetc.. Dstrbuted Arthmetc wth offset-bnary codng (DA-OBC) In ths secton, the offset-bnary codng (OBC) s ntroduced, whch can reduce the OM sze by a factor of,.e., down to N-. Equaton () can be rewrtten as x = [ x ( x )] W [ ( ( ),, ) (,, ) W = xw xw xw xw ] (4) = Table Contents of OM wth DA OBC Codng (N = 4) x, x, x 3, Contents of OM c c c c3 ( ) / ( c c c3 c ) / ( c c c3 c ) / ( c c c c3 ) / ( c c c3 c ) / c ) / ( c c c3 ( c c c3 c ) / ( c c c c3 ) /

4 4 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9.3 Modfed DA-OBC Archtecture It can be observed from Table that the OM values except co term are mrrored along the lne between the 4 th and the 5 th rows. Therefore, the OM table of OBC scheme can be further reduced by a factor of two [6]. Table 3 llustrates the new OM table and Fg. 3 shows the archtecture for the computaton of nner product usng ths method. By repeated applcaton of ths method, the OM sze can be reduced up to words. To acheve the sze reducton of the whole system, the reducton n the number of OM cells and the decoder crcut nsde the OM should be larger than the hardware ncrease for control crcuts. Table 3 Modfed DA-OBC OM Contents (N = 4) dstrbuted arthmetc wth OM decomposton. The total sze of storage s now reduced from N to (N/K) K whch ncreases lnearly wth N. The OM access tme s also reduced along wth the OM sze. Ths reducton of the storage sze s balanced by a lnear ncrease of the computatonal complexty of the accumulator. x, x, xk, OM k words x k, OM k x k, words x N, OM k words x, x, x 3, Contents of OM D shft x, x 3, OM x N, N wth words x, c o c c c c3 ( ) / ( c c c c3 ) / ( c c c3 c ) / ( c c c c3 ) / x, D D shft rght D extra.4 OM Decomposton for Dstrbuted Arthmetc The OM sze of the conventonal dstrbuted arthmetc ncreases exponentally wth N. Generally, OM access tme can be a bottleneck for the speed of the whole system, especally when the OM sze s large. Therefore, reducng the OM sze s very mportant and s of great practcal concern. Explotng the lnearty of equaton (3), one possble soluton to ths problem s to dvde the N address bts of the OM nto N/K groups of K bts,.e., to mplement the OM of sze N wth N/K OMs of sze K and add the outputs of these OMs usng a mult-nput accumulator. Fg. 4 llustrates the archtecture for computng an N-nput nner product usng conventonal Fgure 3 Modfed DA-OBC Archtecture (N=4) Y Fgure 4.6 Decomposng N szed OM nto N/K OMs of sze K.5 amplng ate Converter Archtecture Havng revewed varous dstrbuted arthmetc based technques for vector nner product mplementaton, we wll now dscuss the hardware archtecture of samplng rate converter, whch makes use of these technques extensvely. The nput to the samplng rate converter s the output of the mxer, whch then gets multpled by cos(nπ /) and sn(nπ /) to brng the sgnal to baseband [9]. Then the mage sgnals are removed by the followng LPF, whch n the present case s the C flter. After that, the sgnal s down-sampled by a factor of two, so as to make t sutable for carrer recovery. Mathematcally, the output of the C, n the I-channel, can be wrtten as π In ( ) = hlp ( n) yn ( ) cos( n) N π = hlp ( m) y( n m) cos( ( n m)) m= Decmatng by, N I( n) = hlp ( m). y( n m).cos( π ( n m)) m= ubsttutng m by k, we get

5 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 4 K π I( n) = hlp ( k). y(n k).cos( (n k)) k = where K = ( N ) /, f N s odd and K = ( N / ), f N s even K LP k = K = h ( k). y(( n k)).cos( π ( n k)) = h ( k). y(( n k)).( ) LP k = ( n k) n = hlpi ( n) [( ) y( n)], where hlpi = hlp ( n), for n =,,,3,4... K (7) Effectvely, the nput data s decmated by two and sgn changes are appled to alternate remanng samples. The resultng data stream s fltered by a new low-pass flter. The mpulse response of the new n-phase low-pass flter h LPI (n) s gven by hlpi ( n ) = hlp( n ) for n =,,,, K I (8) It may be noted that the new flter processng speed s half of the nput data rate. mlarly, π Q( n) = hlp ( n) [ y( n). sn( n)] N π = hlp ( m). y( n m).sn( ( n m)) and Q( n m = ) = h LPQ ( n ) [( ) n y( n )], where h LPQ = h LP (n). Effectvely, the nput data s decmated by two and sgn changes are appled to alternate remanng samples. It may be noted that there s one sample relatve delay between the n-phase and quadrature channels. The resultng data stream s fltered by a new low-pass flter. The mpulse response of the new quadrature low-pass flter h LPQ (n) s gven by hlpq( n ) = hlp( n ) for n =,,,, K Q (9) from Mxer z n ( ) LPF h LPI LPF h LPQ Fgure 5 Combned mplfed tructure x x q Agan, the processng rate s half of the nput data rate. The overall dgtal quadrature demodulator s shown n Fg. 5. It may be noted that all samples are not passed to both dgtal flters. The "even" samples are passed to the nphase flter wth every other sample undergong a sgn change. mlarly, the "odd" samples are passed to the quadrature flter, and agan, every other sample also undergoes a sgn change. The two blocks are very smlar from the hardware archtectural pont of vew. Therefore, we wll dscuss the hardware archtecture of only one of these blocks n the next secton..5. Detaled desgn descrpton of I-channel Block ubsttutng values for n n equaton (7), we get I() = h()y() I() = - h()y() h()y().. 96 I() = h(k) y(-k) (-) -k k = = h()y() - h()y(98) h(4)y(96) - h(96)y(4) - h(88)y() - h(9)y() h(9)y(8) = h()[y(8) y()] - h()[y() y(98)] h(4)[y() y(96)] - h(96)y(4) I() = - h()[y() y()] h()[y() y()] - h(4)[y(4) y(98)] - h(96)y(6) I(4) = h()[y() y(4)] - h()[y(4) y()] h(4)[y(6) y()] - h(96)y(8) and so on. It can be seen that the sgn of all the terms contanng coeffcents h(), h(4), h(8),, h(96) s the same. mlarly, all the terms contanng coeffcents h(), h(6), h(),, h(94) bear the same sgn. Agan, the sgns get nverted n each succeedng even value of I(n). Also, due to the symmetry of the FI flter, the number of flter coeffcents reduces to 49 from 97, effectvely. However, mplementng these 49 coeffcents wth Dstrbuted arthmetc wll take a huge amount of memory ( 49 words). Thus, on breakng the OM nto smaller parts, usng mproved form of modfed DA-OBC and takng nto consderaton the symmetry of coeffcents and the

6 4 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 nverson of ther sgn n every succeedng value of I(n), we get the I channel flter archtecture as shown n Fg. 6. An extra sgnal sgn_pos s ntroduced to take care of sgn nverson. A hgh on sgn_pos gves a postve sgn for the terms contanng the coeffcents h(), h(4), h(8),,h(96), whereas a low on ths sgnal produces a negatve sgn for terms contanng coeffcents h(), h(6), h(),,h(94). These terms are then approprately mxed to produce values of I(n). The coeffcents of the smaller modules are as follows: A : h(), h(4), h(8), h(), h(6), h() A : h(), h(6), h(), h(4), h(8), h() A 3 : h(4), h(8), h(3), h(36), h(4), h(44) A 4 : h(6), h(3), h(34), h(38), h(4), h(46) A 5 : h(48), h(5), h(56), h(6), h(64), h(68) A 6 : h(5), h(54), h(58), h(6), h(66), h(7) A 7 : h(7), h(76), h(8), h(84), h(88), h(9) A 8 : h(74), h(78), h(8), h(86), h(9), h(94) Thus, the total OM sze needed reduces to 8* 4 words nstead of 49 words, as n the case of the smple DA esults To verfy the arthmetc based archtectural desgn, we compare the mpulse response of the desgn mplemented n VEILOG wth that coded n MATLAB. A random nput sequence s fed to the functonal block and results of MATLAB and VEILOG mplementatons are presented n Fg. 7a and b for comparson. It can be seen that the two outputs closely follow each other. The man advantage of ths archtecture s that t does not employ any MAC unt, whose operatonal speed s, generally, a MATLAB EPONE VEILOG EPONE Fgure 7 esponse of I-Channel Block n MATLAB and VEILOG a Impulse nput b andom Input equence bottleneck n flter throughput. Agan, t makes extensve use of LUTs and hence s deally suted for FPGA mplementaton. 3. Implementaton of Dgtal Frequency yntheszer We use a dgtal frequency syntheszer n our system to generate a sampled snusodal wave of frequency 7 KHz ± estmated carrer frequency offset MATLAB EPONE VEILOG EPONE Fgure 6 Telescopc Vew of I-Channel Block Implementaton 3. Introducton The maor advantage of Dgtal Frequency yntheszer s that ts output frequency, phase and ampltude can be precsely and rapdly manpulated under the control of a DP. Other nherent DF attrbutes nclude the ablty to tune wth extremely fne frequency and phase resoluton and to rapdly hop between the frequences. These combned characterstcs have made ths technology popular n mltary, radar and communcatons systems. 3. Analyss sgn_pos h(96) _ h(96) Varous technques are avalable n the lterature for quarter wave memory compresson, such as ne-phase dfference algorthm, Taylor seres expanson, Modfed underland Archtecture, Ncholas Archtecture, CODIC (Coordnate otaton Dgtal Computer) Algorthm, etc. The mplct goal of these phase-to-sne converson technques s to reduce the maxmum ampltude error for any phase angle, n effect mmckng the behavor of a LUT. In pursung ths goal, all archtectures become complex n one way or the other. Also, the OM sze becomes farly large as t grows exponentally wth the wdth of the phase accumulator, A A A 3 A 4 A 5 A6 A7 A CALING ACCUMULATO I(n)

7 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 43 whereas a large phase accumulator wdth s desrable n order to acheve fne frequency tunng. Truncatng the phase accumulator output, on the other hand, ntroduces spurous harmoncs. 3.3 Concept of the Archtecture used Instead of a OM LUT, a hardware-optmzed phase-tosne ampltude converter approxmates the frst quadrant of the sne functon wth eght equal-length pecewse lnear segments [8]. The man goal s to mantan low system complexty and reduce power consumpton and chp area requrements. The second am s to acheve a specfed spectral purty, whch s defned as the rato of the power n the desred frequency to the power n the greatest harmonc, across the syntheszer s tunng bandwdth. pectral purty s an essental desgn parameter for syntheszer used n communcaton systems, ensurng that undesred n-band sgnals reman below a gven threshold and are not detected. In order to acheve the frst goal, we approxmate a snusod as a seres of eght equal-length pecewse contnuous lnear segments, s( x ) = m ( x ) y, [,7] 8 where m s the slope of each segment and s carefully selected to elmnate the requrement for multplcaton by representng each one as a sum of at the most two powers of two. Ths s well known and often used technque [5]. We also restrct the precson of slope representaton,.e., the dfference between the smallest and the largest powers of two used; n effect puttng an upper bound on the adder s wdth. Equal length segments are selected to reduce the control system crcutry costs. In order to acheve a desred spectral purty, dfferent sets of m and y coeffcents are evaluated and the best one meetng the requrements s selected. 3.4 Descrpton of the archtecture The new DF archtecture s shown n Fg. 8. It corresponds to a set of coeffcents yeldng 6dB purty. The coeffcents are gven n Table 4. The phase to sne ampltude converter block ncludes a s complement to explot quarter wave symmetry, as prevously seen n other structures. Clearly, ths archtecture s sgnfcantly less complex than those of the other methods dscussed prevously. It does not nclude a OM. No multplers or squarng crcuts are requred. Equal length segments are used to smplfy the control crcutry. Only three ntegers need to be added and multplexers shown n Fg. 8 have been optmzed by combnng smlar nputs and mplemented n combnatonal logc. The phase accumulator s bts wde, truncated to bts. The two MBs are used for quadrant symmetry. The next three bts dentfy the segment. The remanng seven bts dentfy dfferent sub-angles. The two upper multplexers shft these remanng seven bts accordng to the slopes m, lsted n Table 4. In Fg. 8, the notaton {>>n} sgnfes a rght shft by n bts, or equvalently, dvson by n. The lower multplexer selects the approprate y approxmaton lsted n the table. The output from the multplexers s 3 bts wde, to account for the whole dynamc range of possble values. The three-operand adder sums the multplexer outputs together and rounds the result to 7 bts. Table 4 Lnear segment coeffcents for 6 db purty m y ½ /4 ½ 9/4 ¼ 384/4 3 /8 55/ /4 5 ½ ¼ 89/4 6 ½ 99/4 7 /8 97/4 3.5 esults of DF To verfy the archtecture, the desgn was coded n Verlog. The spectrum was obtaned by takng the DFT of one grand repetton of the system output data. It can be easly seen that all the spurs are at least approx. 6 db below the fundamental. pectra for other odd frequency control words are smlar, wth spurs no greater than those shown here. It has been shown [3] that the spectrum correspondng to two frequency control words that are relatvely prme to the phase accumulator s overflow values are permutatons of each other. The ampltudes shown n the spectra of Fg. 9 are, therefore, exact n ampltude to the spurs for any other odd frequency control word. Only ther locatons change. The spectral purty of the DF output s suffcent for the present system requrement.

8 44 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 ΔP 6 Phase accumulator 6 ωˆ MB s comp. 7 7 MB 3 MBs >> m u x >> >> >>3 m u x Format converter DF o/p y y y y 3 y 4 y 5 y 6 y 7 m u x Fgure 8 DF Archtecture ΔP = Ampltude (db) f (elatve to clock) f (elatve to clock) Fgure 9 Output pectrum

9 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July Implementaton of FPGA part of the demodulator 4. Introducton In our earler paper [9], synchronzaton technques and recever structure were dscussed. Also, the task of parttonng the recever algorthm nto two parts, one to be mplemented on FPGA and the other on DP, was performed. We presented a new archtecture for samplng rate converter mplementaton n ecton, whch results n the use of reduced memory utlzaton. The DP mplementaton of the remanng part s out of scope of the present work. In ths secton, we wll descrbe the hardware mplementaton detals of the FPGA part of the demodulator. * Maxmum operatng frequency #.536 MHz and $ 3.56 MHz are what s requred for normal operaton. 4.3 Verfcaton Fg. shows the blocks of the part of the demodulator mplemented usng Verlog and, the necessary Matlab modules requred for ts verfcaton. Matlab generates the nput sgnal for the Modulator. For the sake of testng, two sne wave frequences, KHz and KHz, one at a tme, are used as nput. The Matlab Modulator output s sgned, 6 bts wde. Ths serves as the nput for both the Matlab and Verlog demodulators as shown. 4. Implementaton of mxer and C flters usng Verlog on Xlnx FPGA A block dagram of the FPGA part of the demodulator as mplemented usng Verlog s shown n Fg.. The developed core conssts of a mxer and two numbers of 93 tap, C flters to accept modulated, -bt, sgned ADC output at a samplng frequency of.536 MHz and convert t nto n-phase (I) and quadrature-phase (Q) channel outputs, each of sze 6 bts, sgned, at half the samplng frequency. It may be noted that the core requres two nput clocks for successful operaton: clk_bt must be 8.5 tmes the frequency of clk_word frequency. These clocks may be easly generated from the samplng frequency, clk_word (.536 MHz) usng a PLL and three numbers of frequency dvders. Fg. shows the TL Vew of FPGA part of the demodulator after runnng the synthess usng ynplfy. The synchronous clock, clk_wordby, for the output channels, I and Q, s generated by the core and, the outputs may be regstered at the postve edge of ths clock when I_Q_vald s hgh. EDF fle generated by ynplfy tool s nput to the Xlnx place and route and the results for the same are tabulated n Table 5. Ths was followed by runnng Xlnx back annotaton and smulaton usng Modelsm. The results obtaned after back annotaton were verfed to be correct. FPGA DEVICE Xlnx Vrtex XCV6hq4-4 Table 5 FPGA Implementaton detals LOGIC GATE PEFOMANCE (MHz) * clk_word clk_bt 44, # 9.8 $ reset_n clk_word clk_bt dtn_vald freq_offset_vald dtn[:] freq_offset[4:] Fgure Block dagram of FPGA part of the demodulator [:] [4:] [:] [4:] mxer reset_n clk fltout_vald clk_bt fltn_vald dtn_vald freq_offset_vald outword_[5:] nword[:] outword_q[5:] freq_offset[4:] mxer_ [5:] [5:] [5:] [5:] clk_gen reset_n clk_wordby clk_word cg fl93_q clk reset_n outword[5:] nword[5:] fl93_q_ fl93_i clk reset_n outword[5:] nword[5:] fl93_i_ [5:] [5:] [5:] [5:] clk_wordby I_Q_vald Q_out[5:] I_out[5:] Fg. ynthess (ynplfy) TL Vew of FPGA part of the demodulator It may be noted that the nput to the Verlog demodulator s MB bts (and not the entre 6 bts) so as to keep the same precson as the ADC output n the exstng ADP mplementaton. 6-bt precson has been retaned for the nput to the Matlab demodulator snce t serves as a better standard reference for verfyng the Verlog mplementaton. The modulated sgnal, thus produced, s appled to both the Matlab and Verlog demodulators. The

10 46 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 I and Q channels are the requred outputs, and are each of wdth 6 bts, sgned. The Verlog desgn requres two clocks, clk_bt (3.56 MHz) and clk_word (.536 MHz) for ts operaton. The I and Q outputs from Verlog demodulator compare favorably wth the correspondng outputs of Matlab demodulator, whch has served as the reference for verfcaton of the hardware mplemented on FPGA. I and Q results are shown n Fg. 3 for KHz as an example. Fgure 3 Matlab and Verlog responses of I and Q channels at KHz eferences Fg. Blocks of the part of the demodulator mplemented usng Verlog and the Matlab modules for ts verfcaton 5. Conclusons Ths paper proposed a new dstrbuted arthmetc based archtecture for mplementng a amplng ate Converter. The man advantage of ths archtecture s that t does not employ any MAC unt, whose operaton speed s, generally, a bottleneck for hgh flter throughput. It makes extensve use of LUTs and hence s deally suted for FPGA mplementaton. An archtecture for Dgtal Frequency yntheszer, whch gves 6 db spectral purty was also presented. Both the archtectures were coded n Verlog HDL and mplemented on XILINX FPGA. The hardware and MATLAB results compare favorably. [] G. trang: Introducton to Appled Mathematcs, Wellesly Cambrdge Press (986). [] J. M. Trbolet: A New Unwrappng Algorthm, IEEE Trans. on Acoustc, peech and gnal Processng, Vol. AP-5, No-, pp (977). [3] Mathew P. Joseph: DP Algorthms for On-Board atellte Trans-multplexer and ecever, M Thess, IIT Madras, Inda (). [4]. Haykn: Adaptve Flter Theory, Prentce-Hall, nd Edton (99). [5] M. E. Frerkng: Dgtal gnal Processng n Communcaton ystems, Van Nostrand enhold, NY (993). [6] E. A. Lee and D. G. Messerschmtt, Dgtal Communcaton, econd Edton, Alled Publshers Lmted, 994. [7] J. Proaks: Dgtal Communcatons, Thrd Edton, Internatonal Edton, McGraw Hll (995). [8] J.M.P. Langlos, D. Al-Khall,.J. Inkol: A Hgh Performance, Wde bandwdth, Low cost FPGA based Quadrature Demodulator, Proceedngs of IEEE Canadan Conference on Electrcal and Computer Engneerng (999). [9] Henry amuel, Bennet C. Wong: A VLI Archtecture for a Hgh peed, All Dgtal, Quadrature Modulator and Demodulator for Dgtal ado Applcatons, IEEE Journal on elected Areas n Communcaton, Vol. 8, No. 8 (99). [] aneev Dua: Algorthms and Archtectural Desgn of an Onboard atellte QPK ecever. M Thess, IIT Madras, Inda (3). [] P.P. Vadyanathan: Multrate ystems and Flter Banks,

11 IJCN Internatonal Journal of Computer cence and Network ecurty, VOL.9 No.7, July 9 47 Prentce Hall Inc., Eagle-woods Clffs, N.J. (993). [] Keshab K. Parh: VLI Dgtal gnal Processng ystems, John Wley & ons Inc. (999). [3] H. T. Ncholas, H. amuel, and B. Km, The Optmzaton of Drect Dgtal Frequency yntheszer n the Presence of Fnte Word Length Effects Performance, n Proc. Of 4 nd Annual Frequency Control ymposum, June 988, pp [4] J. M. P Langlos and D. Al-Khall, Hardware Optmzed Drect Dgtal Frequency yntheszer Archtecture wth 6 db pectral Purty, Proc. IEEE Internatonal ymposum On Crcuts and ystems, May. [5]. I. Lu, T. B. Yu and H. W. Tsao, Ppelned Drect Dgtal Frequency yntheszer Usng Decomposton Method, IEEE Proceedngs on Crcuts, Devces and ystems, Vol. 48, No. 3, June, pp [6] Fubng Yu: FPGA mplementaton of a fully dgtal FM demodulator, Communcatons ystems (ICC), The Nnth Internatonal Conference, pp (4). [7] Charoensak, C., Abeysekera,..: FPGA mplementaton of effcent Kalman band-pass sgma-delta flter for applcaton n FM demodulaton, OC Conference Proceedngs, IEEE Internatonal Volume, pp , - 5 ept. (4). [8] Zarf, M.H.; Frounch, J.; Asgarfar,.; Baradaran Na, M, FPGA mplementaton of a fully dgtal demodulaton technque for bomedcal applcaton, Proceedngs of IEEE Canadan Conference on Electrcal and Computer Engneerng, pp , 4-7 May (8). [9] K.. Natara,. amachandran, B.. Nagbushana, Development of Algorthm for Demodulator for Processng atellte Data Communcaton, IJCN, Vol. 9, No. 6, June 3, 9, pp and mplementatons on FPGAs/AICs for Vdeo Processng, DP applcatons, reconfgurable computng, open loop control systems, etc. He s the recpent of the Best Desgn Award at VLI Desgn, Internatonal Conference held at Calcutta, Inda and the Best Paper Award of the esson at WMCI 6, Orlando, Florda, UA. He has completed a vdeo course on Dgtal VLI ystem Desgn at the Indan Insttute of Technology Madras, Inda for broadcast on TV by Natonal Programme on Technology on Enhanced Learnng (NPTEL) and s beng broadcast n You Tube as well. He has also wrtten a book on Dgtal VLI ystems Desgn, publshed by prnger Verlag, Netherlands ( Dr B.. Nagabushana obtaned hs M. Tech. and Ph. D. degrees from Mysore Unversty and Indan Insttute of cence, Bangalore respectvely. He has wde academc as well as software ndustral experence for over 5 years. He has worked as Professor nvarous engneerng colleges as well as consultant to software ndustres lke OMED (oftware), Japan, BFL, CG- mth oftware Pvt. Ltd, KPIT Cummns Infosystems (Bangalore), Pvt. Lmted, an Lab Technologes etc. Hs research nterests nclude Wreless Communcaton, Neural Network, Fuzzy Logc and Embedded systems. He s the recpent of NDC Independence Day award for the year 99, Best Proect Executon award for the year from M/s BMC oftware, UA. K.. Natara obtaned hs ME degree from Bangalore Unversty, Inda n. He worked as Professor and Head of the Department durng -8 and currently he s the Post Graduate Coordnator n the Department of Electroncs and Communcaton n JB Insttute of Technology, Bangalore. Presently, he s pursung hs Ph. D. degree n Dr MG Unversty, Chenna. Hs research nterests nclude Wreless communcaton, FPGA mplementaton, Mcrocontroller and Embedded systems desgn. He s a member of MIE, MITE and IETE. Dr. amachandran obtaned hs M. Tech. and Ph. D. degrees from the Indan Insttute of Technology, Kanpur and Madras respectvely. He has wde academc as well as ndustral experence of over 3 years, havng worked as Professor n varous engneerng colleges as well as desgn engneer n ndustres n Inda and UA, desgnng systems and teachng/gudng students. Hs research nterests nclude developng algorthms, archtectures