Reactive power compensation for nonlinear loads using Fuzzy controller

Transcription

1 NT J CU SC 07, 0(4: E 0-9 ESEACH ATCE SSN eacte power compensaton or nonlnear loads usng Fuzzy controller Sreedhar K, SS Deeksht and D. Nagendra* Department o EEE, ATS ajampet, Kadapa, A.P. nda *Correspondng author: nagendra.dnagendra@gmal.com Abstract An mproed uzzy controller s used or power ratng, lter sze, compensaton perormance and power loss. At the ront end o a oltage source nerter (S an C lter has been used, whch prodes better swtchng harmoncs elmnaton whle usng much smaller alue o an nductor as compared wth the tradtonal lter. A capactor s used n seres wth an C lter to reduce the DC-lnk oltage o the DSTATCOM. Ths consequently reduces the power ratng o the S. Wth reduced DC-lnk oltage, the oltage across the shunt capactor o the C lter wll be also less. Thereore, the proposed DSTATCOM topology wll hae reduced weght, cost, ratng, and sze wth mproed ecency and current compensaton capablty compared wth the tradtonal topology. A systematc procedure to desgn the components o the passe lter has been presented. Here uzzy logc s used or controllng and compared wth DSTATCOM uzzy controller prodes maxmum ecency. Keywords: S; DSTATCOM; eacte power compensaton eceed: th Mar 07; esed: 9 th Jul 07; Accepted: 5 th September 07; JCS New berty Group 07 ntroducton Snce the statc capactors and nacte lters hae been used to enhance control qualty (PQ n a dsperson ramework. Be that as t may, these typcally hae ssues, or example, xed remuneraton, ramework parameter-subordnate executon, and conceable reerberaton wth lne reactance (Ostroznk et al., 00. An appropraton statc compensator (DSTATCOM has been proposed n the wrtng to conquer these dsadantages. t nuses response and sounds part o load streams to make source ebbs and lows adjusted, snusodal, and n stage wth the heap oltages. Nonetheless, a conentonal DSTATCOM requres a powerul apprasng oltage source nerter (S or load pay. The power ratng o the DSTATCOM s speccally relate to the current to be remunerated and the dc-nterace oltage (nzunza and Akag, 005. For the most part, the dc-connect oltage s kept up at much hgher esteem than the greatest estmaton o the stage to-unbased oltage n a three-stage our-wre ramework or tasteul remuneraton (n a three-stage three-wre ramework, t s hgher than the stage to-stage oltage (Ghosh and edwch, 00. Some mxture topologes hae been proposed to consder the preously mentoned mpedments o the customary DSTATCOM, where a decreased ratng dynamc lter s utlzed wth the latent parts. n hal and hal lters or engne dre applcatons hae been proposed. Accordng to Karank et al. (0, creators hae accomplshed a

2 Sreedhar et al., 07 dmnshment n the DC-connect oltage or recepte load pay. Howeer, the lessenng n oltage s restrcted because o the utlzaton o a -sort nteracng lter. Ths addtonally makes the lter greater n sze and has a lower slew rate or reerence ollowng. A C lter has been proposed as the ront end o the S n the wrtng to beat the mpedments o an lter. t ges better reerence ollowng executon whle utlzng much lower estmaton o unnoled parts. A C lter has been proposed as the ront end o the S n the wrtng to conquer the mpedments o an lter. t ges better reerence ollowng executon whle utlzng much lower estmaton o aloo segments. Ths addtonally dmnshes the cost, weght, and sze o the unnoled segment. n any case, the C lter utlzes a comparate DC-connect oltage as that o DSTATCOM utlzng an lter. Subsequently, hndrances because o hgh DC-nterace oltage are stll present when the C lter s utlzed. Fg.. Proposed DSTATCOM topology n the dstrbuton system to compensate unbalanced and nonlnear loads dcult to execute by alterng the nerter control structure. t wpes out the requrement or extra sensors. Ths paper proposes an mproed hybrd DSTATCOM topology where the C lter ollowed by the seres capactor s used at the ront end o the S to address the aorementoned ssues. Ths topology reduces the sze o the passe components and the ratng o the DC-lnk oltage and prodes good reerence trackng perormance smultaneously. A three-phase equalent crcut dagram o the proposed DSTATCOM topology s shown n gure. n ths topology addng o the seres capactor reduces the dc-lnk oltage and thereore, the power ratng o the S. Here, and represent the resstance and nductance, respectely, at the S sde; and represent the resstance and nductance respectely, at the load sde and C s the lter capactance ormng the C lter part n all three phases. A dampng resstance d s used n seres wth C to damp out resonance and to prode passe dampng to the oerall system. S and lter currents are a and a, respectely, n phase-a smlar or other phases. n addton, oltages across and currents through the shunt branch o the C lter n phase-a are gen by sha and sha, respectely, and smlarly or the other two phases. The oltages mantaned across the dc-lnk capactors are dc=dc=dcre. The DSTATCOM source and loads are connected to a common pont called the pont o common couplng (PCC. oads used Another sgncant ssue s reerberaton dampng o the C lter, whch may push the ramework toward shakness. One arrangement s to utlze dynamc dampng. Ths can be accomplshed utlzng ether extra sensors or sensor less plans. The sensor less dynamc dampng plan s anythng but here hae both lnear and nonlnear elements, whch may be balanced or unbalanced. n the tradtonal DSTATCOM topology consdered n ths paper the same S s connected to the PCC through an nductor. n the C lter-based DSTATCOM topology an C lter s connected between the S and the PCC.

3 Sreedhar et al., 07 Proposed DSTATCOM topology A three-phase equalent crcut dagram o the proposed DSTATCOM topology s shown n gure. t s realzed usng a three-phase our-wre two-leel neutral-pont-clamped S. The proposed scheme connects an C lter at the ront end o the S, whch s ollowed by a seres capactor Cse. ntroducton o the C lter sgncantly reduces the sze o the passe component and mproes the reerence trackng perormance. Addton o the seres capactor reduces the DC-lnk oltage and, thereore, the power ratng o DSTATCOM control The oerall control block dagram s shown n gure. The DSTATCOM s controlled n such a way that the source currents are balanced, snusodal, and n phase wth the respecte termnal oltages. n addton, aerage load power and losses n the S are suppled by the source. Snce the source consdered here s nonst, the drect use o termnal oltages to calculate reerence lter currents wll not prode satsactory compensaton. Fg.. Controller Block Dagram the S. Here, and represent the resstance and nductance respectely at the S sde; and represent the resstance and nductance respectely at the load sde; and C s the lter capactance ormng the C lter part n all three phases. A dampng resstance d s used n seres wth C to damp out resonance and to prode passe dampng to the oerall system. S and lter currents are a and a, respectely, n phase-a smlar or other phases. n addton, oltages across and * a a * sa a ta (P Δ ag P loss currents through the shunt branch o the C lter n phase-a are gen by sha and sha, respectely, and smlarly or the other two phases. The oltages mantaned across the dc-lnk capactors are dc-dc = dcre. The DSTATCOM, source, and loads are connected to a common pont called the pont o common couplng (PCC. oads used here hae both lnear and nonlnear elements, whch may be balanced or unbalanced. n the tradtonal DSTATCOM topology consdered n ths paper, the same S s connected to the PCC through an nductor. n the C lter-based DSTATCOM topology, an C lter s connected between the S and the PCC. * b * c Thereore, the undamental poste sequence components o three-phase oltages are extracted to generate reerence lter currents ( a, b, and c based on the nstantaneous symmetrcal component theory. These currents are gen as ollows: Where,, ta tb and tc are undamental poste sequence oltages at the respecte phase load termnal, and b c * sb * sc b c tb (P Δ ag tc (P Δ ag P loss P loss ( ta ( tb ( tc. The terms

4 Sreedhar et al., 07 P ag and Ploss represent the aerage load power and the total losses n the S, respectely. The aerage load power s calculated usng a mong aerage lter or better perormance durng transents and can hae a wndow wdth o hal-cycle or ull cycle dependng upon the odd or odd and een harmoncs, respectely, present n the load currents. At any arbtrary tme t, t s computed as ollows: P ag t ( ta T t T a tb b tc c dt ( The total losses n the S are computed usng a proportonal-ntegral (P controller at the poste zero crossng o phase-a oltage. t helps n mantanng the o 0 khz, and a rpple current o A (5% o the rated current, the dc-lnk oltage and nteracng nductor alues are ound to be 50 and 6 mh, respectely. For the C lter based DSTATCOM topology, the dc bus oltage and lter parameters are chosen or the same set o desgn requrements. The sngle-phase equalent crcut dagram o the passe lter o the proposed scheme connected to the PCC s shown n gure 3. The term udc represents the nerter pole oltage wth u as a swtchng arable hang a alue o + or dependng upon the swtchng states. The procedure to desgn the lter parameters s gen here n detal. Fg. 3. Sngle phase crcut dagram o the passe lter dc-lnk oltage at a reerence alue dcre by drawng a set o balanced currents rom the source and s gen as, P loss K p e dc K e dt dc (3 e dc Where, K, p K and ( are the proportonal dcre dc dc eerence DC-nk oltage dcre : The oltage gan, ntegral gan, and oltage error o the P controller, respectely. The current error eabc s obtaned by subtractng the actual lter currents rom the reerence lter currents. The error s regulated around a predened hysteress band h usng the hysteress current controller (HCC, and GBT swtchng pulses are generated. DSTATCOM parameter desgn The DC bus oltage and nteracng lter alues o the tradtonal DSTATCOM are calculated based on the procedure outlned. For a supply oltage o 30, a load ratng o 0 ka, a maxmum swtchng requency across the dc capactor s a source o energy and s selected to achee good trackng perormance. Here, the use o a seres capactor and a small lter nductor has enabled a sgncant reducton n the dc-lnk oltage. n present case, a dc-lnk oltage o 0 s chosen, whch s ound to prode satsactory compensaton. Desgn o C Flter Parameters: Whle desgnng sutable alues o C lter components, constrants such as cost o nductor, resonance requency res, choce o dampng resstor d, and attenuaton at swtchng requency sw should be consdered. Consder

5 Sreedhar et al., 07 only o the passe lter, as shown n gure 3, s used. The alue o nductance s chosen rom a res π k k C (8 tradeo, whch prodes a reasonably hgh swtchng requency and a sucent rate o change o the lter current, such that the S currents ollow the reerence currents. At any pont o tme, the ollowng equaton represents the nductor dynamcs: Where, k =. The resonance requency must be greater than the hghest order harmonc o the current to be compensated. The equalent mpedance o the C lter approaches to zero at the resonance d dt t dcre (4 requency res, and the system may become unstable. Howeer, the system can be made stable by nsertng a For urther analyss, can be neglected. The nductor s desgned to prode good trackng perormance at maxmum swtchng requency, whch s acheed at zero supply oltage n the HCC. Takng these nto consderaton, nductance s gen by dcre dcre (h a ( max 4h a max (5 Where ha s allowable rpple n the current, and max s the maxmum swtchng requency acheed by the HCC. Once s chosen to attenuate lower order harmoncs, and C need to be desgned or elmnaton o hgher order harmoncs. At hgher requences, the mpedance oered by Cse wll be much lower than that o and can be neglected whle desgnng C lter parameters. Neglectng, and Cse at hgher requences, the ollowng transer unctons are obtaned: (s n (s s (s s (( / C / C (6 resstance d n seres wth the capactor. Usually, t s chosen n proporton to the capacte reactance at.e., res, cres, such that the dampng losses are mnmum whle assurng system stablty. The capacte reactance at resonance wll be cres ππ res C The power losses n the dampng resstor wll be (9 n P 3 (0 loss d h sh Where, h s the harmonc order o the current lowng through. n the C lter-based DSTATCOM topology, d d s chosen such that the dampng losses are mnmzed whle assurng that the sucent resonance dampng s proded to the system. Thereore, sucent resonance dampng o the system s a prme concern whle desgnng a dampng resstor n the proposed method. For C = 0 μf and res = (s n (s s(s / C (( / C (7 400 Hz, the reactance oered by C at res s 6.63 Ω. Here, a 5-Ω resstance s chosen, whch prodes From (6, expresson or resonance requency wll be, satsactory resonance dampng.

6 Sreedhar et al., 07 3 Desgn o Seres CapactorC : The man crteron se or desgnng o C se s that t should prode a low mpedance path or the undamental requency current component (Karank et al., 0. t was ensured that the shunt capactor C wll prode a hgh mpedance path or the lower order harmoncs. Thereore, a neglgble undamental current wll be drawn by C and can be neglected at the undamental requency. Thereore, the undamental current suppled by the lter whle consderng,,,, and Cse as seres connected s gen as, Here, n j( t se (, (, se Cse, and t s the undamental rms PCC oltage. The oltage n s the undamental rms oltage per phase aalable at the S termnal and s gen as, n dc Ater smplcaton, ( becomes ( n t j( n t ( ( se se ( (3 nteracng resstances are ery small compared wth reacte part and can be neglected. Thereore, the greater than the termnal oltage. Otherwse, the compensaton perormance wll not be satsactory. n the tradtonal topology where the seres capactor s absent, the maxmum njected current only depends upon the dc-lnk oltage (snce and t are xed. The maxmum reacte current that a compensator can supply must be the same as that o the maxmum load reacte current to achee unty power actor at the load termnal. The load current wll be maxmum when t wll oer mnmum mpedance (Zlmn = lmn + jlmn,.e., at ull load. Thereore, the maxmum undamental current drawn by the load n a partcular phase s gen as, max mn t j mn (5 Calculatng the magnary load current magntude rom the precedng equaton and equatng wth (Gupta, 0. t mn Zmn n t se A more generalzed expresson can be wrtten as, max p mn n t se (6 (7 Where, and p s the mn max t / Zmn mnmum load power actor gen by. mn / zmn magnary part magntude o wll be Hence, se wll be m [ n ] t se (4 se max n t p mn (8 t can be obsered rom (Gupta, 0 that to nject reacte current rom the compensator to the PCC, the undamental rms oltage per phase aalable at the S termnal (DC-lnk oltage must be much Fuzzy logc control: The Fuzzy logc control conssts o set o lngustc arables. Here the P controller s replaced wth Fuzzy ogc Control. The mathematcal modelng s not requred n FC.

7 Sreedhar et al., 07 Table. Smulaton Parameters nerence method System quanttes Source oltage Feeder mpedance near load C type nonlnear load type nonlnear load S parameters (tradtonal topology S parameters (C lter based alues 30 rms lne to neutral, 50 Hz Zs=+j3.4Ω Zla=30+j6.8Ω, Zlb=40+j78.5Ω, Zlc=50+j50.4Ω l = 50Ω, C = 000 µf l=50ω, =00 mh 50, dc µf, C 3000 dc 6 mh, 0.Ω 50, Cdc = 3000 dcre µf, 6.5 mh, mh, 5Ω, d There are seeral composton methods such as Max-Mn and Max-Dot hae been proposed and Mn method s used. Deuzzcaon A plant requres non uzzy alues to control, so deuzzcaton s used. The output o FC controls the swtch n the nerter. To control these parameters they are sensed and compared wth the reerence alues. To obtan ths the membershp unctons o uzzy controller are shown n gure 4. The set o FC rules are dered rom u=-[α E + (-α*c] (6 Where, α s sel-adjustable actor whch can regulate the whole operaton. E s the error o the system, C s the change n error and u s the control arable. A large alue o error E ndcates that gen system s not n the balanced state. the system s unbalanced, the controller should enlarge ts control arables to balance the system as early as possble. Fg. 4. Fuzzy logc Controller 0.05Ω,C=0µF S parameters (proposed topology Fuzzcaton 0, Cdc = 3000 dcre µf,.5mh, 0.6 mh, 5Ω, d 0.05Ω, C=0 µf,cc =50µF Membershp uncton alues are assgned to lngustc arables. n ths scalng actor s between and -. se esults The adantages o the proposed topology are that t uses a lower ratng o the S, has a smaller alue o the lter nductor, reduces the dampng power loss, and prodes mproed current compensaton. All these adantages are ered through PSCAD sotware. System parameters used to aldate the perormance are gen n table. Fgure 5(a shows the three-phase source currents beore compensaton whch are same as

8 Sreedhar et al., 07 load currents. These currents are unbalanced and dstorted due to presence o unbalanced lnear and nonlnear loads. Three-phase PCC oltages, as shown n gure 5(b, are unbalanced and dstorted due to presence o eeder mpedance. Fg. 5. Smulaton results wthout compensaton (a Source currents (b PCC oltages (d The three-phase source currents, whch are balanced and snusodal, are shown n gure 6(a. Fgure 6(b shows the three-phase PCC oltages. As seen rom waeorms, both the source currents and the PCC oltages contan swtchng requency components o the S. The three-phase lter currents are shown (Fg. 6c. The waeorms o oltages across upper and lower DC capactors, as well as the total DC-lnk oltage are presented (Fg. 6d. The oltage across each Fg. 6. Smulaton results or tradtonal topology. (a Source currents. (b PCC oltages. (c Flter currents. (d oltages across the DC lnk capactor s mantaned at 50, whereas total DC-lnk oltage s mantaned at 040 usng uzzy controller. Concluson n ths proposed method, desgn and operaton o an mproed uzzy controller s used to compensate reacte and harmoncs loads. The hybrd nteracng lter used here conssts o an C lter ollowed by a seres capactor. Ths topology prodes mproed load current compensaton capabltes whle usng reduced DC-lnk oltage and nteracng lter nductance. Addtonally, the current through the shunt capactor and the dampng power losses are sgncantly reduced compared wth the C lter-based uzzy controller. These contrbute sgncant reducton n cost, weght, sze, and power ratng by usng uzzy controller. Eecteness o the proposed topology has been (c aldated through extense computer smulatons.

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