Original scientific paper Journal of Microelectronics, Electronic Components and Materials Vol. 43, No. 3 (2013),

Transcription

1 Orgnal scentfc paper Journal of Mcroelectroncs, Electronc Components and Materals Vol. 43, o. 3 (03, Low-Voltage FGMOS Based Voltage-to-Current Converter Rshkesh Pandey, Maneesha Gupta Dept. of Electroncs and Comm. Engneerng, hapar Unversty, Patala, Inda Dept. of Electroncs and Comm. Engneerng, etaj Subhas Insttute of echnology, ew Delh, Inda Abstract: hs paper proposes a novel floatng-gate MOSFE (FGMOS based voltage-to-current (VC. he proposed VC has ral-to-ral nput dynamc range, low HD (total harmonc dstorton and low power dsspaton. he VC has been smulated usng SPICE n 0.5-mm CMOS technology wth the supply voltages of ±0.75V. he smulaton results of the VC demonstrate HD of less than %, 3-dB frequency of.63ghz and maxmum power dsspaton of 0.84mW. Keywords: Floatng gate MOSFEs, low-voltage, moblty degradaton, SPICE, VC. zkonapetostn napetostno-tokovn pretvornk na osnov FGMOS Izvleček: Članek predlaga nov napetostno-tokovn pretvornk (VC na osnov MOSFE (FGMOS s plavajočm vrat. Predlagan VC pretvornk ma poln vhodn napetostn obseg, nzko HD (dnamčno harmončno dstorzjo n nzko dspacjo moč. VC pretvornk je bl smulran s SPICE v 0.5-mm CMOS tehnologj z napajalno napetostjo ±0.75V. Smulacje VC pretvornka zkazujejo HD manjš od %, 3 db pr.63 GHz n največjo dspacjo moč 0.84 mw. Ključne besede: MOSFE s plavajočm vrat, nzka napetost, degradacja moblnost, SPICE, VC pretvornk * Correspondng Author s e-mal: rshp3@gmal.com Introducton Low-voltage operaton has become a major desgn ssue for the analog sgnal processng applcatons. hs s because a low-voltage power supply reduces the power dsspaton whch ncreases the battery lfetme and the relablty of the portable systems. Some of the low-voltage technques used to reduce supply voltages are level shfters, self-cascode MOSFEs, sub-threshold MOSFEs, bulk-drven MOSFEs and floatng-gate MOSFEs (FGMOS [-]. Out of these, FGMOS presents a unque advantage of programmablty of the threshold voltage. he other advantage of FGMOS s ts compatblty wth standard double-poly CMOS process technology. he FGMOS transstors have found many applcatons n electronc programmng [3], dgtalto-analog (D/A and analog-to-dgtal s [4], neural networks [5], voltage-controlled resstors [6]-[9], operatonal transconductance amplfer [0], multplers [], squarers []-[], etc. he voltage-to-current (VC s extensvely used n the desgn of mxers/ modulators, voltageto-frequency s and nterface unts between crcuts employng voltage-mode sgnal processng and those usng current-mode processng. In addton, VC s are used as basc buldng blocks to perform varous computatonal functons, such as square-rootng, squarng, multplyng, sum of squares and dfference of squares, etc. [3]-[4]. he lnearty and bandwdth are the usually concerned specfcatons of VC whch domnate whether ts performance s adequate. he nonlnear effects of VC manly ncludng nonlnear second-order V-I characterstc, body effect, moblty degradaton, temperature varaton and so on [5-9]. Recently, many researchers have been developed a fxed gan V-I nput stage wth programmable gan current mrrors [0]-[3]. However, these structures ncrease 73 MIDEM Socety

2 R. Pandey et al; Informacje Mdem, Vol. 43, o. 3(03, complexty and power dsspaton. In ths paper, we have proposed a wde band lnear VC wth moblty degradaton and channel length modulaton compensaton. he paper s organzed as follows. he operaton of the FGMOS s descrbed n secton. In secton 3, the FGMOS based VC s proposed. he detaled analyss of second-order effects on the performance of the proposed VC s dscussed n secton 4. In secton 5, SPICE smulaton results are presented to verfy the theoretcal analyss and to demonstrate the effectveness of the proposed crcut. he paper s concluded n secton 6. Operaton of FGMOS he basc structure of n-type, -nput FGMOS s shown n Fgure. he frst poly-slcon layer over the channel forms the floatng gate and the second poly-slcon layer forms -nput gates that are located over the floatng gate. he symbol and equvalent crcut model for an -nput FGMOS are shown n Fgures. (a and (b, respectvely. In both the fgures, V (for,,, are the control nput voltages and D, S and B are the dran, source and substrate, respectvely. Fgure : -nput FGMOS Fgure : FGMOS (a Symbol (b Equvalent crcut Where C, C, C 3,, C are the nput capactances between control gates and floatng gate, C s the sum of -nput capactances, C fd s the parastc capactance between floatng-gate and dran, C fs s the parastc capactance between floatng-gate and source, C fb s the capactance between floatng gate and substrate, V s the nput voltage of th nput gate, V DS s the dran-to-source voltage, V SS s the source voltage, V BS s the substrate-to-source voltage (usually, the value of V BS s chosen as zero volt to avod body effect, and Q FG s the resdual charge. he resdual charge Q FG s trapped n the oxde-slcon nterface durng the fabrcaton process. he trapped resdual charge gves rse to large varatons n the threshold voltage of the FGMOS. he removal of the trapped charge n the FGMOS s possble by usng the method suggested n [5-6], n whch the frst poly-slcon layer s connected to the metal-k (where k represents the top most metal layer, whch s deposted and etched last layer. By ths contact, the floatng gate s not connected to any other part of the crcut, so t wll not affect the operaton of the FGMOS. herefore, Eq. ( reduces to V FG CV + C V + C V fd DS fs SS C where C s the total capactance and s gven as C C + C + C + C (3 fd fs fb C If >> C fd, C fs, Eqs. ( and (3 are modfed as: V C FG CV C ( ( (4 C (5 he current equaton of -nput FGMOS has been obtaned by modfyng the current equaton of conventonal MOSFE. he current I p n the saturaton regon s expressed as follows: he -nput control gates are capactvely coupled to the floatng gate. Hence, the voltage on the floatng gate ( VFG can be determned usng the charge conservaton law as [4]: CV I V V p DD p C (6 74

3 R. Pandey et al; Informacje Mdem, Vol. 43, o. 3(03, where K p m p C ox (W/L s the transconductance parameter, m p s the moblty of holes, C ox s the gateoxde capactance per unt area, (W/L s the aspect rato and V p s the threshold voltage. 3 FGMOS based voltage-to-current he proposed FGMOS based voltage-to-current (VC s shown n Fgure 3. In ths fgure, the FGMOS transstors M, M, M 3 are used to develop voltage-to-current converson whereas the conventonal MOS transstors M 5, M 6, M 7 and M 8 are used to provde proper basng condton. All these transstors are based n the saturaton regon. he transstors M, M, M 3 are perfectly matched.e. K p K p, V p V p and k k k, where,,3,4. he appled bas & nput gate voltages of transstors M, M, M 3 are V b &V I, V b &-V I, V b &-V I and V b &V I, respectvely. he transstors M 5 and M 6 form the current mrror and transstors M 7 and M 8 set the bas current. From Fgure 3, t s evdent that there s no body effect n the proposed crcut. he output current I o s gven as ( ( I I I I + I I + I (7 o p p p3 p4 Where I p, I p, I p3, and I p4, are the currents of transstors M, M, M 3, respectvely. Usng Eq. (6, the currents I p, I p, I p3, and I p4 are gven as ( ( Ip VDD k Vb + VI Vp (8 I ( ( p VDD k Vb VI Vp (9 ( ( Ip3 VDD k Vb VI Vp (0 I ( ( p4 VDD k Vb + VI Vp ( Where k C /C s capactve couplng rato, V I & V I are nput voltages, V b s the bas voltage and V DD s the supply voltage. Substtutng Eqs. (8 - ( n Eq. (7, the output current I o s gven as ( I A V V ( o I I where A K p k( VDD kv b Vp. Equaton ( gves the lnear relatonshp between the output current (I o and the dfferental nput voltage (V I - V I. Hence, Fgure 3 behaves as VC. 4 Second order effects In ths secton, the effects of channel length modulaton and moblty degradaton on the proposed VC are dscussed. 4. Channel Length Modulaton Effect he current I p of -nput FGMOS ncludng channel length modulaton effect s gven as Ip ( VDD k( Vb + VI Vp( +λ VDS (3 where l s the channel length modulaton parameter. Consderng ths effect, Eqs. (8- ( are modfed as Ip ( VDD k( Vb + VI Vp( +λ VDS (4 Ip ( VDD k( Vb VI Vp( +λ VDS (5 Ip3 ( VDD k( Vb VI Vp( +λ VDS3 (6 Ip4 ( VDD k( Vb + VI Vp( +λ VDS4 (7 From Fgure 3, t can be seen that V DS V DS and V DS3 V DS4. Substtutng the values of I p, I p, I p3, and I p4, from Eqs. (4-(7 and V DS V DS & V DS3 V DS4 n Eq. (7, the output current I o s gven as Fgure 3: Proposed FGMOS based VC ( I A V V + B+ C+ D (8 o I I 75

4 R. Pandey et al; Informacje Mdem, Vol. 43, o. 3(03, where A K p k( VDD kv b Vp ; ( ( ( ( ( ( ( BλK V k V V V V ; p DD b p DS DS3 λ C k VI+ VI VDS VDS3 and D k K V kv V V V V V λ p DD b p DS+ DS3 I I. For smaller values of (V DS - V DS3 and (V - V, the I I effect of channel length modulaton n Eq. (8 can be neglected. 4. Moblty Degradaton Effect he current I p of -nput FGMOS ncludng moblty degradaton effect s gven as I p ( VDD k( Vb + VI Vp +θ ( + ( VDD k Vb VI Vp ( (9 In Eq. (9, θ V DD k ( V b + V I V p <<, where Q s the moblty degradaton parameter. Usng Bnomal theorem expanson and neglectng the hgher order terms, Eq. (9 s approxmated as ( ( ( ( ( Ip VDD k Vb + VI V p. θ VDD k Vb + VI Vp (0 Includng ths effect, Eqs. (8- ( are modfed as Ip ( VDD k( Vb + VI Vp ( θ( VDD k( Vb + VI Vp ( Ip ( VDD k( Vb VI Vp ( θ( VDD k( Vb VI Vp ( Ip3 ( VDD k( Vb VI Vp ( θ( VDD k( Vb VI Vp (3 Ip4 ( VDD k( Vb + VI Vp ( θ( VDD k( Vb + VI Vp (4 Usng Eqs. (-(4 n Eq. (7, the output current I o s gven as From equaton (6, t can be seen that the second and thrd terms are very smaller than the unty, causes only the gan error. Snce output current ( I o s vared wth the dfferental nput voltage ( VI - VI, moblty degradaton effect can be neglected. 5 Results and Dscusson he proposed VC has been smulated usng SPICE n 0.5mm CMOS technology. he VC operates wth the supply voltages of ± 0.75V. he varous parameters of the desgned VC are lsted n able. able : Varous crcut parameters Crcut parameters Values CMOS echnology 0.5μm Vb 0.75V Vp λ 9.6X0-3 θ 0.05 Fgure 4 shows the I-V characterstc of VC and plots the output current I o versus dfferental nput voltage V - V. In ths fgure, blue and red lnes I I denote the current/voltage characterstc for V whle I V 0 and for V whle V 0 respectvely. Fgure 5 I I I shows the HD obtaned n the output waveform as a functon of the peak-to-peak dfferental nput voltage. From ths fgure, t s observed that for dfferental nput voltage swngs as large as.5v, dstorton s stll low (< 0.9%. he total power dsspaton of ths crcut s.84mw. Fgure 6 shows the frequency response of VC and t s observed that the response remans constant tll.63ghz. (5 or ( VI + VI + VIVI ( DD b p 3θ θ Io A( VI VI ( VDD kv b Vp k V k V V (6 Fgure 4: I-V characterstc of the proposed VC 76

5 R. Pandey et al; Informacje Mdem, Vol. 43, o. 3(03, Concluson Fgure 5: HD vs. dfferental nput voltage ampltude In ths paper, a new low-voltage FGMOS based VC operates wth the supply voltages of ± 0.75V has been presented. he nherent advantages of ths crcut are wde nput range, low power dsspaton, low HD and wde frequency range whch make t sutable for low-voltage sgnal processng applcatons. he analyss of the channel length modulaton and moblty degradaton effects show that they have lttle nfluence on the proposed crcut. References Fgure 6: ransconductance (I o /(V I -V I curve for Fgure 3 able compares the proposed FGMOS based voltage-to-current and the voltage-tocurrent reported by Srnvasan et al. n [7]. It s observed that FGMOS based voltage-to-current proposed n ths manuscrpt has lower supply voltage requrement, lower power dsspaton and wder nput voltage range as compared to the exstng crcut. able : Comparson of FGMOS based voltage-tocurrent wth the voltage-to-current reported n [7] Crcut parameters Voltage-tocurrent [7] Proposed FGMOS based voltage-tocurrent Supply voltage ot avalable ± 0.75V CMOS technology 0.5 µm 0.5 µm Input voltage range ± 500 mv ± 750 mv Power dsspaton ot avalable 840 µw -3dB frequency 00 MHz.63 GHz HD ot avalable Less than 0.9%. Sanchez-Snenco, E., Andreou, A.G. Low Voltage/ Low Power Integrated Crcuts and Systems. IEEE Press, ew York, Yan, S., Sanchez-Snenco, E. Low Voltage Analog Crcut Desgn echnques: A utoral. IEICE rans. Analog Integrated Crcuts and Systems, 000, Vol. E00 A, no., p Berg, Y., Lande,. S. Programmable floatng gate MOS logc for low-power operaton. In Proceedngs of IEEE Int. Symp. Crcuts Systems- ISCAS-97, Hong Kong, 997, p Lmng, Y., Embad, S.H.K., Sanchez-Snenco, E. A floatng gate MOSFE D/A. In Proceedngs of IEEE Int. Symp. Crcuts Systems, Hong Kong, 997, p Lee, B. W., Sheu, B. J., Yang, H. Analog floatng gate-synapses for general purpose VLSI neural computaton. IEEE rans. Crcuts Syst., 99, vol. 38, p Gupta, M., Pandey, R. Fgmos Based Low-Voltage unable Floatng Resstor. Journal of Actve and Passve Electronc Devces, 0, vol. 6, no. -, p Gupta, M., Pandey, R. Fgmos Based Voltage- Controlled Resstor and Its Applcatons. Mcroelectroncs Journal, 00, vol. 4, no., p Pandey, R., Gupta, M. Fgmos based tunable grounded resstor. Analog Integrated Crcuts and Sgnal Processng, 00, vol. 65, no. 3, p Pandey, R., Gupta, M. Fgmos Based Voltage- Controlled Grounded Resstor. Radoengneerng journal, 00, vol. 9, no. 3, p Ramrez-Angulo, J., Cho, S.C., Altamrano, G.G. Low voltage crcuts buldng blocks usng multple nput floatng gate transstors. IEEE rans. Crcuts Syst. I, 995, 4, no., p Vlasss, S., Sskos, S. Desgn of voltage-mode and current-mode computatonal crcuts. IEEE 77

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