Analysis and Design of Charge Pumps for Telecommunication Applications

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1 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons Vassls Kalenterds, Konstantnos Papathanasou, and Stylanos Sskos Electroncs Laboratory, Physcs Department, Arstotle Unversty of Thessalonk 5414 Thessalonk, Greece Abstract. Ths chapter addresses modern telecommuncaton ntegrated crcuts from the syntheszer focal pont; n partcular t concentrates at the analyss and the desgn of ntegrated charge pump crcut blocks. It presents an overvew of charge pump topologes n addton to a coherent analyss of the assocated benefts and shortcomngs of all crcut alternatves. Moreover a novel favorable charge pump combnng current steerng technques wth well utlzed unty gan buffers n a novel, noseless feedback scheme, s ntroduced to mprove on swtchng speed, nherent charge pump ac nose, dead-zone nterval, theore overall steady state alased loop nose; whle on the other hand ths charge pump exhbts superb DC matchng characterstcs n a wde output voltage range. Furthermore a well documented estmaton of the actve devces that contrbutes mostly to the overall charge pump nose performance s presented. Also an assocated mathematcal analyss concernng the frequency content of the charge pump nose current s gven. Ths proposed topology manfests ts applcablty to charge pump alternatves, as t s demonstrated by the assocated smulaton results from a 0.18μm desgn. Because of the low-nose and accurate propertes of ths mproved charge pump, t s deally suted to modern telecommuncaton standards syntheszer realzatons. 1 Introducton Fully monolthc Phased-Locked Loops (PLLs) are essental buldng blocks, wdely used n modern communcaton or complex dgtal systems [1-8]. A PLL based on a charge pump s often perred over other syntheszer alternatves, because t exhbts a wde capture range wth no systematc phase offset and arguably provdes one of the smplest and most effectve desgn platforms [9-14]. The Charge Pump based PLL also provdes flexble desgn tradeoffs by decouplng varous desgn parameters such as the loop bandwdth, dampng factor and lock range []. Fgure 1 shows a typcal mplementaton of a charge pump based PLL. It conssts of a Phase/Frequency Detector (PFD), a Charge Pump (CP), a Loop Flter (LF), a Voltage Controlled Oscllator (VCO) and a dvder. The most wdely used PFD generates a par of dgtal pulses correspondng to the phase/frequency error between the erence clock f and the VCO output, by comparng the postve (or negatve) edges of the two nputs. The CP crcut converts the dgtal pulses nto an analogue current whch s consequently ntegrated producng a voltage on the passve (or actve) loop flter. Ths voltage drves C. Pguet, R. Res, and D. Soudrs (Eds.): VLSI-SoC 008, IFIP AICT 313, pp , 010. IFIP Internatonal Federaton for Informaton Processng 010

2 44 V. Kalenterds, K. Papathanasou, and S. Sskos the VCO crcut block whch n turn produces the syntheszed frequency of operaton as t s demanded by the system specfcaton. However, some non-dealtes of the CP such as DC msmatch of the chargng/dschargng currents and gltches degrade the performance of the overall loop. Moreover the nose of the charge pump s the domnant close-n phase nose contrbutor n a PLL [15]. Several charge pump mplementatons have been proposed n the assocated lterature [16-18]. In [16, 17] an opamp has been used n order to keep the dc msmatch current, and hence the resultant phase offset at a mnmum level and mprove the overall performance. Ths n effect adds sgnfcant nose contrbuton at the output of the proposed charge pump due to the ncreased gan ntroduced by the opamp. Others [18] assume that the and sgnals from the PFD that drve the charge pump swtches could not be smultaneously hgh, to avod the dc msmatch between the pump-up and pump-down currents. Ths s a fallacy because at lock both the and sgnals are hgh for a gven short tme to ensure the elmnaton of the PLL dead-zone, whch f present wll degrade sgnfcantly the n-band nose suppresson characterstc functon of the PLL. The objectve of ths chapter s the desgn of an mproved sngle-ended low nose charge pump wth low dc msmatch current, hgh voltage output range and programmable gan. The second secton depcts some typcal charge pump archtectures ether for sngle-ended or dfferental desgn, along wth the advantages and dsadvantages of each category. In the thrd secton a detaled analyss of the mproved charge pump s presented and compared to other alternatve desgns. Also the nose contrbuton of the mproved charge pump actve devces to the total output nose s gven wth the approprate mathematcal nose analyss. In the fourth secton the smulaton results from three alternatve methods (DC, PSS and Pnose) are presented, over temperature and process corners for the charge-pump key specfcatons to sgnfy the applcablty of the overall approach. Fnally the key concludng remarks of ths chapter are gven n the last secton. Charge Pump F Fdv PFD LF VCO Fout DIVIDER Fg. 1. Block level dagram of a charge pump based PLL CMOS Charge Pump Archtectures.1 Sngle-Ended Charge Pump Archtectures Sngle-ended charge pump crcuts are an elegant approach to system flexblty, lowpower consumpton, mnmzaton of pads and external components, or area. The output

3 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons 45 current of the charge pump can be as hgh as 4.5mA [3] at lock to provde better spur performance thus less leakage current and to have hgh SNR for low nose contrbuton to the PLL, whle ths current can be sgnfcantly more whle the PLL s n the trackng perod, to mprove on settlng tme. By usng tr-state operaton, the current consumpton of the charge pump s lmted to a few hundred μa dependng on the erence clock frequency and the delay of the PFD. Fgure shows some typcal sngle-ended charge pump topologes. IUP I UP M5 M6 M Out M3 M4 M1 M Out M1 + - M4 M3 M4 M3 M M1 I DN I DN I CP I CP Fg.. Sngle-ended charge pump archtectures: a) wth current steerng swtch, b) wth unty gan actve amplfer and c) wth NMOS swtch only Fgure a shows a charge pump utlzng a current steerng swtch. Ths structure provdes hgh speed swtchng for a sngle-ended charge pump, snce the swtchng tme s mproved by the current steerng propertes of the assocated swtchng par (M1-M3 and M-M4). Another charge pump approach utlzng current steerng wth an actve amplfer [4-5] s shown n fgure b. Ths unty gan amplfer, buffers the voltage at the output node forcng the dran voltage of the current sources I DN and I UP to be the same when M1 and M are on or when they are off. Ths reduces the charge sharng effect, when the swtch s turned on. Ths archtecture ensures fast transent response through current steerng, reduces the effect of any parastc capactance, at the expense of extra current. Fnally, n fgure c the nherent msmatch of pmos and nmos transstor s avoded by usng only nmos swtches [6]. Snce the current does not flow n the current mrror, (M5 and M6), when the UP swtch s turned off, the current mrrors stll lmt the performance unless large current s used [3].. Dfferental Charge Pumps A fully dfferental charge pump has several advantages over the conventonal sngleended charge pump [7-8]. Frstly, the swtch msmatches between nmos and pmos transstors do not substantally affect the overall performance. Ths relaxes the matchng requrement between the two type of transstors. Secondly, the dfferental charge pump has only nmos swtchng transstors thus the nverter delays for the and sgnals are fully symmetrc and theore do not generate any offset. Thrdly, ths

4 46 V. Kalenterds, K. Papathanasou, and S. Sskos confguraton doubles the range of the output voltage complance compared to the sngle-ended charge pump. Ths s a sgnfcant advantage for low voltage operaton, snce the lmted output voltage range of the charge pump makes t dffcult for the VCO to meet the specfed tunng range. Fourthly, the dfferental output stage s less senstve to the leakage current, snce the leakage current behaves as a common-mode offset at the dual output stages. Lastly, the use of two on-chp loop flters provdes better mmunty to the supply, ground and substrate nose, whle the lack of bond wre nductors facltates faster swtchng speeds and reduces transent oscllatons. However, these advantages can only be acheved at the cost of extra area due to the use of two loop flters, common-mode feedback crcutry [3], hgher nose levels and power consumpton mposed by the potental ntroducton of an actve flter and most mportantly the flexblty of alterng the overall PLL loop characterstcs by changng the loop flter should ths prove desrable. 3 Improved Charge Pump Desgn The mproved accurate low nose charge pump s shown n fgure. It s a sngleended tr-state charge pump wth programmable gan. Ths topology exhbts mproved swtchng speed, snce all nodes are precharged to the resultant operatng ponts and the current s ether steered to the output or to the unty-gan buffer. The two opamps O P1 and O P are used n order to mnmze the DC msmatch current that wll be ntroduced by the output voltage varaton. The O P1 and O P nputs are connected at the drans of the correspondng transstors as t s shown n fgure 3, whle the opamp outputs drve the gates of transstors M3 and P1 respectvely. Vdd P P3 Ibas P1 + - Op1 PS1 PS M1 M3 Out + - Op3 MS1 MS Op + - M M4 M5 Fg. 3. Improved Charge Pump Crcut 3.1 Characterstcs of the Improved Charge Pump Approach In the mproved crcut transstors M1, M, M3 and M4 compose a cascode current mrror wth ncreased output resstance and mnmzed channel length modulaton.

5 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons 47 F Fdv PFD L L Fg. 4. Buffer chan between PFD and CP Ths cascode connecton offers the advantage of low voltage operaton for the charge pump. The bas current (Ibas) from the nput branch s mrrored to the output branch where P3 and M5 act as current sources. The current source mrrorng rato s 4, whch means that the output current s four tmes larger than Ibas. MS1 and PS1 are the transstor swtches whch are drven by the and sgnals from the PFD. When the sgnal s low, the PS1 swtch s turned on and the current Iup from P3 charges the loop flter capactor, ncreasng the output voltage. On the other hand when the sgnal s hgh, the MS1 swtch s turned on and the output voltage s decreased by the dschargng current Idn that flows through M5. Transstors MS and PS are the swtches whch are drven by the complementary and sgnals, provdng a constant current flow path when the swtches MS1 and PS1 are off. Ths mples a fast swtchng operaton at the expense of ncreased power consumpton. When the loop s locked, both swtches are on for a small fracton of the tme. At lock both MS1 and PS1 have to swtch on and off smultaneously to reduce the nose ntroduced n the loop and the magntude of the f and consequent spurs. For ths reason a buffer wth a tmng synchronzaton scheme whch consttutes from two chans s used; the frst chan s used to generate the sgnal and the second to generate the sgnal. Ths buffer placed between PFD and CP, as shown n fgure 4. The scalng rato for the nverters s chosen to be close to 4 [19], n order to acheve the best power, speed and area trade-off. Also the channel length L, of the nmos and pmos transstor n the frst nverter of the sgnal s ncreased to equalze the delay between the two tmng control sgnals ntroduced by the asymmetry of the two chans [7]. Synchronzaton can also be acheved by usng the two paths of the chan, where the frst one ncludes an extra nverter compared to the second one and ntroduce an actve resstor (a transmsson gate adequately dmensoned) n the second path. In addton to that the dmensons of the swtches must be properly szed, n order to turn on and off smultaneously. An mportant advantage of the mproved CP crcut s the low DC msmatch between the pump up and pump down currents. The two opamps O P1 and O P are used n order to mnmze ths DC offset current. As t s shown n fgure 3, the two nputs of O P1 and O P are connected to the drans of P-P3 and M4-M5 transstors respectvely, formng a closed loop. If the output voltage ncreases to lock at a hgher frequency, then the voltage at the dran of M5 ncreases as well. Because of the O P the same voltage s forced on the dran of M4. Lkewse O P1 forces the voltage to the drans of P and P3 to be almost the same. As a result, the same amount of current flows between the two branches, for a wde output voltage dynamc range.

6 48 V. Kalenterds, K. Papathanasou, and S. Sskos The dmensons W/L of the current source transstors that s M5 and P3 are chosen n such a way to mnmze the current mrrorng msmatch from the nput to the output branch. Also the systematc current varaton due to any resdual n the V DS despte the presence of the opamps has been remeded by choosng large gate lengths for the current source transstors. In addton the PS1 and MS1 transstor swtches, whch operate n the lnear regon, have been desgned wth mnmum gate length, n order to acheve maxmum output voltage range. Moreover the unty gan amplfer O P3 plays an mportant role, snce t sets the voltage at the dran of the swtches PS1 and MS1 at the output node. Thus the charge sharng effect becomes mnmal when the swtches turned on. It also ncreases the swtchng-speed of the charge pump due to current constant flow from P3 to M5, even when the PLL s locked. Hence the charge and dscharge of the parastc capactances at the dran node of P3 and M5 s avoded. Ths ncreases swtchng speed, theore the dead zone and the resultant nose contrbuton s reduced durng the lock condton at the expense of a small current consumpton ntroduced by O P3, snce t only needs to source or snk a small P and N msmatch current. Fnally a compensaton capactance has been added at the output of the amplfer, to ncrease the phase margn, as denoted by an assocated stablty analyss. Moreover t acts as a charge reservor durng swtchng transtons. 3. Comparson to Alternatve Approaches The sgnfcant mprovement compared to smlar, alternatve charge pump mplementatons [16, 17] s n essence due to the fact that the output of the opamps drves the gates of the cascode transstors and not the gates of the current source transstors drectly. In the mproved approach P1 s connected as a source follower, resultng to a sgnfcant reducton of the O P1 nose contrbuton at the charge pump output. Vdd P P3 Op1 + - Ibas P1 Vb1 PS1 PS M1 Vb M3 Out + - Op3 MS1 MS M M4 + - Op M5 Fg. 5. Opamp drves drectly the gates of P and P3

7 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons 49 For example n the case where the O P1 drves drectly the gates of P3 and P transstors, as shown n fgure 5, the nose current * out1 generated at the output of P3 s gven by the followng equaton: out1 = gm P3 (1) n where Vn represents the output erred voltage nose of the opamp O P1 (both flcker and thermal) and gm s the transconductance of the current snkng transstor. From the above equaton t can be seen that the nose current s the product of the nose voltage and the transconductance of P3. In our case, as shown n fgure 3, the output of O p1 s connected to the gate of P1 nstead of P3. Takng nto account that P acts as a current source wth a fnte large output resstance r o, the nose current of P s equal to: * n o V n = () r Ths current produces a nose voltage at the gate of P equal to n * n P v = gm Thus the nose current that appears to the output of P3 s gven by the equaton: (3) out = gm P3 v n = gm gm P3 P r * n o (4) Theore the rato of the mproved charge-pump over the one n [16] s gven by the equaton: out out1 1 gm P r = (5) For example f common modern transstor values r o =7kΩ and g m =.84mS are subsdzed n the above equaton, a sgnfcant reducton by 45dB, of the Op1 nduced nose at the output s obtaned. 3.3 Analyss and Estmaton of Nose Contrbutors of the Improved Charge Pump The analytcal estmaton of the nose contrbuton, from the charge pump transstors s presented n ths secton. As t s well known the flcker (1/f) and thermal (whte) nose from the actve devces are the domnant nose sources that affect the overall nose performance of the charge pump. The nose plot of an actve devce (MOS or Bpolar transstor) s shown n fgure 6, whch has only two dstnctve regons; thermal nose and 1/f regon. The 1/f nose corner s n the vcnty of 500kHz to 1MHz o

8 50 V. Kalenterds, K. Papathanasou, and S. Sskos for a sub-mcron CMOS technology and t s n the vcnty of 1kHz to 10kHz for bpolar transstor [1]. There are three dfferent combnatons for the charge pump swtchng condtons whch are gven n the followng table: Table 1. Sgnals MS1 PS1 (low), (hgh) On On (low), (low) Off On (hgh), (hgh) On Off 0logV n 1/f Flcker nose Thermal Nose f 1/f f Fg. 6. Nose characterstcs of a MOS transstor at a fxed bas voltage 1. PS1 on and MS1 on The frst condton s when the two transstor swtches are both on for a small fracton of tme correspondng to the locked condton of the loop. For the flcker nose estmaton a nose voltage source s placed at the approprate gate devce and the resultant nose current s calculated at the output of the transstor. So n ths condton the transstors that affect the total nose of the charge pump are: M, M4, M5, P, P3. g mn and gmp are the transconductances for nmos and pmos transstors respectvely, where ndex ndcates the number of the correspondng transstor. For the nose calculaton the flcker nose s easly modeled as an equvalent voltage source V n n seres wth the gate of a MOS transstor and roughly gven by the followng equaton V n C ox K f 1 W L f = (6)

9 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons 51 where K f s a process-dependent constant on the order of 10-5 V F, C ox s the oxde capactance, W and L are the wdth and length of the transstor respectvely. The nverse dependence of (7) on W, L suggests that to decrease 1/f nose, the devce area must be ncreased. Takng nto account that W M =W M4, W P =4 W M4 and W P3 =4 W P =16 W M the total output nose current s gven by the followng expresson: n, out = g = = g mp3 n4 + g mp3 np3 + g mp3 np + g mn5 mp3 n4 + gmp3 np3 + gmp3 np + gmn5 n n + n + n + n n, out = 5 16 n n5 = = (7) * n where s the output fered nose current of transstor M. It should be noted that the frst two terms whch are the summaton of the nose current from M transstor are cancelled by the thrd term; the negatve sgn of ths thrd term comes from the fact that the two nose currents g V and mn5 n g are fully mp3 n correlated wth a phase dfference of 180 degrees to each other (for the actual CP swtchng frequences). Ths s because the P3 transstor sources current whle M5 transstor snks the same nose current. Moreover these transstors have equal transconductances, snce the rato of ther mobltes s equal to the rato of the dmensons W/L for the same current.. PS1 Off and MS1 On In the second condton only M and M5 transstors are taken nto account snce they affect the charge pump nose and the total output nose current s gven by the followng expresson: * n, out gmn n + gmn5 n5 = n + n = n = (8) The dode connected M produces a nose current whch s mrrored at the output of the charge pump. M5 acts as a current snk producng also a nose current whch s four tmes smaller than the nose current of M, because ts wdth s four tmes larger than the wdth of M, as depcted n (7). 3. PS1 On and MS1 Off In the last operatng condton the output nose current conssts of the nose currents of the M, M4, P and P3 transstors. M5 does not contrbute any nose at the output because the MS1 swtch s n the off state. Takng nto account that W M =W M4, W P =4 W M4 and W P3 =4 W P =16 W M the total output nose current s gven by the followng expresson: * n

10 5 V. Kalenterds, K. Papathanasou, and S. Sskos n, out = g mn * n + g mn4 n4 + g * mp = n + n + n + n = np n + g mp3 np3 Comparng the results from the three dfferent operatng condtons, a sgnfcant concluson s obtaned. In the frst case, though both the swtches MS1 and PS1 are on, the crcut does not exhbt hgher nose. Ths s because the nose current generated by the M transstor s fully correlated n both the pmos and nmos branch and theore cancelled at the output of the charge pump. The most nosy operaton state s the last one where the PS1 swtch s on and the MS1 swtch s off. In the thrd secton of the chapter these nose calculatons wll be confrmed by the assocated smulaton results. 3.4 Spectral Components of the Charge Pump Output Sgnal In ths secton an attempt to calculate the spectral components of the output sgnal Iout, as a functon of the phase error Δθ, between f and f dv, s presented. In the followng analyss t s assumed that the output of the charge pump conssts of current pulses of ampltude I cp. It s also assumed that there s no msmatch between the current sources (M5, P3) of fgure 3. The duty cycle of the output pulse s equal to τ/t, where τ s the actve tme of the charge pump output current and T s the perod of the erence sgnal. From the sgnal processng theory [0] t s known that the Fourer seres expanson for a perodc tran of pulses of ampltude I cp and duraton τ s: I out ( t) Icpτ Icpτ + T T sn( nπτ / T ) πnt cos( ) T n= 1 nπτ / T = (10) The equaton (11) can be expressed as a functon of the phase error Δθ, takng nto account that the rato τ/t s proportonal to Δθ/π: I out ( t) IcpΔθ IcpΔθ + π π Δθ sn( nπ ) π πnt cos( ) Δθ nπ T π n= 1 = (11) If the duty cycle δ cp equals to τ/t and for small values of the δ cp, the snc functon sn(nπτ/t )/(nπτ/τ ) can be approxmated as unty. Ths results n the followng expresson for I out : I out ( t) = I cp cp n= 1 = (9) δ + I δ cos(πnf t) (1) cp cp whch shows that the ampltude of the spectral components of I out are twce as large as ts dc value I cp δ cp. Theore, f δ cp =Δθ/π equals to zero the charge pump output deally contans no dc or ac sgnal components. The next step s to study the effect of msmatch n current sources. Msmatch orgnates n the dfferent type of devces used to mplement the n-type current snk, whch snks current from the output node to ground and the p-type current source

11 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons 53 whch sources current from the supply to the output node. Moreover the nomnal current suppled by the n-type and p-type current sources s lkely to be a functon of the voltage at the output node of the charge pump. Ths s fltered by the loop flter producng the tunng voltage V tune to the oscllator, and theore t s a functon of the output frequency of the entre loop. If V msmatch (n f ) s the magntude of the rpple voltage at the fundamental and harmoncs of the erence frequency, then the equaton whch relates the above voltage wth the current-source msmatch s gven below: V msmatch where Z( j π ) nf ( n f ) = I out ( n f ) Z ( jπnf ) (13) s the magntude of the transmpedance functon of the loop flter and n rangng from 1 to. It s common to express the magntude of the undesred sgnal components wth respect to the magntude of the carrer frequency f LO. From the standard modulaton theory [0] the relatonshp of the peak phase devaton θ p (f m ) to the peak frequency devaton Δf(f m ) and the modulaton frequency f m s gven by ( f Δf ( f ) = ) m θ p m (14) fm The peak frequency devaton s the product of the magntude of the spectral components of the msmatch voltage V msmatch (n f ) wth the gan K VCO (V/Hz) of the VCO: f ( fm ) = Vmsmatch( n f ) KVCO Δ (15) Combnng (14) and (16) and substtutng nto (15) we get the peak phase devaton due to each of the spurous frequency components n f θ n f p I ) = out ( n f ) Z( jπnf ) n f K ( (16) Each of the baseband modulaton frequences n f generates two RF spurous sgnals, whch are located at offset frequences ± n f from the carrer frequency f LO. The ampltude of each spurous sgnal A sp s related to the magntude of the carrer A LO and to the peak phase devaton θ p by A sp ( f LO ± n f ) = A LO ϑ p ( n f ) Substtutng (17) nto the numerator of (18) the followng expresson n db s obtaned A sp VCO ( f ± n f ) Iout( n f ) Z( jπnf ) LO A LO dbc = 0 log n f K VCO [ dbc] An mportant concluson that can be drawn from (19) s that the relatve ampltude of the spurous sgnals s ndependent on the absolute value of loop bandwdth or on the (17) (18)

12 54 V. Kalenterds, K. Papathanasou, and S. Sskos nomnal charge-pump current I cp. Instead, they are determned by the transmpedance of the loop flter, by the magntude of the erence spurous components, by the VCO gan and by the value of the erence frequency. 3.5 Nose Performance of Charge Pump An deal CP-PLL wth zero phase error nether sources current to, nor snks current from, the loop flter. However, PLLs wth zero phase error are nsenstve to small loop-phase devatons due to fnte rse tmes n the PFD and charge pump whch s also called the dead zone. A commonly employed soluton to dead-zone s to use an artfcal phase offset so that CP pumps/snk current when PLL s locked. When the PLL s locked the average output current flowng nto the flter s zero. Both the currents from the P3 and M transstors n fgure 3, are on for the duraton of the dead zone pulse. Even though the average current s zero, nose s njected from both transstors currents for the duraton of the dead zone pulse. The charge pump nose current njected to the loop flter under lock condton can be calculated as, δ T cp n, out = I n, CP (19) I, where constant factor s used to account for the source and snk current pulses. n CP s the nose current of the CP n A /Hz. δ CP s the dead zone pulse wdth and T s the erence perod sgnal. The above equaton suggests that f the erence frequency s ncreased then more nose wll be njected nto the loop flter and n consequence to the VCO crcut block. Moreover the PLL close-n phase nose wll ncrease wth the erence frequency by a factor proportonal to 10 log (f ). Also a dead zone pulse wth large duraton leads to an ncreased nose as depcted by equaton (0). 4 Smulaton Results The mproved charge pump was desgned usng 0.18um CMOS technology. The supply voltage was.5volt for the charge pump and nverters n the buffer chan. Smulatons were obtaned by usng Cadence desgn framework wth spectre devce models from UMC 0.18um and 0.35um devces. The pump up and pump down currents are 1mA from a.4v power supply. The CP desgn ncludes a programmable gan by a step of 50uA. Corner and temperature analyss has also been performed, n order to further the demonstrablty, applcablty and robustness of the mproved crcut. The percentage of DC msmatch current over output voltage of the mproved CP, for three dfferent process and temperature worst cases (typcal 0 7 o C, slow o C, fast o C) as shown n fgure 7. The crcut s able to operate wth a msmatch current less than.5% at the typcal case and.5% at the extreme process/temperature condtons. The output voltage ranges from 300mV to.v. Beyond these lmts, transstors close to the supply rals (P3, M5), leave the saturaton and enter to the lnear regon of operaton, whch results to an ncreased msmatch current. The power consumpton of the mproved charge pump ncludng the three opamp consumpton s roughly 6.65mW for a.4 power supply voltage.

13 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons 55 Fg. 7. The dc msmatch of the output current vs output voltage A perodc nose analyss (Pnose) has also been performed n order to obtan the nose contrbuton of the devces at the output of the charge pump. Fgure 8 llustrates the nose power spectral densty of the output current, when the loop s locked, whch means that the transstors are on for a small fracton of tme that s equal to the reset delay of the PFD. Ths tme delay s 500ps, whch results n a duty cycle of 0.5%. Because of the fast swtchng characterstcs of the mproved charge-pump even smaller duty cycles can be used, further reducng the close n nose contrbuton of the charge pump by as much as 6dB! Due to the delay added n the reset path of the PFD, the current sources (P3, M5) are on for small or zero phase errors. The dumped charge on the capactor of the loop flter as a functon of the phase error s llustrated n fgure 9. The X axs represents the phase error n tme. A maxmum 180 degrees phase devaton corresponds to 50ns. In addton to that a second perodc nose analyss has been performed to confrm the valdty of equaton (0). The three plots n fgure 10 represent the power spectral densty of the charge pump nose current for three dfferent duty cycles. As t can be observed, ncreased duty cycle leads to an ncreased nose to the charge pump output. To verfy the theoretcal nose analyss and hghlght the actve nose contrbutors of the charge pump, an ac nose smulaton has been done for the crcut. Three dfferent cases have been smulated for typcal model transstor and room temperature (7C) and the results are gven n the followng tables. At the frst column s gven the correspondng nose contrbutor transstor and at the second column s the smulated current nose at a specfc spot frequency (f=1hz for ths case).

14 56 V. Kalenterds, K. Papathanasou, and S. Sskos Table. PS1 on MS1 on Nose Contrbutors Nose Current (A /Hz) M4.3e-16 M5 5.8e-17 P 3.15e-17 P3 7.95e-18 Table 3. PS1 off MS1 on Nose Contrbutors Nose Current (A /Hz) M 1.875e-16 M5 5.61e-17 Table 4. PS1 on MS1 off Nose Contrbutors Nose Current (A /Hz) M4 8.4e-16 M5.3e-16 P 5.5e-17 P e-18 Fg. 8. Nose power spectral densty from Pnose analyss

15 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons 57 Fg. 9. Dumped charge as a functon of phase error Fg. 10. PSD of CP Current Nose for three dfferent Duty Cycle

16 58 V. Kalenterds, K. Papathanasou, and S. Sskos The most sgnfcant nose contrbutors have been obtaned for each case n consstency wth the theoretcal analyss, whch s gven n the prevous secton. It s worthy to note that M n table does not produce any nose contrbuton, due to the correlaton of the current nose components whch cancel each other at the output. Moreover nmos transstors contrbute hgher amount of nose current than pmos transstor due to ther hgher moblty. 5 Conclusons The desgn and analyss of a low nose charge pump has been presented n ths chapter. Low nose charge pumps are essental to modern telecommuncaton systems, because they domnate the close-n nose of the assocated syntheszer. In modern GSM, CDMA or OFDM standards the nose of the PLL s defned by the n-band nose, snce the VCO nose can be reduced by smply openng the loop bandwdth to ht the VCO phase nose characterstc n a more attenuated level at a hgher frequency whch s especally true nowadays wth the evoluton of the fractonal-n syntheszers. Theore the low-nose propertes of the charge pump are becomng ncreasngly more essental. The mproved charge-pump (fgure 3) performs better than older alternatves, because t uses the current steerng technque to swtch on and off, theore mnmzes delays. Furthermore the ntroducton of O P3 at fgure 3 ensures that all nodes are precharged to ther fnal levels, and theore less tme s needed for the crcut to settle, furtherng the ntal speed mprovement. Fast swtchng speed n essence demands a smaller dead-zone tme and thus mnmzes the nose contrbuton of the charge pump at lock (and non-lock) condton. Inherent nose of the charge-pump s reduced by addng the stablzng opamp crcuts n an mproved fashon compared to other alternatves [16, 17, 18]. By addng ths novel feedback approach t s possble though to mprove on output matchng, wthout ncreasng nose. The mproved charge-pump accuracy over the full output range, expressed by an excellent P/N msmatch, ensures that there s a lmted systematc DC offset and theore the spurous content s smaller, thus makng t easer to meet the modern f spurous content specfcatons, whch are steadly decreasng n sze. In table 5 alternatve advanced CP famles are compared, to provde a good percepton of the mprovement ntroduced by the crcuts presented n the current chapter. Table 5. CP verson Swtchng Speed Nose Performance DC msmatch Cheng et al. Very Good Good Good Rapnoja et al. Medum Good Good Chang et al. Good Medum Good Ths approach Very Good Very Good Very Good

17 Analyss and Desgn of Charge Pumps for Telecommuncaton Applcatons 59 References [1] Parker, J.F., Ray, D.: A 1.6-GHz CMOS PLL wth on-chp loop flter. IEEE Journal of Sold State Crcuts 33(3), (1998) [] Crannckx, J., Steyaert, M.S.J.: A fully ntegrated CMOS DCS-1800 frequency syntheszer. IEEE Journal of Sold-State Crcuts 33(1), (1998) [3] Rhee, W.: Desgn of hgh-performance CMOS charge pumps n phase-locked loops. In: IEEE Internatonal Symposum on Crcuts and Systems (ISCAS), vol., pp (1999) [4] Rategh, H.R., Samavat, H., Lee, T.H.: A CMOS frequency syntheszer wth an njectonlocked frequency dvder for a 5-GHz wreless LAN recever. IEEE Journal of Sold-State Crcuts 35(5), (000) [5] Rhee, W., Song, B.S., Al, A.: A 1.1-GHz CMOS fractonal-n frequency syntheszer wth a 3-b thrd-order ΔΣ modulator. IEEE Journal of Sold-State Crcuts 35(10), (000) [6] Hungand, C.-M., Kenneth, K.O.: A fully ntegrated GHz CMOS phase-locked loop. IEEE Journal of Sold-State Crcuts 37(4), (00) [7] De Muerand, B., Steyaert, M.S.J.: A CMOS monolthc δσ-controlled fractonal-n frequency syntheszer for DCS IEEE Journal of Sold-State Crcuts 37(7), (00) [8] Loke, A.L.S., Barnes, R.K., Wee, T.T., Oshma, M.M., Moore, C.E., Kennedy, R.R., Glsdorf, M.J.: A versatle 90-nm CMOS charge-pump PLL for SerDes transmtter clockng. IEEE Journal of Sold-State Crcuts 41(8), (006) [9] Perrott, M.H., Trott, M.D., Sodn, C.G.: A modelng approach for sgma-delta fractonal- N frequency syntheszers allowng straghtforward nose analyss. IEEE Journal of Sold- State Crcuts 37(8), (00) [10] Shu, K., Sanchez-Snenco, E., Slva-Martnez, J., Embab, S.H.K.: A.4-GHz monolthc fractonal-n frequency syntheszer wth robust phase-swtchng prescaler and loop capactance multpler. IEEE Journal of Sold-State Crcuts 38(6), (003) [11] Arora, H., Klemmer, N., Morzo, J.C., Wolf, P.D.: Enhanced phase nose modelng of fractonal-n frequency syntheszers. IEEE Transactons on Crcuts and Systems I: Regular Papers 5(), (005) [1] Huh, H., Koo, Y., Lee, K.-Y., Ok, Y., Lee, S., Kwon, D., Lee, J., Park, J., Lee, K., Jeong, D.K., Km, W.: Comparson frequency doublng and charge pump matchng technques for dual-band delta sgma fractonal-n frequency syntheszer. IEEE Journal of Sold-State Crcuts 40(11), 8 36 (005) [13] Woo, K., Lu, Y., Nam, E., Ham, D.: Fast-lock hybrd PLL combnng fractonal-n and nteger-n modes of dfferng bandwdths. IEEE Journal of Sold-State Crcuts 43, (008) [14] Mtomo, T., Fujmoto, R., Ono, N., Tachbana, R., Hoshno, H., Yoshhara, Y., Tsutsum, Y., Seto, I.: A 60-GHz CMOS recever front-end wth frequency syntheszer. IEEE Journal of Sold-State Crcuts 43, (008) [15] Fahmand, A.M., Elmasry, M.I.: A low-power CMOS frequency syntheszer desgn methodology for wreless applcatons. In: The Internatonal Symposum on Crcuts and Systems (ISCAS), vol., pp (1999) [16] Cheng, S., Tong, H., Slva Martnez, J., Karslayan, A.I.: Desgn and analyss of an ultra hgh-speed gltch-free fully dfferental charge pump wth mnmum output current varaton and accurate matchng. IEEE Transactons on Crcuts and Systems II: Express Brefs 53, (006)

18 60 V. Kalenterds, K. Papathanasou, and S. Sskos [17] Rapnoja, T., Stadus, K., Halonen, K.: A low-power phase-locked loop for uwb applcatons. Analog Integrated Crcuts and Sgnal Processng 54, (007) [18] Chang, R.C., Kuo, L.-C.: A new low-voltage charge pump crcut for PLL. In: The Internatonal Symposum on Crcuts and Systems (ISCAS), vol. 5, pp (000) [19] Rabaey, B.N.J.M., Chandrakasan, A.: Dgtal Integrated Crcuts, A Desgn Perspectve, nd edn. Prentce Hall, Englewood Clffs (00) [0] Taub, H., Schllng, D.L.: Prncples of Communcaton Systems, nd edn. McGraw-Hll, New York (1986) [1] Jones, D.A., Martn, K.: Analog Integrated Crcut Desgn, 1st edn. Wley, Chchester (1996) [] Hanumolu, P.K., Brownlee, M., Mayaram, K., Moon, U.-K.: Analyss of Charge Pump Phase Locked Loops. IEEE Transactons on Crcuts and Systems I: Regular Papers 51(9), (004) [3] LMX330A, Natonal Datasheet [4] Johnson, M., Hudson, E.: A varable delay lne PLL for CPU-coprocessor synchronzaton. IEEE Journal of Sold-State Crcuts 3(10), (1988) [5] Young, I.A., Greason, J.K., Wong, K.L.: A PLL Clock Generator wth 5 to 110MHz of Lock Range for Mcroprocessors. IEEE Journal of Sold-State Crcuts 7(11), (199) [6] Maneats, J.: Low-Jtter and Process-Independent DLL and PLL Based on Self-Based Technques, ISSCC Dgest of Techncal Papers (1996) [7] Soyuer, M., Ewen, J.F., Chuang, H.L.: A Fully Monolthc 1.5GHz CMOS Frequency Syntheszer. In: Symposum on VLSI Crcuts, Dgest of Techncal Papers, vol. 6, pp (1994) [8] Razav, B.: Monolthc Phase-Locked Loops and Clock Recovery Crcuts, pp IEEE Press, Los Alamtos (1996)

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