THE UCC3884 FREQUENCY FOLDBACK PULSE WIDTH MODULATOR

Transcription

1 U-64 Phlp Cooke THE UCC3884 FREQUENCY FOLDBACK PULSE WIDTH MODULATOR

2 UNITRODE CORPORATION APPLICATION NOTE U-64 The UCC3884 Frequency Foldback Pulse Wdth Modulator by Phlp Cooke ABSTRACT Ths applcaton note focuses on the UCC3884 frequency foldback peak current mode controller. The UCC3884 provdes a soluton to the current tal problem often seen n hgh frequency converters under overload fault condtons. Intended prmarly for sngle-ended converters, other features such as a maxmum duty-cycle clamp and an accurate volt-second clamp are also ncluded. The block dagram and the man features of the UCC3884 wll be presented n the theory of operaton secton. Followng that a dervaton of the oscllator, frequency foldback, and volt-second clamp equatons are gven. Fnally, desgn detals and test results for an example RCD clamp forward converter operatng at 400kHz are shown. INTRODUCTION The output VI characterstc of hgh frequency, buck-derved, peak current mode converters can exhbt a current tal durng current overload condtons. Ths overload may be caused by a short crcut condton or a low mpedance at the power stage output. The current tal s actually a gradual ncrease n the average output current as the average output voltage decreases toward zero. The peak current lmt n a PWM controller commands the power stage swtch off durng overcurrent condtons whch should lmt the maxmum average output current. However, the propagaton delay nherent n the controller and n the power swtch durng turn-off lmts the mnmum attanable duty cycle []. Ths mnmum duty cycle lmt can produce a current tal durng overloads. Upon close nspecton one fnds that ths propagaton delay exsts collectvely between the current sense (CS pn) and the output (OUT pn) of the ntegrated crcut (IC) and the turn-off delay of the power stage swtch. The reducton of the propagaton delays for a gven IC and power stage desgn can help, but tends to ncrease system cost. An alternate method s needed to reduce the delays and thus the excessve currents durng a fault. One possble technque s mplemented n the oscllator secton of the UCC3884. Durng a fault condton as the output voltage approaches zero the operatng frequency also decreases. By reducng the frequency durng overload condtons the dutycycle s permtted to decrease below the value prevously lmted by propagaton delay n the constant frequency converter. The UCC3884 reduces the frequency smoothly as the load mpedance approaches a short crcut, thus preventng possble latch-up wth nonlnear loads []. Ths effectvely dmnshes the current tal n the output VI characterstc. The UCC3884 s ntended for hgh performance, peak current mode, sngle-ended applcatons that can beneft from frequency foldback. Ths frequency reducton only operates when the output voltage s below a user programmable value. More specfcally, the oscllator runs at constant frequency and only folds back when the output voltage drops below a gven value (e.g., 4.2V for a 5V output). A volt-second clamp crcut s also ncluded that allows accurate duty-cycle clampng under transent lne and load condtons provdng an extra level of crcut protecton from transformer saturaton. For example, f a sudden ncrease n load power occurs whle the nput voltage ncreases, the appled volt-seconds could be enough to saturate the transformer, whch could cause the power swtch to fal. In ths case, the volt-second clamp crcut could be used to prevent the falure of the power swtch by overrdng the control loop and lmtng the appled volt-seconds. Ths controller also features a depleton-mode n-channel MOSFET gate drve ntended to be used n the bas supply durng start up. A reducton n both the sze of the start up storage capactor and turn-on tme can be acheved by usng an external depleton-mode devce.

3 U-64 Fgure. UCC3884 Block Dagram THEORY OF OPERATION The UCC3884 current mode controller, shown n Fgure, contans a programmable oscllator secton whch ncludes the ablty to synchronze multply PWMs. The postve and negatve sloped portons of the oscllator waveform (measured at CT, the connecton pont for the tmng capactor) have tme ntervals that are set by external resstors at ION and IOFF as shown n Fgure 2. The nomnal operatng frequency s determned by the tmng capactor durng non-frequency foldback condtons, that s, wth the output voltage at ts regulated value. The postve sloped porton of the oscllator waveform has a fxed tme duraton and s set by a resstor connected to ION. In a smlar fashon the off-tme s set by a resstor at IOFF. However, the negatve sloped porton of the oscllator waveform s extended n tme as the measured output voltage decreases provdng protecton durng output faults. When the voltage at VOUT decreases below 3.5V, due to an output short crcut, the operatng perod ncreases and the IC s n frequency foldback operaton. It should be emphaszed that normal converter operaton, except durng start up, s at a fxed frequency. The power supply output voltage and the voltage from VREF can be fed back nto VOUT wth summng resstors. Ths ensures a mnmum frequency at startup and durng short crcut condtons when the output voltage s zero. Fgure 3 shows computer smulated VI curves for a 47kHz forward converter, one wth frequency foldback and one wthout frequency foldback. The total propagaton delay was set to 50ns n ths computer model of a forward converter wth 48V nput (8:2 turns rato). Power stage component values were L =.3µH wth a DCR of 0.0Ω and C = 0000µF wth an ESR of 70mΩ []. It can be seen that the current tal s reduced wth frequency foldback. Fgure 4 further detals the effect of the propagaton delay. Two smulatons were done at the same operatng frequency both wthout frequency foldback. The smulaton wth the current tal approachng 22A had a 50ns delay and the other 2

4 U-64 Fgure 2. Functonal Block Dagram of the UCC3884 Oscllator had an unrealstc, nearly zero,.0ns delay. It s clear that the propagaton delay can cause sgnfcant overcurrents and frequency foldback s a practcal way to reduce the current tal effect. Another feature ncluded n the UCC3884 s an nterface to drve an external depleton-mode MOSFET durng power supply startup untl the bootstrap wndng exceeds a 0V threshold. At whch tme the depleton-mode MOSFET s turnedoff. The nternal amplfer controllng ths MOSFET has 300mV of hysteress to avod oscllaton durng power-up. An accurate programmable volt-second method to clamp the duty-cycle s mplemented. It s confgured so that the duty-cycle lmt s nversely proportonal to nput voltage and a resstor dvder network s used to program the proportonalty constant. At a gven nput voltage and constant load, assumng regulaton, the operatng duty-cycle s a fxed value. The volt-second clamp duty-cycle may then be set somewhat hgher than ths operatng duty-cycle. Snce the volt-second duty-cycle lmt s nversely proportonal to V IN at any other constant nput voltage level, the volt-second clamp wll stll exceed 6 6 Average Output Voltage Non-Frequency Foldback Case Frequency Foldback Case Average Output Voltage Propagaton Delay = 50ns Propagaton Delay =.0ns Average Output Current Fgure 3. Frequency and Non-Frequency Foldback Comparson Average Output Current Fgure 4. Non-Frequency Foldback wth.0ns and 50ns Propagaton Delays 3

5 the steady state operatng duty-cycle as shown n Fgure 5. Ths allows normal current-programmed closed-loop operaton of the converter wthout the volt-second duty-cycle lmt nterferng wth the control. For example, durng a load transent and possbly an nput voltage transent the volt-second clamp can accurately lmt the maxmum appled volt-seconds by lmtng the duty-cycle. Ths ensures that the transformer does not saturate durng a fault whch could otherwse fal the power supply. After the fault passes the converter wll go back nto regulaton. Fgure 5. Varous Duty Cycles An external capactor may be connected to CSS whch provdes for a soft-start and also allows the IC to be dsabled wth an external transstor. The frequency foldback and the soft-start functons wll both be n effect durng power-up snce the output voltage fed back to the VOUT pn s less than 3.5V and the voltage on CSS s less than 4V. The ncreasng on-tme at the OUT pn durng soft-start s controlled by C SS and the perod s controlled by the frequency foldback crcutry. When an overload or short crcut occurs the frequency foldback crcut and possbly the volt-second clamp crcut s actvated (assumng the overcurrent s not trggered). In each desgn the steady state VI characterstc produced by the frequency foldback crcut should be compared to the load VI curve to be certan that the converter wll start under load. The current sense feedback pn has an over current protecton feature whch forces a soft-start cycle only f the IC s not currently n a soft-start cycle. A voltage bas of.0v s added to the voltage sensed on the CS pn n order to facltate zero duty-cycle when the error amplfer s output s less than.0v. The PWM latch s reset domnant so that f the error amplfer output s below.0v the output of the latch s not drven hgh. The error amplfer s unty gan stable and has a wde gan-bandwdth product for accuracy. Its non-nvertng nput s nternally set to 2.5V. U-64 DETAILED DESCRIPTION AND DESIGN EQUATIONS A descrpton of the UCC3884 BCMOS pulse wdth modulator and desgn equatons wll be presented followed by an example RCD Clamped Forward Converter desgn usng the UCC3884 peak current mode controller [2,3,4]. Oscllator and Frequency Foldback Secton: The oscllator secton has an ndependently programmable frequency and a maxmum duty-cycle clamp. A sngle resstor sets the tmng capactor (CT) charge current whch creates the postve slope porton of the oscllator waveform. A second resstor sets the tmng capactor dscharge tme. Wth reference to Fgure 2 the oscllator waveform ncreases lnearly from.5v to 3.5V and decreases lnearly back to.5v completng one cycle. If T OSCon represents the charge tme and T OSCoff s the dscharge tme then the frequency of the converter s gven by f =. () T OSCon + T OSCoff The output of the modulator can only be asserted durng the postve slope porton of the oscllator waveform. Wth ths lmtaton the maxmum duty-cycle s gven by the rato of T OSCon to T OSCon + T OSCoff ; T OSCon D MAX =. (2) T OSCon + T OSCoff The oscllator off-tme s a functon of the man output voltage only f the VOUT pn drops below 3.5V. The VOUT pn may exceed 3.5V n whch case the off-tme s calculated usng 3.5V. Note that the IC does not nternally clamp ths voltage to 3.5V. If the output s short crcuted or a low mpedance load s appled the feedback voltage to the VOUT pn decreases whch causes T OSCoff to ncrease. Ths wll ncrease the perod and therefore decrease the frequency. Recall that the oscllator on-tme (T OSCon ) s constant and does not vary wth output voltage. Under nomnal operatng condtons the frequency s constant and equaton can be expanded to f = = (3) C T (3.5.5) + C T (3.5.5) 8.8 I ON 8.8 I OFF 4.4 I ON C T ( + ) C T ( R ON R + OFF ) I OFF = 4

6 where C T s the tmng capactor, R ON sets the value of the C T chargng current, (8.8 I ON ), and R OFF sets the value of the C T dschargng current, (8.8 I OFF ). The maxmum current sourced from the ION and IOFF pns s lmted to approxmately 800µA. To avod start up problems, a resstor can be added from VREF to VOUT whch provdes a voltage bas to VOUT even when the output voltage s zero. The choce of value also sets the mnmum operatng frequency durng frequency foldback, as wll be revewed n the example desgn secton below. Desgns usng an solaton transformer can derve a dc voltage level proportonal to the output by usng a peak detector crcut off of the bootstrap wndng of the power transformer (Fgure 8). Ths bas supply s normally requred for solated converters and therefore requres only a mnmum of components. Fgure 6 shows the oscllator and frequency foldback portons of the UCC3884, where V X s found by assumng no lmtng acton wthn the VOUT pn (see also Fgure 2). V X s gven as R OUT R OUT2 V X = V REF + (4) R OUT R OUT2 + R OUT3 R OUT R OUT3 R OUT R OUT3 + R OUT2 V O U-64 Synchronzaton of Multple ICs: A CLKSYNC pn s provded whch s used to synchronze two or more UCC3884 ICs. Multple ICs are synchronzed n frequency by connectng ther CLKSYNC pns wth capactors to the CLKSYNC bus as shown n Fgure 7. Each free runnng oscllator s desgned wth the same base frequency and the same maxmum duty-cycle and s connected to the CLKSYNC bus wth a capactor and a pull-down resstor. A negatve edged pulse from any IC wll ntalze all the ICs to start the upslope of ther oscllator waveforms. For a gven oscllator on the down-slope, f t receves a negatve synchronzaton pulse before t reaches the.5v threshold, an nternal MOS swtch wll quckly dscharge ts C T down to.5v. After soft-start synchronzaton for each controller may take one or two cycles to come nto lock. Durng frequency foldback under an output fault condton, the synchronzaton n the overloaded IC s nhbted and the converters can become unlocked. Ths s necessary snce the overloaded ICs frequency s n foldback. The oscllators wll resynchronze when the fault s removed. Due to tolerances, each free runnng oscllator frequency may be slghtly dfferent; therefore the CLKSYNC bus synchronzes to the hghest frequency. For multple PWM converters, synchronzaton to other controllers s only possble when the VOUT pn s greater than 3V. where V REF = 5V, V O s the output voltage, and represents parallel resstors. If equaton 4 yelds a V X greater than 3.5V t would then be replaced wth 3.5V. One possble desgn approach would be to gnore the loadng of R OUT3 and set V X slghtly below the output voltage mnus one-half of the maxmum rpple voltage. Wth R OUT and R OUT2 known, set V O = 0 and R OUT3 may be calculated based upon the mnmum operatng frequency desred. Fgure 7. Oscllator Synchronzaton Connecton Dagram Fgure 6. Oscllator and Frequency Foldback Connectons to the UCC3884 Volt-Second Clamp: The volt-second duty-cycle clamp operates by takng the recprocal of the voltage on VVS (see Fgure ) whch s drectly proportonal to the nput voltage and uses ths sgnal to lmt the duty-cycle. As V IN ncreases, to mantan constant operatng volt-seconds for a forward converter, the duty-cycle 5

7 decreases based upon V O + V D D OP = ; (5) (V IN V DSon )... N S N P where D OP s the operatng duty-cycle, V DSon s the on-state dran-to-source prmary swtch voltage, N S s the secondary turns, N P s the prmary turns, and V D s the voltage drop of the secondary rectfer dode [5]. In a smlar fashon, the maxmum duty-cycle clamp due to ths voltsecond functon wll also decrease and s gven by K T D VS = OSCon (6) V VS T OSCon + T OSCoff =. D MAX V VS U-64 where D VS s the duty-cycle clamp based upon appled volt-seconds to the transformer, V VS s the voltage on the VVS pn, and K was calculated from Fgure 8. RCD Clamp Forward Converter wth Frequency Foldback 6

8 the UCC3884 data sheet. The volt-second clamp s set by an external resstor dvder network from the nput voltage to the VVS pn. Normally, D VS s chosen to exceed D OP by some fxed percentage, say 0%. It may be necessary to put a small ceramc capactor at the VVS pn to flter swtchng nose. Ths feature allows for an accurate volt-second clamp wthn the nput voltage range under load transent condtons. It s accurate snce the tmng capactor tolerance does not effect equaton 6. The voltage at VVS can be provded by % resstors and the nternal accuracy s mantaned to 3% (for the 0 C to 70 C temperature range). To lmt the on-tme at the mnmum nput voltage the maxmum possble duty-cycle s clamped by D MAX. The converters actual duty-cycle can be lmted by ether the volt-second clamp or the maxmum programmable duty-cycle clamp dependng on operatng condtons. Soft-Start Operaton: A constant current source ISS, set nternally to 20µA, charges C SS to a clamped voltage level of typcally 5.0V. The soft-start tme s gven by 3.5 C SS /I SS. Durng start up the PWM comparator selects the mnmum of ether the error amplfer output or the soft-start capactor voltage. The output duty-cycle s therefore slowly ncreased as the voltage at CSS ncreases. At some pont the error amplfer voltage s lower and the voltage loop s closed. An overcurrent fault wll ntate a soft-start cycle by frst dschargng C SS and then slowly rechargng the capactor untl the voltage returns to 4V. Soft-start dscharge can only be actvated when the voltage at C SS exceeds about 4V. Under Voltage Lockout Features: The converter s dsabled untl VREF exceeds 4.6V and VDD exceeds 9.V. Once these levels are reached the converter wll begn the soft-start sequence. If VREF falls below 4.4V or VDD decreases below 8.8V the converter wll mmedately dscharge C SS and then start up agan when VREF exceeds 4.6V and VDD exceeds 9.V. DESIGN EXAMPLE A forward converter wth an RCD clamp and a maxmum of 75% duty-cycle at 400kHz was desgned as shown n Fgure 8 [,2,3,4,6]. The nput voltage range s 35V to 72Vdc wth a 5V output. The hghest operatng duty-cycle s set to about 65% and wll occur at the mnmum nput voltage durng normal condtons. A maxmum duty-cycle lmt ensures reset of the transformer at low lne. Power Crcut Desgn: A hgh frequency forward converter topology s often used n telecommuncatons applcatons requrng battery nput from 35V to 72V DC wth 48V nomnal. A common output voltage s 5V and n ths desgn a large capactor, 0000µF, wll be used to smooth the low frequency rpple components n order to more accurately measure average load currents durng overload condtons. The output nductor was selected to be.3µh wth a coupled wndng for the bootstrap crcut (5:2 turns rato). The transformer prmary to secondary turns rato s 8:2 and a RCD clamp s used to reset the transformer durng the swtch off-tme. The laboratory prototype was bult usng hgher rated components than necessary (maxmum of 78W). Ths was done snce constant measurement of short crcut fault currents wthout frequency foldback could cause excessve power dsspaton. Oscllator Desgn: The oscllator on-tme can be found, assumng D MAX and f s known, by solvng T OSCon D MAX = (7) T OSCon + T OSCoff = T OSCon f for T OSCon yeldng D MAX C T (3.5.5) T OSCon = = (8) f 8.8 I ON C T =. 4.4 I ON From equaton, T OSCoff becomes U-64 T OSCoff = T OSCon (9) f The oscllator operatng frequency s gven by f =. (0) C T Solvng for C T yelds C T =. () f Wth T OSCon and C T known, I ON may be found from equaton 8 C I ON = T. (2) 4.4 T OSCon 7

9 Now R ON s gven by.5 R ON =. (3) I ON The next step s to calculate the maxmum value of I OFF whch occurs durng non-frequency foldback condtons. A porton of equaton 3, repeated below, f = (4) C T ( + I ON I OFF ) may be solved for I OFF yeldng C I OFF = T f I ON. (5) I ON C T f Fnally, the R OFF resstor value s 3.5 R OFF = (6) I OFF These equatons are used n a Mathcad spreadsheet lsted n Appendx I [7]. Frequency Foldback Desgn: The three resstors assocated wth frequency foldback may now be calculated. A useful approach s to frst gnore the loadng from the VOUT pn and gnore the R OUT3 connecton. To allow for a small decrease n the output voltage before frequency foldback kcks n (ths s not a requrement, but can be used to guarantee constant frequency operaton under the expected output voltage rpple) set V X = 4V and from Fgure 6 one can wrte R OUT V X = 4 R V O (7) OUT + R OUT2 where V O s the actual output voltage. By arbtrarly selectng R OUT, the value of R OUT2 can be determned. Now, the selecton of R OUT3 determnes the mnmum frequency of operaton. Rewrtng equaton 6 for the general case (when the VOUT pn s less than 3.5V) V X = R OFF I OFF. (8) Settng V O equal zero n equaton 4 one solves R V X = OUT R OUT2 V REF (9) R OUT R OUT2 + R OUT3 for R OUT3. Wth R OUT, R OUT2, and R OUT3 known, equaton 4 can be used n a Mathcad spreadsheet U-64 to plot operatng frequency of the converter as a functon of the output voltage. Lsted n Appendx I s an example of the spreadsheet whch ncludes the calculatons and graphs of the steady state volt-second clamp and frequency foldback characterstcs. Volt-Second Clamp Desgn: The voltage at the VVS pn s gven by R V VS = VS V IN (20) R VS + R VS2 once R VS s selected R VS2 can be solved for after D VS s chosen. From equaton 6 D V VS = K MAX (2) D VS as an example D VS may be set to 0% of D OP. For ths case, after solvng for R VS2 n equaton 20 wth V VS replaced usng equaton 2, one fnds D R VS2 = R VS (V IN OP ). (22) D MAX Control Loop Component Calculatons: The concentraton of ths applcaton note s to show the characterstcs of the frequency foldback and volt-second clamp features of the UCC3884. Detals of the small-sgnal modelng of the modulator and power crcut can be found n [8] and [9]. Integral compensaton was used to set the crossover frequency to 9kHz wth a gan of about 7dB needed at ths frequency. EXPERIMENTAL RESULTS The RCD clamp forward converter was prototyped n the laboratory and relevant results are presented n the followng secton. Frequency Foldback Data: The prmary current sense resstor n Fgure 8 was ncreased to 32Ω from 6Ω (6Ω was used n the computer model that generated Fgures 3 and 4) n order to lmt the average load currents to reasonable values for easy measurement. The prevous smulaton results showed the basc phenomena of the current tal wth and wthout frequency foldback. Due to effects not ncluded n the computer model the expermental data dffers from the smulated data. The computer model s a powerful tool to gan a fundamental understandng of the large sgnal VI characterstcs as shown n Fgures 3 and 4. It may be possble to take nto account gnored complcatons so that the smulated results match 8

10 U-64 more closely the expermental data. It s thought that some of these effects could be the saturaton of the magnetcs (output nductor), errors n estmatng the fnte turn-off tme of the MOSFET power stage swtch and possble saturaton of the prmary current sense transformer. Despte these measurement naccuraces the frequency foldback operaton does reduce the current tal as compared to non-frequency foldback operaton and ths can be seen n the smulaton results and the actual crcut measurement data. Fgure 9 shows normal operaton at constant frequency wth about a 4A average load current. The top waveform s the output voltage (5V, channel 3) followed by the oscllator waveform measured at Fgure 9. Converter Output Voltage, Oscllator Waveform, Prmary Sde Current Durng Normal Operaton, and MOSFET Gate Voltage Fgure 0. Converter Output Voltage, Oscllator Waveform, Prmary Sde Current Durng a Low Impedance Load Fault, and MOSFET Gate Voltage 9

11 pn 0 (CT, channel ). Note that for small values of CT the scope probe capactance on pn 0 can decrease the frequency. The thrd from the top s the prmary sde current at A/dv (channel 4). Note that there s a 470pF capactor n parallel wth the MOSFET prmary swtch to reduce clamp loss [2]. The bottom trace s the gate voltage at pn 8 (OUT, channel 2) whch drves an IRF630 through a 3Ω resstor. A low mpedance load was appled and the resultng converter waveforms are shown n Fgure 0 wth the same scales as used n Fgure 9 except the output voltage scale was decreased and the prmary current scale on the AM503B was ncreased from A/dv to 2A/dv (channel 4). The average load current was 7.4A and the frequency was reduced from 403kHz to 267kHz. The output voltage decreased from 5.06V to 0.880V. U-64 A toggle swtch was used to change from frequency foldback to non-frequency foldback operaton. Ths allowed drect comparson between frequency foldback and non-frequency foldback operaton as the load resstance decreased. Fgure shows the data taken under the same condtons wth and wthout frequency foldback. It was found that a fan was helpful n keepng the sense resstors cool n order to avod drft durng current measurement. The shape of the curves n Fgure dffer from Fgure 3, obvously the computer model has not taken nto account all of the parastc and saturaton effects. The value of R OUT3 calculated n Appendx I was ncreased to 33.k to generate the frequency foldback curve shown n Fgure. The actual measured frequency versus output voltage s shown n Fgure 2. 6 Average Output Voltage Wth Frequency Foldback Wthout Frequency Foldback Average Output Current Fgure. VI Characterstcs wth and wthout Frequency Foldback Frequency (khz) Voltage (V) Fgure 2. Measured Frequency versus Measured Output Voltage 0

12 SUMMARY The UCC3884 peak current mode controller provdes the desgner a frequency foldback scheme to reduce the current tal often seen n hgh frequency buck derved converters. A possble practcal desgn approach n the prototype crcut s to set the mnmum frequency to about /3 of the nomnal frequency and to use the smplfed analyss outlned above to gve frst pass crcut values for the frequency foldback resstors R OUT, R OUT2, and R OUT3. Durng testng of the power converter low mpedance loads can be appled for fnal adjustment of the frequency foldback resstors and to verfy desred operaton. The maxmum duty-cycle clamp and volt-second clamp may be used to enhance performance and relablty of the power converter system. The undervoltage lockout, clock synchronzaton, depleton-mode MOSFET drver, and soft-start functons are all provded to complete a feature rch peak current mode controller wthn a 6 pn DIL package. REFERENCES: [] Phlp Cooke, Analyss of a Voltage Controlled Frequency Foldback Technque that Improves Short Crcut Protecton for Buck Derved Converters, Intelec, October 996, page [2] Leu, Hua, Lee, and Zhou, Analyss and Desgn of RCD Clamp Forward Converter, VPEC, Vrgna Tech and Delta Power Electroncs Lab, Blacksburg, VA. U-64 [3] Bll Andreycak, Actve Clamp and Reset Technque Enhances Forward Converter Performance, Untrode Semnar SEM-000, page 3-. [4] Clemente, Pelly, Ruttonsha, A Unversal 00kHz Power Supply Usng a Sngle HEXFET, Internatonal Rectfer Applcaton Note 939A. [5] Abraham I. Pressman, Swtchng Power Supply Desgn, McGraw-Hll, Inc. 99. [6] Larry Hayes, Warren Schultz, Optosolators for Swtchng Power Supples, Motorola Optoelectroncs Devce Data Book, DL8/D REV 4. [7] Mathcad User s Gude, Mathcad PLUS 6.0, Mathsoft Inc., 995. [8] Lloyd H. Dxon, Control Loop Cookbook, Untrode Power Supply Desgn Semnar, SEM-00, 996. [9] Rdley, Raymond B, A New Small Sgnal Model For Current Mode Control, Dssertaton, November 27, 990, VPEC, Blacksburg, VA. ACKNOWLEDGMENTS: The author acknowledges and apprecates the assstance of Pentt Nemnen and Gosta Baarman of Noka Telecommuncatons durng the defnton of ths ntegrated crcut.

13 Appendx I: Oscllator and Volt-Second Calculatons Hgh Performance UCC3884 PWM wth Frequency Foldback and Volt-Second Clamp Mathcad desgn worksheet. by Phlp Cooke Specfcatons: Input Votage Outputvoltage Operatng frequency 35V<Vn<72V 5V dc 400 khz f Estmated operatng frequency (for non-frequency foldback condtons). D_max 0.75 Maxmum duty-cycle. N 8 2 Prmary transformer turns rato. Vt 3.5 Peak oscllator voltage. Vb.5 Mnmum oscllator voltage. Vd 0.5 Estmated voltage drop on secondaryforward dode. Kon 8.8 Ion multpler to charge Ct. Koff 8.8 Ioff multpler to dscharge Ct. K. Volt-second constant. Vds_on 0.5 Approxmate voltage drop of prmary swtch. Vout 5 Output dc voltage. Vref 5 Output of on-board UCC3884 regulator. Vn_mn 35 Mnmum nputvoltage. Vn_max 72 Maxmum nput voltage. Oscllator Calculatons: Calculate the tmng capactor from the frequency: Ct f whch gves Ct = select Ct Recalculate operatng frequency, f Ct so that f =

14 The oscllator on tme s gven by equaton 8 Tosc_on D_max f Tosc_on = Now from equaton 2, calculate Ion Ion Ct. 4.4 Tosc_on so that Ron Vb Ion Ron = Ioff s found from equaton 5 Ioff Ct. f. Ion Ion Ct. f Ioff = Fnally, Roff s Roff Vt Ioff Roff = Checkng the Kon*Ion and Koff*Ioff values to be sure they don't exceed 800 ma: Kon. Ion = Koff. Ioff = Frequency Foldback Calculatons: Set Rout to 4.99 kw. Rout Rout Rearrangng equaton 7 to solve for Rout2: Rout2. 4 Vout Rout Rout2 = The mnmum frequency s selected tobe /3.3 ofthe nomnal frequency; now Ioff mnmum can be calculated from equaton 5: Ct. f. Ion Ioff 3.3 Ioff = Ion Ct. f 3.3 Wth Ioff equaton 8 s used to fnd the mnum value of Vx Vx. Roff Ioff Wth Vx = V Rout3 s gven by (equaton 9): Rout. Rout2 Rout3. Rout Rout2 Vref Vx Rout3 =

15 Volt-Second Calculatons: Choose 0 kw for Rvs and set D_vs =.467*D_max; Rvs Calculate the operatng duty-cycle at Vn_mn. Dop Vout Vd ( Vn_mn Vds_on ). N From equaton 22 Rvs2 Rvs.. Vn_mn Dop D_max Rvs2 = Fnal Selecton of Components: Rout Rout Ron Roff Rout Ct Rvs Rvs Recalculate Ion, Ioff, f, Tosc_on, and Tosc_off: Ion Ioff f Vb Ron Vt Roff Ct Ion = Kon. Ion = Ioff = Koff. Ioff = f = Tosc_on Ct. 4.4 Ion Tosc_on = Tosc_off f Tosc_on Tosc_off = Derve Equatons to Plot: 0,.. 00 Set up a range varable. Vn Vn_max Vn_mn Vn_mn. 00 Use as a parameter to vary Vn. 4

16 Vo. Vout 00 Vary Vo parametry wth. D_op Vn Vout Vd Vds_on. N Calculate the steady state operatng dutycycle as a functon of nput voltage. The Vx voltage s calculated assumng no clamp orload of the VOUT pn:. Rout Rout3. Rout Rout2 Vx Rout. Rout Rout3 Rout Rout3 Rout3 Rout2. Vo Rout. Rout Rout2 Rout Rout2 Rout2 Rout3. Vref Next, the 3.5V lmt s takng care of by the Mathcad condtonal f statement: Vout f Vx > 3.5, 3.5, Vx Now the Ct dscharge current, Tosc_off, and f can be found as a functon of Vout; Ioff Vout Roff Tosc_off ( Vt Vb). Ct. Koff Ioff f Tosc_on Tosc_off A temporary varable s used to calculate the voltage at the VVS pn as the nput voltage vares. Stop gaps of 0.6V and 4.5V are assumed. Vtemp Rvs Rvs Rvs2. Vn Vvs f Vtemp < 0.6, 0.6, f Vtemp > 4.5, 4.5, Vtemp Fnally, the effectve volt-second duty-cycle clamp s calculated; D_vs K. D_max Vvs 5

17 Plot Expected Results: Waveforms from top to bottom; maxmum duty cycle, volt-second clamp, and operatng duty cycle varous duty cycles D_max 0.6 D_vs 0.5 D_op Vn nput dc voltage (V) Voltage at the VOUT pn as the actual output voltage vares. 5 4 voltage at VOUT pn (V) Vout Vo output voltage (V) 6

18 Frequency foldback characterstcs: as the output voltage decreases the converters operatng frequency decreases operatng frequency (Hz) f Vo output voltage (V) 7

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