A CMOS Single Stage Fully Differential OP-Amp with 120 db DC Gain

Transcription

1 EES 413 Fall 2003 Final Poject Repot 1 MOS Sinle Stae Fully Diffeential OP-mp with 120 d D Gain Xin Jian, Sanhyun Seo and Yumin Lu EES Dept. Univesity of Michian at nn bo, MI bstact sinle stae fully diffeential 120-d op amp fo standad 0.25µm pocess is desined based on folded cascode and ain boostin technique. This desin demonstates a D ain of 120 d with a unity ain fequency of 381MHz and a phase main of 64 o. The cicuit s pefomance has been simulated with +/-10% voltae supply vaiation and 27 o -85 o tempeatue ane. Index Tems folded cascode, sinle stae, ain boost. Fi. 1. ascoded ain stae with ain enhancement I I. INTRODUTION n many analo cicuit applications such as /D convetes [1], switched capacito filtes [2] and sampleand-hold amplifies, speed and accuacy ae detemined by the settlin behavio of the op amp cicuit. The settlin speed mainly depends on the unity ain fequency and a sinle pole settlin time while hih settlin accuacy is due to hih D ain of the op-amp cicuit [3]. In ode to achieve both hih settlin speed and hih D ain, seveal cicuit appoaches such as dynamic biasin of tnsconductance amplifie [4], tiple-cascode amplifie [5], positive-feedback tansconductance amplifie [6] wee poposed, but the ain and unity ain fequency of those ain boostin techniques ae not enouh fo the ecent submicon MOS cicuit applications. In 1990, K. ult and G. Geelen poposed the folded cascode op-amps with the ain boostin technique [7], which shows a D ain of 90 d and a unity-ain fequency of 116MHz with 16pF load. The ain boostin technique is intoduced by Hosticka in 1979[8] and ult and G. Geelen fistly applied this technique to op-amp. ased on the folded cascode op-amp desin with the ain boostin technique, this pape pesents the state-of-the-at 120d D ain fully diffeential op-amp with 381MHz unity ain fequency usin IM 0.25µm MOS technoloy. The ain boostin technique is explained in section II and the cicuit s fequency behavio is analyzed in section III. In section IV, the cicuit implantation with 0.25 MOS pocess is pesented. The simulation esults ae iven and discussed in section V. II. GIN OOSTING s shown in Fiue 1, the idea of ain boostin is based on neative feedback loop to set the dain voltae of M2 [9]. Neative feedback dives the ate of M2 until V x has the same value as V ef. Theefoe, the vaiation of V out has much less effect on V X, because add eulates this voltae. This topoloy is usually called eulated cascode o active cascode. With the smalle vaiation of V X due to the chane of V out, the output cuent becomes less sensitive to the voltae vaiation at V out compaed with conventional cascode stuctue. Theefoe the output impedance inceases as shown in equation (1): R out = add m 2 o1 [ ( ] o1 + o 2 + m 2 add ) mb 2 o1 This inceased output esistance esults in seveal odes of impovements on the oveall ain as shown in equation (2): = R = (2) vtot m1 out add m1 m 2 o1 III. FREQUENY NLYSIS. Diffeential Folded ascade Op mp Fo a fully diffeential folded cascode op amp like the one shown in Fiue2, the dominant pole is the pole at output node (node ) which has the hihest impedance and in most cases, the hihest capacitance. The pole fequency 1 is iven by wp 1 =, whee R out is the op amp RoutL output impedance and L is the load capacitance [10]. (1)

2 EES 413 Fall 2003 Final Poject Repot 2 10 M1 11 M =s2 2 M2 1 M0 8 7 Opmp MP1 2 M2 M0 1 Opmp MP3 3 M3 M4 9 6 Opmp MP2 3 M3 M The second pole is at the cascade tansisto souce node (node ). The pole fequency is iven as: m2 w p2 = whee m2 is the tansconductance of the L cascade tansisto M2, and L is mainly fom the atesouce capacitance s of M2 [10]. m3 The thid pole fequency is w p3 = and thee is a zeo at Fiue 2. Fully diffeential folded cascade op amp m 3 L. The effect of this two will thus canceled out [10]. Fo the inteest of ou desined op amp, we only conside up to the second pole fequency. m0 The unity ain fequency is iven by wu =, the L size of the input tansisto M0 is thus desined accodinly to satisfy the 300 MHz unity-ain fequency specification with 2 pf load.. Reulated Folded ascade Op mp s discussed in session II, additional amplifie staes ae used to boost ain [7]. Fiue 3 shows the half cicuit of the poposed op amp. With the addition of the ain boost amp, the second pole fequency is chaned. The souce-ate capacitance of M2 now foms a Mille cap which is connected between the input and output of the additional amp. Theefoe the capacitance seen at node is not just s2 now, but (1+ ) s2 whee is the ain of the additional amp. This educes the second pole fequency w p2 and thus deades the phase main of the op amp. In ode to ovecome this effect, an exta cap is added at the output of amp. The exta cap educes the dominant pole fequency L Fiue 3. Half cicuit of the eulated folded cascade op amp of amp so that its ain dops to a much lowe value aound w p2. This educes the Mille effect and pushes up the second pole fequency. schematic of this technique is shown in Fiue 4 and the simulated bode and phase plots with and without the exta cap ae shown in Fiue 5. It is shown that without the exta cap, the second pole effect is kickin in aound 300MHz which is the unity-ain fequency of the desined op amp. y addin the exta cap (1pF in this case), the second pole is pushed up. This effect is shown moe clealy fom the phase plot. Fo stability concen, the unity ain fequency of the additional stae ( m / ladd ) has to be lae than the fist pole of the main stae (1/R out Lmain ) [7]. This can be easily achieved since R out is typically much lae than 1/ m. mplif ie MP1 mplif ie MP I_D SR1 Fiue 4: Reulated folded cascade op amp with exta capacito mplif ie MP4 mplif ie MP3

3 EES 413 Fall 2003 Final Poject Repot 3 Low-voltae cascode cuent mio 500mV 1.6 V with exta ap with exta ap ias cicuits Fiue 6. Schematic of the addition ain stae Fiue 5. old and phase plots of the amp with and without the exta cap IV. IRUIT IMPLENTTION M6 I1 I2 P. dditional ain stae The additional ain staes ae aain implemented with folded cascade op amps with sinle end output. dditional ain stae is applied to both the cascode tansisto and cuent souce of the main stae. NMOS diffeential pai is used fo amp (fo cascode tansisto) and PMOS diffeential pai is used fo amp (fo cuent souce). They ae chosen based on the common-mode D equiement. Low voltae cascode active cuent mio is used in the additional amp. This esults in a lae output D ane and only equies one bias voltae [9]. Fo example, Fiue 6 shows the schematic of the additional stae. Its maximum output voltae is set by V dd -2V DST which is aound 2V.. ommon Mode Feedback The common mode feedback is achieved by contollin the biasin cuent fo the folded cascode in the main stae. s shown in Fiue 7, uent I1 and I2 add up and o thouh the cuent souce M5. If V cm, out ets hihe, cuent I1 inceases and thus cuent I2 educes. This lowes the voltae of node P and as the esult, the I ds of tansisto M6, which is the biasin cuent fo the cascode amp (main stae), inceases. This inceasin biasin cuent will lowe down the V cm, out. The minimum common mode input is detemined by V dd - V GS - V DST which is about 0.9V. So the common mode input ane is 0.9V-2.5V. This cicuit implementation also allows fo the output swin of 0.5-2V. This is basically detemined by the two V DST consumed by M1, M2 and M3, M4 (Fiue 2). The dominant pole feq is about 200 Hz and the unity ain fequency of 300 MHz with 2pF diffeential load. Main Stae V. SIMULTION RESULTS M5 MF Fiue7. Schematic of the main stae with common mode feedback ased on the desin pocedue descibed in the pevious sections, a sinle stae 120-d fully diffeential op amp was desined based on IM 0.25µm MOS pocess and simulated usin adence Desin Systems. s shown in Fiue 8, the entie cicuit s chip size is mm 2, which includes the 5 µm wide powe supply slab and ound slab. In this layout, besides the powe supply and ound, only one efeence cuent souce ae needed to povide pope biasin fo the cicuit. The two 1-pf capacitos wee ealized usin metal-insulato-metal confiuation between layes of Metal 2 and Metal 3. Fo the est pat of the cicuit, only Metal 1 and Metal 2 wee used in the layout pocess. This layout has passed DR and LVS compaison. In the simulations, the extacted cicuit model based on the layout has incopoates the layout paasitic capacitances, which wee omitted in the initial schematic simulations. In ou layout, since the device s paasitic capacitances demonstate effects simila with the exta capacitos loaded to the additional staes, the simulated esults based on the extacted cicuit model fom the layout has a sliht hihe unity ain fequency compaed with that fom the schematic cicuit model. Theefoe, only the simulation esults based on the extacted model with paasitic capacitances ae shown in the followin discussions. The capacito load used in this desin at the diffeential output is 2pF.

4 EES 413 Fall 2003 Final Poject Repot 4 Nfet dditional Stae Main Folded ascode Stae MF Exta apacito Exta apacito Pfet dditional Stae Fiue. 8: Layout view of the completed op amp. s shown in Fiue. 9, when the powe supply chanes fom 2.25 V t.75v (2.5V+/-10%), the simulated D output esponses demonstate simila hih ain esponses with zeo input voltae offsets. The output voltae swin is minimum (±0.55 V) unde 2.25V powe supply, which still satisfies the desin specification of ±0.4 V. lso, unde the same powe supply vaiations, the esponses of this desin satisfy the ain ( 0 90 d), unity ain fequency (f MHz) and phase main (PM 60 o ) equiements (Fiue. 10). ecause the common mode feed back netwok stabilizes the output common mode voltae, the acceptable input common mode voltae can be as hih as 2.5 V and can be as low as 0.9 V with D and pefomance satisfyin the desied desin specifications (Fiue 11). 2.75V 2.5V 2.25V (a) ode plot (M1 maks out unity ain); 2.5V 2.75V 2.25V Fiue 9: Diffeential output D swin vesus input voltae (vin+ only) unde diffeent powe supplies. (b) Phase plot (M1 maks out PM of 60 o ); Fiue 10: esponses unde diffeent powe supply. The simulated D and esponses unde diffeent powe supply voltaes and tempeatues (25 o and 85 o ) ae listed in Table I. s shown in Table I, fo all but one opeatin conditions, ou desin meets all the specification. Only at the wost-case scenaio, (T=85 o and V dd =2.25V), the unity ain fequency dops to 156.8MHz, while the ain (94 d) is still

5 EES 413 Fall 2003 Final Poject Repot 5 (V) TLE I SIMULTED RESPONSES OF THE OP MP DESIGN UNDER DIFFERENT OPERTING ONDITIONS Output Swin (V) (Desied:1.25±0.4) D Gain (d) (Desied: 90) Unity Gain f 0 (MHz) (Desied: 300) Phase Main ( o ) (Desied: 60) 2.25(27 o ) 1.25± (27 o ) 1.25± (27 o ) 1.25± (85 o ) 1.25± (85 o ) 1.25± (85 o ) 1.25± VI. ONLUSIONS In this pape, a sinle stae fully diffeential 90-d op amp fo standad 0.25µm pocess is desined based on folded cascode and ain boostin technique. When the diffeential output capacito load is 2pf, this desin demonstates a D ain of 124 d with a unity ain fequency of 381MHz and a phase main of 64 o. The pefomance of this op amp is compaable with the state-of-at desins in moden MOS pocess. (a) ode plot (M1 maks out unity ain); KNOWLEDGEMENT The authos ae vey ateful to Pof. Micheal Flynn and M. ian lu Duveneay fo thei eat help and suestions on this poject. (b) Phase plot (M1 maks out PM of 60 o ); Fiue 11: esponses at diffeent input common mode voltae (Vincm:0.9V, 1.7V and 2.5V). hihe than the 90-d equiement. y adoptin some tempeatue compensation techniques in the bias cicuit (such as band-ap based bias cicuit), the unity ain fequency could be impoved up to 300 MHz. ased on D simulations unde nomal opeation conditions, the obtained common mode ain of this desin is 68d and the common mode ejection atio is lae than 300d. The total powe consumption is 13mW unde 2.5V powe supply. REFERENES [1] P. J.. Naus et. al., OMS Steeo 16-bit D/ convete fo diital audio, IEEE J. of Solid-State icuits, vol. S-22, No. 3, pp , June [2] F. W. Sino and W. M. Snelove, Switched capacito bandpass deltasima /D modulation at 10.7MHz, IEEE J. of Solid-State icuits, vol. 30, No. 3, pp , Mach [3] P. Mandal and V. Visvanathan, Self-iased Hih Pefomance Folded ascode MOS Op-mp, VLSI Desin Poceedins., Tenth Intenational onfeence on, 4-7 Jan [4] M.. opeland and J. M. Rabaey, Dynamic amplifie fo MOS technoloy, Electon Lett., coll. 15, pp , May [5] H. Hoaa et al,. MOS poammable self-calibatind 13-bit eihtchannel data acquisition peipheal, IEEE J. of Solid-State icuits, vol. S-22, pp , Dec [6].. Labe and P. R. Gay. positive-feedback tansconductance amplifie with application to hih-fequency, hih-q MOS switchedcapacito filtes, IEEE J. of Solid-State icuits, vol. 23, no. 6, pp , Dec [7] K. ult and G. Geelen, Fast-Settlin MOS Op mp fo S icuits with 90-d D Gain. IEEE J. of Solid-State icuits, vol. 25, pp , Dec [8]. J. Hosticka, Dynamic MOS amplifies. IEEE J. of Solid-State icuits, vol. S-14, no. 6, pp , Dec [9]. Razavi, Desin of nalo MOS Inteated icuits, New Yok: McGow-Hill, [10] S. Mallya and J. Nevin, Desin Pocedues fo a Fully Diffeential Folded-ascode MOS Opeational mplifie in IEEE Jounal of Solid-State ucuits, Vol 24, No , pp