An Ultra Low Power Segmented Digital-to-Analog Converter

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1 An Ulta Low Powe Segmented Digital-to-Analog onvete Manoj Kuma Univesity Institute of Engineeing and Technology, Mahashi Dayanand Univesity, Rohtak-4, Hayana, India. Raj Kuma Pofesso and Diecto, Mata Raj Kau Institute of Engineeing and Technology, Rewai-34, Hayana, India. Abstact An ulta low Powe Successive Appoximation egiste (SAR) Analog-to-Digital onvete (AD) is poposed. All blocks ae used fo single ended fo low powe applications, the puposed achitectue, that is a 3 bit themomete coded and 9 bit aay to fom a bit DA (Digital to Analog convete) to achieve ulta low powe pefomance. Most Significant bits (s) of themomete impove the lineaity of a binay weighted capacito aay with help of decode at high esolution. By vitue of educe glitch achitectue, Powe consumption is futhe impoved. The themomete based DA have advantageous ove simple DA such as low eos and monotonicity. This Papes pesents compaison between onventional and SAR AD with 3 bit themomete based. Using Simulation, Powe consumption fo SAR AD with Themomete based DA 39.4 µw at.8 powe supply whee as onvectional SAR consumption is 9.6 µw at.8 powe supply. Keywods: Themomete based DA; Powe consumption INTRODUTION In Today ea, SAR AD offeed sophisticated platfom fo Bio-medical applications because of high esolution and medium speed. SAR AD is impotant pat of Bio Implanted Devices. Due to thei excellent powe efficiency, SAR ADs become moe and moe impotant. A SAR AD mainly consists of a compaato, a DA and SAR logic. The onvectional SAR AD is shown in fig.. The capacito matching diectly affects the effective no. of bits (ENOB) o esolution. A themomete based DA has advantages of low diffeential non lineaity (), good monotonicity and low glitches. Such appoach is mostly used in cuent steeing DA []. A fully themomete based cuent DA is pesented in []. The fully themomete based appoach is not useful fo biomedical application because of lage aea and high powe. A full diffeential themomete coded DA is pesented in this [3]. This pape shows good lineaity but it is not a powe efficient. So we pupose a single ended solution with segmented DA fo the bette tade-off between lineaity, powe consumption and decode logic implementation. A segmented DA has advantage of lineaity and low glitches. This pape compised fou sections. Section II illustates mathematical analysis of diffeent DA s achitectues. Section III discussed the icuit implementation and the SAR pefomance. Section I concludes the pape. Figue. Block Diagam of hage edistibution SAR AD MATHEMATIAL ANALYSIS ) Binay weighted apacitive DA The semantic diagam of genealised single ended full binay weighted capacitive DA is shown in fig.. Fig 3 shows semantic fo bit apacitive DA. The data acuisition pocess is achieved by cycle of thee opeations like as hold mode, sample mode and edistibution mode. Duing the sample mode pocedue, all top plates of capacitos ae fed with input voltage and bottom plates with gound. In this pocess, input voltage is sampled on the capacito aay. Duing hold pocess, switches connect the bottom plates to Figue. Single fully Binay weighted apacitive SAR AD gound theefoe a chage of IN + M is stoed on the capacito aay. Using edistibution mode, digital code can detemined checking by the status of switches and actual convesion is pefomed in this mode. Afte sampling, the total chage (Q) stoed in aay of capacito is given as: Q = IN () = 833

2 In the apacitive DA, apacito aay top plate is only attached to high input of compaato and emains detached duing sampling pocess. Duing data acuisition, Q (hage) emains unaffected. Bottom plates attached to ecognied voltages. The hage value is depend upon the position of switches and output of DA, DA and given by as ef + p Q = - DA () toef DA tognd In above Euation, the tem sum toef apacitos bottom plate attached to gound and epesents all tognd epesents all apacitos top plate attached to efeence oltage, ef. A digital contol wod b [:] ϵ {, }. If bit b[] =, than, is attached to efeence to gnd. If d[] = Than is attached to ef. So fom Euation can witten as -b p p+ + ) (3) Q = ( - ) b [] + ( ( DA ef + DA = p= The output of compaato is given as: b [] + = D A = - IN+ M+ef b [] + ( -b[p] ) p++ = + p= Denominato can be witten as because sum consist all capacito aays b [] + ( -b[p]) + = (5) = Figue 3. DA with bit hage Redistibution + p+ p= = As pe successive appoximation esults in ef DA = Theefoe, simplifies the euation 4 that esults the contol wod elationship with input voltages = IN = ef (- b [] = + ) fomula fo code (s) is witten as (s) = M (s) M (s+), (7) wheeas = ½ ef and sie of one uantiation step. The maximum eo that is known as tansition point is expected to the cente of the chaacteistic [5, 7]. p (4) (6) The eo i s g i v e n at specific point s = with the contol wod b =... = = = Above Euation (8) povides diffeence between of capacito and all othe apacitos. Due to mismatch of capacitos esults in lage eo. Due to both additive uantities, consist of diffeent unit capacito, so thee is no coection between exist tems. Due to mismatch, eo distibution can be calculated. Let assume independent nomal distibution capacitances values with a standad deviation (δ) popotional to suae of the aea occupied, then, capacitos matching values is as given Δ A σ ( ) = W.L (9) Hee A (Matching) demands on apacito type and technology. is standad deviation. Δ is identical designed apacitos and is nomalied absolute value. W and L ae geometic a paamete of capacito. Standad deviation of a one apacito is facto smalle than standad deviation of the capacito and witten as: A A WL σ () = = AWL =AA () W.L W.L The A facto is aea capacitance and technology depended. So Y-Y Q=. - () Y +Y + Y, Y and ae independent vaiables having means EY =. and Deviations ae δ Y -.δ() (8) E Y =. and Standad δ Y -.δ() and Because of non-linea distotion, the vaiable Z is not matching to a nomal distibution. Analytical solution of exact uotient is not available. By using Taylo polynomial of st Figue 5. Diffeent Block of Segmented DA with 3 bit code 834

3 ode appoach to a sufficient appoximation of standad deviation D L N () () The accuacy specification educes fom euation () 3. () < ½ (3) The achievable esolution can be computed by (4) ) Segmented DA: To ceate a segmented DA, the binay weighted capacitos ae splitted into eually sied segments. By using additional decode, segments ae elated most significant bits of segmented DA. The switches attached to theses capacitos ae contolled by decode as shown in fig.4 The Diffeent Blocks used in Segmented DA is shown in fig. 5. Themomete coded pat having bits of a bit DA consist of - eually sied segments and each ceated T = -. unit capacitos. The wok out fo calculation of input voltage and eo is simila to pevious pat. At Tansition point, the elationship fo input voltage given as (-) = T IN ef (5) = - and contol wod is given as IN (-) - + = = T (6) At switch point eo is given as T = = = T = - + (7) bin < ld. + 6 σ = ef - = = As compaed with to euation 8, above this contain identical capacitos. That means coelation educes deviation. So above becomes T (-) - = = - + = = T T (8) By using Taylo Seies, standad deviation appoximation leads to T( -) = = = T = - () (9) In the Segmented DA, the attainable esolution is given by Themo < ld. + + m-= Bin + m- 6 σ icuit ompaison: The Segmented capacitos get switched only once to efeence voltage and these capacitos ae neve switched and eplaced by othes capacitos as incease of contol wod. In onvese to implementation of full binay achitectue, the Switch point of a Segmented DA is caused by smalle mismatch of only - unit capacito but not by - unit capacito. Afte Matching of a unit capacito as pe specification of euation 3, the DA output is shown in fig.6. The Standad deviation of eo can be educed by intechanging euation and euation 6 as (,bin ) (DN L,Themo) () Theefoe, at othe majo switch points, the eo is impotant too, but less intensive. By addition of one bit in the segmented code inceases total accuacy by one bit. In othes ways, fom euation, the sie of a unit capacito can be deceased by (W.L) (W Themo.L) bin At a conseved accuacy, this atio tem allows a huge eduction of cicuit aea at few segmented bits. The segmented code does not affect the INL so eduction of aea depends upon decease of Maximum INL eo. These mathematical esults ae veified in [7]. The ompaison of and INL eo of a bit SAR AD with and without segmented code based on specte simulato 835

4 Figue 4. Semantic of Segmented apacitive SAR AD with 3 Bit ode is shown in fig.7 Thee is eduction of eo at multiple of 8 and missing no. of codes wheeas INL eo emains unchanged. sie of unit capacito is chosen as pe euation 4 and a eo below.5 as pe appoached pesented in [7]. A layout stuctue, common centoid is used in which one and half dummy columns and ows ae used. The unit capacito ae used in suae shaped. MIM capacito with slanted cones ae used fo matching puposes. The Binay weighted configuation was designed in.8µm MOS technology with 4 layes. The measued esults ae in ange and specifications i.e. eo,, aea etc. The Achievable impovements of Diffeent achitectues of DA with and without segmented codes ae shown in Table no. Table no. Figue 6. Tansient esponse of DA Figue 7. and INL of SAR AD IRUIT IMPLEMENTATION A single ended bit binay weighted SAR AD is implemented. Thee ae two cicuit vesions one is onvectional binay weighted DA and othe is single ended binay weighted with segmented coded DA as shown in fig. and fig. 5 espectively. Fo eduction of total no. of unit capacitos, a single ended capacito configuation is used. The Paamete Sie of aps in bit DA (pf) Full Binay Themomete ode bit 3 bit 4 bit Powe consumption (µw) W, L euied unit cap sie(µm) Logic gates in themo.decode The Sie of switches on the plates is scaled accoding to connected unit capacito count. Using this techniue, no exta switches ae euied fo the segmented vesion. Thee ae 7 logic cicuit used in 3 bit themomete decode cicuit. By application, themomete code of the 3 s allows downsiing the unit capacito fom 6 µm to 9.8µm in suae futhe impoving the accuacy. The capacito aay sie is educed by 5%, hence the total aea of the complete SAR AD is educed by 9% including digital contol, bias cicuity and compaato So additional powe consumed by decode is almost negligible as compaed to state machine and compaato. ONLUSION As fom analysis of diffeent achitectue of DA, the eo is caused by device mismatch which enables convectional fully binay weighted and segmented coded achitectue. To achieve the aea impovement, a bit SAR AD is demonstated. A segmented coding of few bits 836

5 impoves the eo at switch point. The segmented methods euie small change in existing cicuits, easy to implement and not bounded deep submicon technologies because of additional cicuit that is decode euies only small no. of gates. Small voltages glitches and deceased switching enegy ae advantages of this method because of small pat of capacitos is chaged and dischaged duing cycle iteation [5.] The obtained esults ae applicable to all configuations. By using exta cicuit, Powe consumption and lineaity impovement is obtained as compaed to full themomete coded cicuit. These esult ae also not only fo SAR AD but also used fo cuent steeing DA stuctues. REFERENES [].-H. Lin and K. Bult, A -b, 5-msample/s cmos dac in.6 mm, Solid-State icuits, IEEE Jounal of, vol. 33, no., pp , dec 998. [] G. Radulov, P. Quinn, P. van Beek, J. Hegt, and A. van Roemund, A binay-to-themomete decode with built-in edundancy fo impoved dac yield, in icuits and Systems, 6. ISAS 6. Poceedings. 6 IEEE Intenational Symposium on, may 6, p. 4 pp. [3] S.Haencshe and Rene Schuffny, Analysis of a hage Redistibution SAR AD with Patially Themomete oded DA, 3 IEEE Euopean onfeence on icuit Theoy and Design (ETD), Nov. 3. [4] M.Hesene, T.Eichle,, A 4b 4ms/s edundant sa adc with 48mh clock in.3pm cmos, in Solid-State icuits onfeence, 7. ISS 7. Digest of Technical Papes. IEEE Intenational, feb. 7, pp [5] K.-P. Pun, L. Sun, and B. Li, Unit capacito aay based sa adc, Micoelectonics Reliability, vol. 53, no. 3, pp , 3. [6] Y.-Z. Lin,.-. Liu, G.-Y. Huang, Y.-T. Shyu, and S.- J. hang, A 9-bit 5-ms/s.53-mw subanged sa adc in 9-nm cmos, in LSI icuits (LSI), IEEE Symposium on, june, pp [7] S. Haensche, S. Henke, and R. Schuffny, Modelling of capacito mismatch and non-lineaity effects in chage edistibution sa adcs, in Mixed Design of Integated icuits and Systems (MIXDES), Poceedings of the 7th Intenational onfeence, june 837

Chapter 9 Cascode Stages and Current Mirrors

Chapter 9 Cascode Stages and Current Mirrors Chapte 9 Cascode Stages and Cuent Mios 9. Cascode Stage 9. Cuent Mios CH 9 Cascode Stages and Cuent Mios Boosted Output Impedances S O S m out E O E m out g g Bipola Cascode Stage [ g ( )] out m O O O