Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design

Transcription

1 RESEARCH Open Access Configuable M-facto VLSI DVB-S2 LDPC decode achitectue with optimized memoy tiling design Gabiel Falcao 1,2*, Maco Gomes 1,2, Vito Silva 1,2, Leonel Sousa 3,4 and Joao Cacheia 2 Abstact Semi-paallel achitectues fo decoding Digital Video Boadcasting-Satellite 2 (DVB-S2) Low-Density Paity-Check (LDPC) codes have impoved Vey Lage Scale Integation (VLSI) solutions, but thei design is challenging fom seveal pespectives. In ode to conveniently exploit paallelism fo obtaining VLSI LDPC decodes that occupy small cicuit aeas and demand low powe consumption, we popose in this aticle a novel ASIC econfiguable appoach that exploits efficiently the memoy block eshaping euied to use a educed numbe of pocesso nodes. We exploit diffeent memoy tiling configuations to educe the memoy aea about 20%. The poposed achitectue was synthesized fo a 90 nm pocess design with a vaiable numbe of pocesso nodes and a competitive cicuit aea of 6.2 mm 2 was achieved. The opeating feuency simultaneously guaantees thoughputs supeio to 90 Mbps, as euied by DVB-S2, and low levels of powe consumption. Keywods: LDPC decoding, DVB-S2, VLSI, ASIC, memoy tiling, semi-paallel achitectue, M-factoizable achitectue, Low-powe consumption, high-thoughput 1 Intoduction Ove the last 15 yeas Low-Density Paity-Check (LDPC) codes have assumed a gowing impotance in the channel coding aena, namely because they have eo coection capability to achieve efficient coding close to the Shannon limit. These codes wee invented by Robet Gallage (MIT) in the ealy sixties [1] and have neve been fully exploited due to ovewhelming computational euiements by that time. LDPCs ae linea block codes (N,K) and can be descibed by spase binay paity-check H matices with dimensions (N -K) N. They can also be elegantly epesented by a Tanne gaph [2] defined by edges connecting two distinct types of nodes usually denoted as Bit Nodes (BN), with a BN fo each one of the N vaiables of H, and Check Nodes (CN), also called estiction o test nodes, with a CN fo each one of the (N -K) paity-check euations given by H. Natually, the fact that thei patent has expied, has shifted the attention of the scientific community and industy away fom Tubo codes [3] towads the study of LDPC codes [4], which uickly have shown to be able * Coespondence: gff@co.it.pt 1 Instituto de Telecomunicações, Pólo II - Univesidade de Coimba, Coimba, Potugal Full list of autho infomation is available at the end of the aticle of guaanteeing simila o even supeio coding pefomance. Mainly fo these easons and also because advances in micoelectonics allowed the development of hadwae solutions fo eal-time decoding, LDPC codes have been adopted by moden communication standads [5-7]. Impotant examples of these standads ae: the Digital Video Boadcasting-Satellite 2 (DVB-S2) fo satellite communications [8]; the WiMAX IEEE e fo wieless communication systems in Metopolitan aea netwoks (MAN) [9]; the WiFi n standad fo wied home netwoking technologies; and the 10 Gb Ethenet IEEE 802.3an. Also, the intoduction of LDPC codes in 4G systems has ecently been poposed, as opposed to Tubo codes adopted in 3G. Some of these applications impose challenges that typically have to be addessed by using dedicated solutions that euie System-On-Chip (SoC) hadwae poviding at the same time good pefomance, low powe consumption and small die aeas. Natually, special emphasis has been given to solutions addessing the DVB-S2 standad fo satellite communications [8], which epesents the most challenging application that actually incopoates the use of LDPC codes. In the past we have seen that paallelism can be efficiently exploited to achieve good pefomances with 2012 Falcao et al; licensee Spinge. This is an Open Access aticle distibuted unde the tems of the Ceative Commons Attibution License ( which pemits unesticted use, distibution, and epoduction in any medium, povided the oiginal wok is popely cited.

2 Page 2 of 16 iteative message-passing algoithms used in LDPC decoding [10-12]. Howeve, LDPC codes with good coding pefomances demand vey long lengths [4,13], as it is the case of those adopted in the DVB-S2 standad. The development of efficient Vey Lage Scale Integation (VLSI)-hadwae able of poviding the huge computational powe necessay and pefoming iegula memoy accesses in eal-time actually epesents a eal challenge. Focused on the oiginal achitectue developed by Kienle et al. [5] that uses M = 360 pocesso nodes, we investigated and developed efficient hadwae-dedicated DVB-S2 LDPC decodes, namely by using a educed numbe submultiple of M of lightweight node pocessos. Conseuently, we have also educed significantly the outing complexity of the inteconnection netwok between pocesso nodes and memoy blocks, which epesents a taget that aims to impove the design in tems of cost and complexity. This achitectue has been initially poposed in [14], but some impotant challenges have not been addessed yet. In this aticle we tackle these challenges, namely by mateializing the benefits and uantifying the gains achieved with the VLSI design of this achitectue, in paticula egading the complex design of Application Specific Integated Cicuit (ASIC) memoy blocks that can benefit fom the use of the educed numbe of pocessos. The poposed achitectue exploits the modulom popeties of DVB-S2 codes that allow to take advantage of patial paallelism to incease thoughput pefomance.becausewepoposeaeductionofthenumbe of pocessos used, we also addess the necessay memoy blocks eshape. Although the amount of stoed bits emains the same independently of the numbe of pocessos, we show that the memoy configuation fo a solution that uses less pocessing units is moe efficient in tems of cicuit aea. The achitectue has been pototyped using ASIC technology. Synthesis esults show that the poposed solution achieves high pefomance with low powe consumption and within a small cicuit aea context. We also pesent synthesis esults fo a memoy optimized ASIC achitectue that compae well with those epoted in state-of-the-at solutions of DVB-S2 LDPC decodes [5-7,15,16]. The main contibutions of the aticle ae: efficient, scalable and paallel achitectues with any submultiple of M =360numbe of pocessos fo VLSI-based LDPC decodes unde the context of DVB-S2; (ii) optimized synthesis aea esults fo diffeent sets of functional units and coesponding memoy blocks econfiguation; (iii) achitectue with educed outing complexity, occupying small die aeas and consuming low powe; and (iv) decodes with high thoughput. This aticle is oganized as follows. In the next section we descibe stuctued DVB-S2 LDPC codes. In Section 3 we pesent an oveview of the state-of-the-at and also the main challenges egading the development of efficient VLSI LDPC decodes fo DVB-S2. Section 4 addesses the M-factoizable paallel appoach poposed, and in Section 5 we descibe an optimized RAM memoy design pocedue fo ASIC. Section 6 pesents expeimental esults fo the poposed LDPC decode achitectue synthesized fo ASIC and compaes its pefomance with othe achitectues in the liteatue. Section 7 concludes the aticle. 2 LDPC codes Gaphical models, and in paticula Tanne gaphs [13], have often been poposed to pefom appoximate infeence calculations [17,18]. They ae based on iteative intensive message-passing algoithms [19] also known as Belief Popagation (BP) that pefom the computation of joint pobabilities on gaphs (as depicted in Figue 1) and ae commonly used in infomation theoy (e.g., channel coding), atificial intelligence and compute vision (e.g., steeo vision) [17], which, unde cetain cicumstances, can become computationally pohibitive. 2.1 LDPC decoding InthisaticleweaeinteestedintheBPalgoithm applied to LDPC decoding. In paticula, we exploit the Min-Sum Algoithm (MSA), an efficient simplification [13] of the Sum-Poduct Algoithm (SPA), which is vey demanding fom a computational pespective. The MSA hee applied to LDPC decoding opeates ove Log-likelihood Ratios (LLR) [1], exchanging infomation and updating messages between neighbo nodes ove successive iteations. Fom a computational pespective, this simplification deceases the complexity of pocessing because it uses sum opeations instead of multiplications, while subtactions eplace divisions [13,20]. Although this epesents a lowe wokload than the one euied by the SPA, it is still uite significant. If the numbe of nodes is lage in the ode of thousands as in the case of DVB-S2 the MSA can still demand vey intensive pocessing [13,19]. But if fom a computational pespective it makes sense to use the MSA, in [15,21] it is shown that by using the conventional MSA algoithm, it is not possible to achieve acceptable Bit Eo Rate (BER) pefomance fo the paticula case of DVB-S2. The utilization of this algoithm puts pefomance fa away fom BER specifications defined fo the standad [8], as it is clealy shownbyfigue7in[15].inodetoobtainberpefomances close to those defined by the DVB-S2 standad, we adopted the impoved nomalized MSA algoithm [22,23] with two distinct nomalization factos that depend on the pocessed messages at the output of the CNs. Although in [23] this poblem is only analyzed

3 Page 3 of 16 Diection of pocessing (t) BN 7 BN 7 BN 7 BN 7 BN 6 CN 3 BN 6 CN 3 BN 6 62 CN 3 26 BN 6 BN 5 BN 4 CN 2 zoom aea BN 5 BN CN BN 5 BN 4 32 CN 2 23 BN 5 BN 4 BN 3 BN 2 BN CN 1 CN BN 3 BN 2 BN 1 31 CN 1 CN 0 13 BN 3 BN 2 BN 1 02 CN 2 CN 0 20 BN 3 BN 2 BN 1 BN 0 Check Node 0 updating Bit Nodes 0, 1 and 2 BN 0 Check Node 1 updating Bit Nodes 3, 4 and 5 BN 0 zoomed aea Check Node 2 updating Bit Nodes 0, 3 and 6 BN 4 BN 0 Edge 2 41 BN 3 Edge 1 CN Edge BN 5 Figue 1 Tanne gaph epesentation and coesponding message passing used in belief popagation. fo shot length codes, in [22] it is successfully extended to DVB-S2 LDPC codes. This fact, associated with the coesponding and elatively simple changes necessaily intoduced in the design of the achitectue, is the main eason why we adopted the l - min = 1 solution [24], which computes LLR messages based on two minimums. The SPA can also be pefomed in the logaithmic domain as descibed in [20]. In the next euations, Lp n designates the apioillr of BN n, deived fom the values eceived fom the channel, and L mn is the message that is sent fom CN m to BN n, computed based on all eceived messages fom BNs of goup N (m)\n, whee N (m)\n epesents BNs connected to CN m excluding BN n, accoding to: L mn = with L n m, (1) n N(m)\n a b =sign(a) sign (b) min( a, b ) + f (a, b) (2) and f (a, b) =log(1+e a+b ) log(1+e a b ). (3) In the paticula case of the MSA f(a, b) =0.This epesents an oveestimation of LLR calculated values, which can be compensated by using the impoved nomalized MSA algoithm [22,23] with two nomalization factos (this was the solution adopted in ou achitectue). Conseuently, (1) becomes: ( L mn = α L n m n N(m)\n ), (4) whee a can be obtained by: { α1 if Lmn == fist minimum α = α2 if L mn == second minimum. (5) Also, L nm is the LLR of BN n,whichissenttocn m and calculated based on message Lp n eceived fom the channel and fom CNs of M(n)\m,wheeM(n)\m epesents the set of CNs connected to BN n excluding

4 Page 4 of 16 CN m, and is given by: L nm = Lp n + m M(n)\m L m n. At the end of each iteation we compute the aposteioi LLRs of BNs, LQ n = Lp n + L m n (7) m M(n) and pefom had decoding to obtain the decoded output wod ĉ [13,19] { 0 LQn > 0 ĉ n = 1 LQ n < 0. (8) Befoe the fist iteation occus, fo each node pai (BN n,cn m ), we initialize L nm with the LLR infomation Lp n eceived fom the channel, and then we poceed to the iteative body of the algoithm until stop conditions occu: Hĉ T 0 o the maximum numbe of iteations is eached DVB-S2 LDPC codes Following the ecognition of thei potential, LDPC codes have been ecently adopted by DVB-S2 [8] and othe new standads fo communication and stoage applications. They use thei poweful coding gains, obtained at the expense of computational powe, to achieve good pefomances unde advese channel conditions. Some of the LDPC codes adopted in those standads have a peiodic natue, which allows exploiting suitable epesentations of data stuctues fo educing the computational euiements. These modulo-m popeties of DVB-S2 LDPC codes ae descibed next, in ode to allow undestanding how achitectues can take advantage of them, namely fo exploiting paallelism. The Fowad Eo-coecting (FEC) system of the ecent DVB-S2 standad [8] incopoates a special class of LDPC codes based on Iegula Repeat Accumulate (IRA) codes [25]. The paity-check matix H is of the fom: H (N K) N = [ ] A (N K) K B (N K) (N K) = a 0,0 a 0,K 1 a 1,0 a 1,K = (9) , 0.. a N K 2,0... a N K 2,K 1. a N K 1,0... a N K 1,K (6) whee A is spase and has modulo-m popeties, and B is a staicase lowe tiangula matix. The stuctued constaints put on the pseudo-andom geneation of matix A allow a significant eduction on the stoage euiements without significant code pefomance loss. The N bits of a codewod ae epesented in the systematic fom, divided in infomation bits (IN) and paity-check bits (PN) given by the numbe of columns of A and B, espectively. The constuction techniue used to geneate the A matix consists of splitting the IN nodes into disjoint goups of M=360 consecutive 1 s. All the IN nodes of a goup l should have the same weight w l and it is only necessay to choose the CN nodes that connect to the fist IN of the goup, in ode to specify the CN nodes that connect to each one of the emaining (M -1) IN nodes of that goup. The connection choice fo the fist elements of goup l is pseudoandom but it guaantees that, in the esulting LDPC code, all the CN nodes must connect to the same numbe of IN nodes. Denoting by 1, 2,..., wl the indices of the CN nodes that connect to the fist IN of goup l, the indices of the CN nodes that connect to IN i,with0 i M-1, of goup l can be obtained by: ( 1 + i ) mod (N K), ( 2 + i ) mod (N K),...,( wl + i ) mod (N K), (10) with = (N K)/M. (11) The paamete M=360 is constant fo all codes used in the DVB-S2 standad. Fo each code, the fist goups of IN that fom A have constant weights w b >3, and the emaining goups have weights w b = 3. Matix B has a lowe tiangle staicase pofile as shown in (9). The LDPC codes adopted by the DVB-S2 standad suppot two diffeent fame lengths, one fo shot fames (N = 16, 200 bit) and the othe fo nomal fames (N =64, 800 bit). The shot fame mode suppots ten distinct code ates as depicted in Table 1, while the latte suppots 11 ates as shown in Table 2. The column and ow weights ae also depicted in Tables 1 and 2 fo all ates in the standad. Fo shot fame lengths, only 50% of the codes have constant weight w c as indicated in Table 1, while fo nomal fame length codes all CNs have a constant weight w c, as indicated in Table 2. Both tables show the numbe of edges fo each code adopted in the DVB-S2 standad. In each edge ciculate messages (L mn and L nm ) that ae used to update the connected nodes. A close inspection, fo example, of code with ate = 3/5 fo nomal fames, shows that the total numbe of edges of the Tanne gaph is Given that communications occu in both diections (fom CNs to BNs, and then fom BNs to CNs),

5 Page 5 of 16 Table 1 Popeties of shot fame length DVB-S2 codes Rate Codewod bits (N) Inf. bits (K) Col. weight (w b ) Row weight (w c ) Numbe of edges 1/ {3, 12} {4}* / {3, 12} {5} / {3, 12} {6} / {3, 8} {6}* / {3, 12} {11} / {3, 13} {10} / {3, 12} {12}* / {3} {14}* / {3, 13} {19}* / {3, 4} {27} Popeties of LDPC codes (the five shot fame codes maked with the symbol * don t have a constant weight pe ow w c, since they have been shotened has defined in the standad [8]. Conseuently, they have ates which ae an appoximation to those mentioned in this table, but not exactly the same.) used in the DVB-S2 standad [8] fo the shot fame length >2 19 messages ae exchanged pe iteation, which imposes significant computational demands (at seveal levels) fo the development of LDPC decodes. 3 Oveview of VLSI LDPC decoding achitectues The two types of nodes (BN and CN) in the Tanne gaph euie distinct pocessing. Theefoe, pocesso nodes of LDPC decoding achitectues must be capable of pefoming these two types of calculations in ode to compute the impoved nomalized MSA. Also, it is necessay to incopoate memoy to stoe messages associated with each pocesso node, and the decode euies an efficient switching mechanism to allow each pocesso node in the gaph to access diffeent memoy banks. Ideally, this should be pefomed in paallel to incease thoughput. The message-passing scheduling mechanism contols the ode in which messages ae updated (i.e., the ode how memoy is addessed by each node pocesso), defining which nodes communicate with each othe and in what ode. A contol logic unit, dependent on scheduling, contols the inteconnection netwok that pefoms this task. It connects existing BN (usually a facto of N) with CN (usually a facto of (N -K)) pocessos to the coesponding memoy blocks, in ode to allow ead/wite opeations (to be pefomed in paallel) into diffeent blocks that stoe subsections of the gaph. The inteconnection netwok should be designed to allow conflict-fee accesses to memoy banks. 3.1 Paallel LDPC decode achitectues The complex natue of such a VLSI achitectue pesents seveal challenges. To pefom fast LDPC decoding, it euies a cetain level of paallelism, which should have some significance in ode to achieve a thoughput that can be vey demanding (90 Mbps in the DVB-S2 case [8]). Above some level of paallelism the euiements fo outing, aea and powe consumption may be difficult to achieve fo pactical easons. Pesently, thee ae LDPC decode achitectues anging fom seial [26] to fully paallel [10], tageting diffeent objectives. Seial decodes tade thoughput with achitectual simplicity, obtaining educed die aeas. Although limitations at the pocessing level can make Table 2 Popeties of nomal fame length DVB-S2 codes Rate Codewod bits (N) Inf. bits (K) Col. weight (w b ) Row weight (w c ) Numbe of edges 1/ {3, 12} {4} / {3, 12} {5} / {3, 12} {6} / {3, 8} {7} / {3, 12} {11} / {3, 13} {10} / {3, 12} {14} / {3, 11} {18} / {3, 13} {22} / {3, 4} {27} / {3, 4} {30} Popeties of LDPC codes used in the DVB-S2 standad [8] fo the nomal fame length

6 Page 6 of 16 them taget mainly low-thoughput applications, they can exploit hadwae simplifications, such as educing the stoage size of messages and still achieve coding gains without noticeable loss in pefomance [26]. Paallel appoaches offe supeio thoughput at the expense of achitectual complexity and cicuit aea. On a fully paallel system, the complexity inceases significantly as the code length gows. The dimension and complexity of this type of achitectues ae only acceptable fo shot to medium length LDPC codes. One of the fist LDPC decode on ASIC [10] is based on a fully paallel achitectue fo a 1, 024 bit, ate = 1/2 LDPC decode pocessing 64 iteations, that obtains a thoughput of 1 Gbps. The excellent pefomance achieved is only possible due to the complex outing established to connect all N BN pocessos with coesponding (N -K)CN pocessos. Conseuently, the complex wiing of the cicuit ceated the need to caefully manage the floo planning and outing of the design, which aleted fo the pohibitive complexity involved in the design of achitectues that suppot block codes with high lengths (N >1,024 bit). Natually, the size of the achitectue is influenced by the length of the lagest code suppoted and also by the level of paallelism adopted. This has diect implications in the numbe of node pocessos necessay to pefom computation and, moe impotantly, in the complexity of the inteconnection netwok (epesented by a bael shifte in Figue 2). The complexity of this netwok deceases by educing the level of paallelism of the achitectue. Fo a fixed code, pemutation pattens ae known apioiand the indices/addesses that indicate which nodes connect with each othe ae usually computed offline. Compaed with full-paallel decodes, the complexity of an inteconnection netwok in a patialpaallel achitectue significantly deceases, which eliminates impotant estictions fom the outing pocess (in the place & oute phase of the design). Patial-paallel achitectues fo high-thoughput LDPC decoding have been poposed by Mansou et al. [11,12], whee the concept of achitectue-awae LDPC codes was fistly intoduced. Achitectue-awae codes decouple the achitectual dependence of the decode fom the LDPC code popeties. They achieve a faste convegence ate, which allows obtaining highe thoughputs [12]. In this case, the inteconnection netwok can be efficiently implemented by using pogammable multi-stage netwoks [11]. A compaison between seial, patly-paallel and full-paallel achitectues has been pefomed by Fanucci et al. in [27] fo a egula code with N =2,048bits,w c =6andw b =3.Howeve, these achitectues ae dedicated to paticula cases and othe solutions wee necessay to suppot othe types of moe demanding LDPC codes, namely those that have iegula natue and highe block lengths. Fo long length LDPC codes (e.g., DVB-S2 codes), typically moe than 70% of the cicuit s aeainvlsi decodes is occupied by memoy units [6,15], which ae essential to suppot the iteative message-passing mechanism. They ae extensively addessed in the context of this aticle. Memoy euiements fo paallel achitectues capable of suppoting long length codes ae feasible, but had to achieve fo pactical easons on a VLSI appoach. The numbe of accesses and the amount of memoy necessay to stoe messages exchanged between hundeds o thousands of nodes is extemely high, which imposes estictions in die aea and powe consumption. Although in a patial-paallel ROM ROM x w c x w c A0 A1 A 1 A 2 A3 A4 A 4 A5 A 357 A 358 A358 A359 x w c mem. positions ADDRESSES Addess Calculato SHIFTS x w c A2 A5 A 359 Contol: 0 - IN mode 1 - CN mode 1 0 Seuential Counte FU0 FU1 FUP-1 Shaed Contol Contol BARREL SHIFTER Shift Calculato Figue 2 Poposed M-factoizable achitectue.

7 Page 7 of 16 appoach the total amount of memoy necessay to stoe messages emains unchanged fo any numbe of pocessos, by vaying the latte, the height and width of memoy blocks change, which can be exploited to achieve achitectues with moe efficient aeas. 3.2 Paallel M-kenel LDPC decode achitectues fo DVB- S2 The development of LDPC decodes fo the DVB-S2 standad can be consideed to be among the most demanding applications fo this type of pocessing, mainly due to the high length of codes adopted [8]. LDPC codes used in this standad ae IRA codes, whee the spase paity-check H matix has modulo-m popeties that can be exploited to achieve hadwae paallelism [25]. The use of scalable paallelism to obtain chips with small aeas fo DVB-S2 has been poposed fo technologies anging fom 0.13 µm down to 65 nm [5-7,15,16] based on the pocessing of sub-sets of the Tanne gaph, which guaantee the minimum necessay thoughput of 90 Mbps euied by the standad [8]. The design of patial-paallel solutions geneates systems with lowe aeas, but also implies lowe thoughputs, compaing to full-paallel achitectues in a SoC. One of the achitectues initially poposed by Kienle et al. [5] uses M=360 pocesso nodes, also efeed in this text as Functional Units (FU). They wok in paallel and shae contol signals, that pocess both CN nodes (in CN mode) and IN nodes (in BN mode) accoding to a flooding schedule appoach. Attending to the zigzag connectivity [8] between PNs and CNs defined by B in (9), they ae updated jointly in CN mode [5]. An efficient VLSI achitectue has been poposed in [28,29], whee the joint pocessing of CNs andpnsispefomedasdepictedinfigue3.fo example, when updating PN m, accoding to (6) it becomes a passing node because the message it sends to CN m+1 is the message eceived fom CNm added to the channel infomation, and vice-vesa (see Figue 3). Since each FU pocesses consecutive CNs, the update of PNs follows an hoizontal schedule appoach, with PNs and CNs being pocessed simultaneously. This scheduling mechanism allows a faste decoding convegence [30]. Theefoe, the message that tavels though CN m, PN m and CN m+1 is kept in the FU and only the backwadmessagethatissentfomcn m to PN m-1 is saved in the extenal memoy. The euations that descibe the opeation inside the FU in CN mode ae [29]: ( L mn = ( L m PNm 1 = L n m n IN(m)\n L n m n IN(m) ) L PNm m Mem (12) ) L PNm m (13) LQ PNm 1 =Mem+L m PNm 1 (14) and [( ) Mem = n IN(m) L n m ] Mem + Lp PNm (15) Consecutive check nodes (e.g. CN m and CN m+1 ) ae pocessed by the same FU PN m-1 PN m PN m+1 L PNm Lp PNm L PNm-1 L PNm L PNm-1 MEM MEM CN m-1 CN m CN m+1 MEM MEM L IN L IN L IN L IN Figue 3 Zigzag connectivity of a functional unit descibing the joint pocessing of CNs and PNs.

8 Page 8 of 16 whee IN(m) epesents the set of INs connected to CN m, and Mem is the intenal memoy of the FU. All 360 FUs pocess one message pe cycle. In IN mode, the 360 messages ae ead fom the same addess (seuentially incemented, fo this type of pocessing) in the espective memoy blocks. The new messages esulting fom this computation ae then stoed in the same addess cyclically shifted ight though the inteconnection netwok, implemented by a bael shifte. The modulo-m popeties of LDPC codes used in DVB-S2 allow to eplace the complex inteconnection netwok by a common bael shifte. In CN mode, messages have to be ead fom specific addesses and stoed back in the same addesses cyclically shifted left to conclude the execution of an iteation. Once again, the access is pefomed in paallel fo all 360 messages. The bael shifte mechanism and the efficient memoy mapping scheme constitute the majo stengths of the achitectue descibed in [5]. Memoy euiements fo a patially paallel achitectue capable of suppoting long length codes used in DVB-S2 ae demanding. The appopiate Contol of ADDRESSES and SHIFTS memoy banks indicated in Figue 2 guaantees that evey time the addess of a memoy block changes, it changes accodingly and without conflicts fo all M = 360 pocessos in paallel. The bael shifte, which has a switching activity contolled by the SHIFTS memoy bank, can be popely managed togethe with the ADDRESSES memoy block that defines memoy accesses, to simulate the connectivity of the Tanne gaph. In [5] it is illustated the memoy mapping mechanisms used in BN pocessing as a function of (a paamete defined by the standad), which is pesented in (11). In CN pocessing, a simila scheme applies. Fo each diffeent code we use diffeent SHIFTS and ADDRESSES values, which can be easily obtained fom annexes B and C of the DVB-S2 standad [8]. In Figue 4 mainly thee distinct types of memoy ae depicted: Channel memoy which initially eceives data (IN and PN) fom the input of the LDPC decode; (ii) Message memoy, whee all messages associated with infomation bits ae stoed (the FU suppots both types of BN and CN pocessing, which pefom altenately duing the same iteation); and (iii) PN Message memoy that holds messages associated with paity bits, which ae computed in CN mode and have all weight w c = 2 (zigzag connectivity depicted in Figue 3). In PN Message memoy each FU only needs to stoe the message which is passed duing the backwad update of CNs [14]. Howeve, the lage numbe of FUs used (360) still implies a wide and complex bael shifte that euies a significant die aea and imposes outing poblems in ode to accommodate the simultaneous accesses of all 360 FUs to coesponding messages in memoy. Since this achitectue is able to povide, with the cuent technology, a thoughput fa above the mandatoy 90 Mbps, we ae able to educe the numbe of FUs even futhe. In fact, we heein show that this can be done by any intege facto submultiple of M = 360, which, fo VLSI systems, pesents a beneficial eduction of the size of the bael shifte. 4 M-factoizable VLSI paallel LDPC decode achitectue fo DVB-S2 Unde this context we developed a novel hadwae appoach, oiginally poposed in [14,28], which is based on a patial-paallel achitectue that simplifies the bael shifte and educes memoy euiements. We addess the genealization of the well known M-kenel paallel hadwae stuctue [5] and popose its patitioning by any intege L submultiple of M (which can be obtained fom the decomposition of M =360= ), without memoy addessing/econfiguation oveheads and keeping unchanged the efficient message-passing mechanism. The poposed achitectue povides an efficient way of educing the numbe of FUs and the oveall complexity of the decode. This appoach does not only supass some disadvantages of the achitectue descibed in [5], such as die aea occupied o outing congestion, but it also adds flexibility and econfiguability to the system accoding to the decode euiements and device constaints. This type of sub-sampling appoach peseves the key modulo-m popeties of the achitectue [5], with only P = M/L pocessing units addessed in [28,29] as shown in Figue 2. This stategy allows a linea eduction by L of the hadwae esouces occupied by the FU blocks, and educes significantly the complexity (2 O(P log P)) of the inteconnection netwok (o bael shifte), which simplifies the outing poblem. This stategy does not imply an incease by L in the size of ROM memoies (that hold SHIFTS and ADDRESSES values). In fact, by pefoming a sub-sampling by L, eachgoupofm=360 INs o CNs esults in L subgoups of P INsoCNs.Asthepopetiesof the fist subgoups of CNs and BNs to pocess ae known, the modulo-m peiodicity of DVB-S2 codes allows to automatically calculate the popeties of the emaining subgoups. Based on the SHIFTS shift 0 to apply to the fist subgoup, we can obtain the emaining subgoups g, with 0 g L-1 by [14]: shift γ =(shift 0 + γ )div L. (16) The same applies fo ADDRESSES, which can be computed as: addess γ = (addess 0 + w c γ )mod( w c L). (17)

9 Page 9 of 16 Channel memoy 5 Message memoy IN/CN mode ADDRESSES Addess calculato 1 0 PN Message memoy FU s contol FU 1 FU 2 FU 3 FU SHIFTS VLDW BUS Bael shifte Shift calculato Figue 4 Optimized 45 functional units achitectue. Fo the achitectue to suppot only P FUs (instead of the M=360 FUs as in [5]), memoy blocks have to be eoganized accoding to (16), (17) and Figues 2 and 5. We can eshape these memoy blocks and keep unchanged the size of the system ROM, by computing on the fly the new SHIFTS as a function of those initially stoed in the ROM, as indicated in (16). In the configuation shown in Figue 2, each FU i,with0<i<p- 1, is now esponsible fo pocessing infomation (IN), paity (PN) and CN accoding to a pope memoy mapping and shuffling mechanism. As we incease L, the smalle become the sub-sets of the Tanne gaph pocessed in paallel. Figue 5 descibes the addessing mechanisms used in the factoizable achitectue fo L= 2, which uses 180 FUs. The amount of memoy is exactly the same as in the achitectue with L=1, but the stuctue is diffeent. Thee ae less FUs and the coesponding memoy wod size deceases. As shown in Figue 2, memoies have to become highe and thinne in ode to hold the same infomation as befoe. This new memoy configuation will intoduce benefits in aea occupied by the achitectue, as it will be shown late. 5 Optimizing RAM memoy design based on maco cells fo ASIC The pesented achitectue has been descibed in RegisteTansfeLevel(RTL)foP={45,90,180,360}FUs. All solutions use 5-bit to epesent data messages. Figue 2 shows that all fou configuations use exactly the same amount of memoy, though eaanged with diffeent widths and heights (distinct memoy dimensions). ThesmallethenumbeofP functional units adopted, the highe and thicke block memoies become. The

10 Page 10 of 16 Message mapping INs BN weight w b 360(-1) FU 0 FU 1 FU 179 Bael Shifte CN weight w c Legend: st goup nd goup Message mapping CNs Figue 5 Memoy oganization using M = 180 functional units. Memoy oganization fo the computation of L mn and L nm messages, automatically adapted fo a L = 2 factoizable achitectue with coesponding P = 180 functional units [5]. complete type and amount of memoies necessay fo such design ae: Message memoy holds intenal messages calculated duing each iteation of the decoding pocess associated with IN; Message memoy width (wod length) is given by w a = numbe of FU message, which in this case is w a =M 5/L bits; the height h mm can be obtained fo wost case scenaio (code with ate = 3/5 obtained fom Table 2, whee the numbe of edges is maximum). In this case, h mm =L (w c - 2); Channel memoy stoes IN and PN data incoming fomthechannel.thismemoyhasthesamewod length as Message memoy (w ch = w a ), and the height is given by h ch = L 64800/M, epesenting the wost case (nomal fame); PN message memoy holds messages calculated duing each iteation, which ae associated only with paity bits. It has the same width as Channel memoy and the height h PN = L is obtained fo wost case scenaio (code with ate =1/4)fomTable2, which tuns = 135 (only one 5-bit message pe each paity bit has to be stoed); Had decoding memoy holds IN and PN data obtained in the had decoding phase of pocessing (1-bit pe FU); the width of this memoy is given by the numbe M/L FUs of the achitectue, and the height h HD is obtained fom h HD = L 64800/M. Table 3 summaizes the euied width and height (mem. pos.) of all memoies used in the fou synthesized configuations. Unfotunately, sometimes RAM memoy

11 Page 11 of 16 Table 3 Reuied RAM memoy size fo each configuation Type of RAM 360 FUs 180 FUs 90 FUs 45 FUs (mem. pos. width) Message Channel (IN + PN) PN message Had decoding (IN + PN) libaies of maco cells do not exactly suppot all the specified heights euested in Table 3, but athe standad dimensions which ae usually a powe of 2, as shownintable4.theaeaesultsobtainedinthe synthesis pocess and shown in Table 5 allowed othe inteesting conclusions. Memoies occupy nealy 97% of the cicuits total aea. The emaining pat of the cicuit is occupied by the bael shifte, the functional units and the contol logic. The fact that in the fou configuations the aeas ae diffeent was also a supise. Table 5 shows these diffeences. As mentioned befoe and depicted in Figue 2, the total amount of memoy is the same fo all designs. If we ealize that they occupy a significant aea of the design, we conclude that thei diffeences should be minimal. To analyze these diffeences, we fist need to undestand how memoies ae geneated and the RAM geneato limitations. The achitectue implemented in RTL uses memoies with lage width (wod length) and height (numbe of wods, o memoy positions). The RAM geneato used can ceate memoies that suppot the euested numbe of wods, but the maximum wod width is limited to 64 bits, which is fa below the achitectual needs. To ovecome this poblem, B blocks of RAM memoy wee concatenated until the euied width was achieved, as shown in Figue 6. Each RAM memoy has its own intenal contol logic which can addess data in the opeating clock cycle, with its own antenna diode potection, testing mechanisms, powe ings, etc. As epesented in Figue 6, moe memoies ae necessay fo lage wods, which eplicates contol hadwae and inceases silicon aea. This seemed to show that some level of inefficiency should be expected. A pactical example with eal aeas can be addessed fo the Message RAMs fo 360 and 45 Table 4 Physical (eal) RAM memoy size fo each configuation Type of RAM 360 FUs 180 FUs 90 FUs 45 FUs (mem. pos. width) Message Channel (IN + PN) PN message Had decoding (IN + PN) FUs, to give a bette pespective of the poblem. In the fome configuation, the Message RAM width is 1,800 bits (5 bits pe message 360 FUs) with 2 10 addesses (height). Fo the second configuation, the RAM width is 225 bits (5 bits pe message 45 FUs) with 2 13 addesses. Both Message memoy blocks have the same capacity (2 10 1, 800 bits), howeve the aea used by the wide 360 FUs Message memoy is 6.2 mm 2,while the thine 45 FUs memoy occupies only 3.2 mm 2. These memoies wee ceated by concatenating B banks of 45 bit RAMs, as illustated in Figue 6. Fo 360 FUs, 40 instantiations ae necessay (40 45 bits = 1,800 bits) while fo 45 FUs only five instantiations ae needed (5 45 bits = 225 bits). Whateve the factoization level L adopted, the achitectue will still have to suppot a Vey Long Data Wod (VLDW) bus. This popety is illustated in detail in Figue 4, whee the VLDW bus implies a complex outing of the wiing associated with it. This intoduces additional complexity managing the floo planning and outing pocess (in the place & oute phase of the design). Nevetheless, the achitectue with 45 FUs minimizes this poblem by moving its complexity to a dimension whee it can be moe easily tactable. 5.1 Minimal RAM memoy configuation Fom all designs in Table 5 the achitectue with 45 FUs occupies the smallest aea. Compaing Tables 3 and 4, we notice that due to hadwae estictions, thee is a Table 5 Optimized synthesis esults fo ASIC optimized Technology (nm) Max. voltage (V) Typ. voltage (V) Min. voltage (V) Max. tempeatue ( C) Typ. tempeatue ( C) Min. tempeatue ( C) Fe. opeation (MHz) Powe (mw) Cuent (ma) Gate count (Mgates) Aea (mm 2 ) ASIC synthesis esults fo P = {45, 90, 180, 360} paallel functional units and fo an optimized 45 functional units achitectue

12 Multiplexe S 1 D Counte S 2 U/ D B 1 C ENB SE Reset B 4 T Cay out ENB CL R Page 12 of 16 x/b x/b x/b x/b x/b x/b x/b x/b Impot existing memoies y Tiling engine RTL Used memoy Unused memoy S R Q Q EN B Figue 6 Tiling of an y (height) by x (width) RAM memoy layout based on maco cells. potion of the RAM which is neve used. The 45 FUs achitectue Message RAM, fo instance, needs = 1,166,400 bits. But physically, we have = 1,843,200 bits, esulting in about 37% unused bits. This fact occus in all memoies and fo all achitectues and we tied to minimize it by using decompositions into powes of 2 and concatenating smalle RAMs, but we ealized that instead of deceasing, the aea inceases nealy 30%, which can be justified by the additional numbe of intenal RAM hadwae contolles incopoated into the design. Howeve, joining togethe seveal blocks of memoy that opeate in diffeent time slots into one bigge common block of memoy can become a moe efficient solution. By analyzing in detail the Message memoy block of the achitectue with 45 FUs depicted in Figue 4, each 5 bits of the wod ae diectly connected to each FU, and conseuently only one main memoy block is used, as mentioned in the beginning of Section 5. Theefoe, the contol is uniue and only one (wite o ead) addess is needed to tansfe data to/ fom all FUs. This memoy must be a dual pot RAM, in ode to allow eading and witing duing the same clock cycle. Howeve, due to memoy geneato limitations in the tools used, this type of memoy was not possibletoachieve.toovecomethis,weadopteda solution that consists of ceating a memoy that opeates at twice the cicuit s feuency (f op ): in the fist cycle it pefoms ead opeations; and in the second one it wites data to memoy. The system s masteclock opeates at 200 MHz and it is used to feed memoy blocks, while f op = 100 MHz is synchonously deived fom this clock souce. The LDPC decode input data comes fom an extenal de-inteleave module that does not wok at the same clock feuency as the LDPC decode. To guaantee that no infomation is lost, all messages deliveed to the decode must be stoed in Channel memoy. The PN message memoy is eually stoed on a dual pot RAM which, due to memoy geneato limitations as befoe, was conveted into a single RAM woking at twice of the initial feuency. In the beginning, this memoy is loadedwithzeos,andthenitwillholddataassociated with paity bits necessay in each iteation of the decoding pocess. Shift and addess data ae loaded fom an outside souce into SHIFTS and ADDRESSES memoies. The values stoed in these memoies depend on the code ate and must be peviously calculated. 6 Expeimental esults In the next subsections we pesent the obtained expeimental esults fo the achitectue in Figue 2, which was synthesized fo ASIC using a 90 nm CMOS pocess design. Place & oute was pefomed using eight metal layes. Memoies wee synthesized using a geneic RAM geneato tool with libaies of maco cells. Estimates fo powe consumption wee obtained assuming a toggling ate of 10%. The achitectue was also synthesized fo Field-Pogammable Gate Aay (FPGA), but only fo validation puposes [14]. 6.1 Expeimental synthesis esults fo ASIC Synthesizing in ASIC technology the achitectue with P = {45, 90, 180, 360} FUs aims at finding the one which poduces bette powe consumption and aea esults, while simultaneously suppoting the thoughput euiements of the standad. The achitectue suppots shot and nomal fame lengths fo all code ates, even though it is dimensioned fo the wost case. All ates in

13 Page 13 of 16 the solutions hee poposed suppot 90 Mbps as euied by the DVB-S2 standad. Figues 7a) and 7b) epot thoughput pefomance achieved fo nomal and shot fame length DVB-S2 codes decoding ten iteations. Fo example, with P = 90 FUs (o euivalently L = 4) in the nomal fame mode, fo code with ate = 1/4 the thoughput supasses 295 Mbps, while with P =90 FUs it eaches 1.18 Gbps. Figues 7c) and 7d) epot the maximum numbe of iteations suppoted by the achitectue woking at 100 MHz, while poducing the DVB- S2 taget thoughput of 90 Mbps. Fo example, fo P = 180 FUs (L = 2) in the nomal fame mode, a maximum of 65 iteations is suppoted when decoding ate = 1/4, while 27 iteations ae achieved fo code with ate 3/5 (wost case woking conditions fo DVB-S2). Half these values ae obtained with P = 90 FUs (L = 4) and a value fou times infeio is achieved with P = 45 FUs (L =8). It can also be seen that a maximum of 55 iteations is suppoted fo the configuation with P = 90 FUs decoding the wost case code. Technical limitations imposed by the available libay of memoy maco cells, namely the maximum feuency of opeation at 200 MHz and the fact that they do not suppot dual-pot memoies, have put limits on thoughput and maximum numbe of iteations suppoted. To exemplify this, ou achitectue implemented with P = 45 FUs suppots at maximum seven iteations when decoding at a thoughput of 90 Mbps fo wost case woking conditions, as depicted in Table 6. By using dual-pot memoies, o memoies capable of suppoting feuencies in the ange of 400 MHz (that would allow to have the main cicuit opeating at 200 MHz), it would be possible to achieve 14 iteations fo wost case condition (see Table 6) without additional modifications in the design, at the expense of an incease in powe consumption. To validate this assumption, we e-synthesized the achitectue with the cicuit opeating at f op = 125 MHz and then at f op = 200 MHz (as indicated in Table 6) and no timing violations occued. In (18) and (19) it is descibed how the thoughput and maximum numbe of iteations wee calculated fo Figue 7, with the feuency of opeation selected at f op = 100 MHz, i.e.: Thoughput = fame length f op ((2 W + w j 3) max ite L). (18) The vaiables fame_length, W and w j depend on code length and ate, and can be found in the standad [8]. 9/10 8/9 5/6 45 FUs 90 FUs 180 FUs 360 FUs 8/9 37/45 7/9 45 FUs 90 FUs 180 FUs 360 FUs Code Rate 4/5 3/4 2/3 3/5 1/2 2/5 1/3 Code Rate 11/15 2/3 3/5 4/9 2/5 1/3 1/4 1/ (a) (b) Code Rate 9/10 8/9 5/6 4/5 3/4 2/3 3/5 1/2 45 FUs 90 FUs 180 FUs 360 FUs Code Rate 8/9 37/45 7/9 11/15 2/3 3/5 4/9 45 FUs 90 FUs 180 FUs 360 FUs 2/5 2/5 1/3 1/3 1/4 1/ (c) (d) Figue 7 Decoding pefomance. (a) Thoughput pefomance fo nomal fame DVB-S2 codes with P = {45, 90, 180, 360} FUs pefoming ten iteations; (b) thoughput pefomance fo shot fame DVB-S2 codes with P = {45, 90, 180, 360} FUs pefoming ten iteations; (c) maximum numbe of iteations fo nomal fame DVB-S2 codes with P = {45, 90, 180, 360} FUs fo a 90 Mbps thoughput; (d) maximum numbe of iteations fo shot fame DVB-S2 codes with P = {45, 90, 180, 360} FUs fo a 90 Mbps thoughput.

14 Page 14 of 16 Table 6 Compaing state-of-the-at synthesis esults [5] [6] [7] [15] [16] [31] This a This b This c Technology (nm) / Fe. op. (MHz) / Powe (mw) / Aea (mm 2 ) / Thoughput (Mbps) Max. numbe of ite ASIC synthesis esults fo state-of-the-at achitectues in the liteatue a Synthesis esults fo the poposed optimized achitectue with 45 FUs and a cicuit clock feuency f op = 100 MHz b Synthesis esults fo the poposed optimized achitectue with 45 FUs and f op = 200 MHz c Estimated synthesis esults fo the poposed optimized achitectue with 45 FUs, scaled fo a 65 nm pocess design with the same paametes as [7] (i.e., f op = 400 MHz) The vaiable W defines the numbe of elements of A in the compact fom (see (9)) as pesented in annexes B and C of the standad [8]. It can be computed fom Tables 1 and 2 by pefoming: W = IN weight j weight j +IN weight 3 3, (19) 360 whee IN_weight_j and IN_weight_3 ae the numbe of IN nodes with weights weight_j and 3, espectively. Table 5 shows that the total aea of the cicuit is eual to 21.2 mm 2 fo a 360 FUs solution, while the achitectue with 45 FUs can be obtained with only 7.7 mm 2. Diffeent pats of the achitectue wok at two distinct clock feuencies, namely 100 and 200 MHz, and fo the solution with 45 FUs we estimate a powe consumption of appoximately 105 mw. Final cicuit validation has been pefomed by place & oute using eight metal layes. No time, physical o outing violations wee epoted, so at this stage the 45 FUs achitectue is physically validated. At this point and due to the configuable natue of the achitectue, we found oom to pefom some exta optimizations. Fo pactical puposes, and since it pesented good esults fo thoughput and aea, we adopted the configuation based on 45 FUs as the basis solution to be optimized. The next subsection shows that thee is still oom to pefom optimizations and how to achieve that. 6.2 Expeimental synthesis esults fo ASIC using an optimized 45 FUs achitectue To tanslate the optimizations mentioned in Section 5.1 into aea esults, the new cicuit has been synthesized fo the same 90 nm technology used in the oiginal synthesis. The optimizations educe the aea of the smallest oiginal achitectue nealy 20%. Synthesis esults fo the peviously mentioned P = {45, 90, 180, 360} FUs based achitectues and also fo the optimized 45 FUs vesion ae listed in Table 5. The aeas ange fom 21.2 to 6.2 mm 2, with coesponding levels of powe consumption of, espectively, 290 mw down to 85 mw. The 45 FUs achitectue optimized with an efficient RAM memoy eshape pesents a total aea of 6.2 mm 2 and 85 mw of powe consumed at a typical cone voltage of 1.1 V. The estimation of powe consumption was pefomed by consideing typical cone opeating conditions fo cuent, voltage and tempeatue. This appoach was followed because exteme woking conditions usually do not occu, o if they do, it is duing small peiods of time which does not negatively affect the design. No timing o design ule check (DRC) violations wee epoted, so at this stage the 45 FUs optimized achitectue is physically validated and eady to be implemented in silicon. To accommodate place & oute, it should be noted that, based on pevious design expeience, we estimated an incease in aea euivalent to 20% (afte final validation, we ealized that it could have been appoximately 19%), which coesponds to a global aea of 7.4 mm 2 fo the optimized 45 FUs achitectue. 6.3 Discussion The assessment of synthesis aea esults fo the poposed achitectue pesented in Table 5 shows that it compaes well with state-of-the-at solutions [5-7,15,16,31]. Table 6 compaes synthesis esults fo state-of-the-at achitectues with the 45 FUs-optimized achitectue hee poposed. A 90 nm technology is used in [6,16], poducing, espectively, an aea of 4.1 and 9.6 mm 2. Although it is not possible to fully assess [6] because impotant chaacteistics of the cicuit such as powe consumption ae not indicated and only aea and thoughput ae mentioned, it is impotant to efe that the achitectue in [6] pesents a smalle aea but it only suppots the nomal fame mode of opeation. Results fo simila achitectues but using diffeent technologies have been pesented: fo example, fo a 0.13μm technology, an aea of 22.7 mm 2 has been achieved [5], while [7] pesents 3.9 mm 2 fo a 65 nm technology, and [15] achieves 6.03 mm 2 fo the same 65 nm technology.

15 Page 15 of 16 Although some of them claim to occupy smalle die aeas, ou solution suppots both fame lengths, while [6,7] only suppot the nomal fame mode. Also, consideing that ou design is based on a 90 nm pocess, it compaes favoably in tems of aea against [7,15], which use a 65 nm technology as mentioned befoe. The new achitectue hee poposed based on 45 FUs shows an LDPC decode cicuit with smalle aea occupied than those epoted in [5,16]. Moe ecently, Kim et al. [31] pesented an achitectue with an excellent thoughput of 520 Mbps but at the expense of a cicuit aea eual to 12.4 mm 2 fo a 90 nm pocess. Fo powe consumption puposes, pehaps most impotant is the fact that ou achitectue woks with an infeio maximum feuency of opeation than those just epoted in state-of-the-at solutions [5,7,15,16]. While [5,15] popose achitectues with opeating feuencies of 270 MHz, the one in [7] euies 400 and 320 MHz in the case of [16]. In the new appoach heein poposed, 45% of the cicuit woks at 200 MHz, while the emaining 55% wok at 100 MHz. The powe consumption euied by ou achitectue is infeio to those mentioned by competitos. Namely, 477 mw ae epoted in [15] fo best case woking conditions, while we achieved 105 mw fo the 45 FUs achitectue and 85 mw fo the optimized vesion of it, as depicted in Tables 5 and 6. By scaling the poposed achitectue to a 65 nm technology using the same paametes as those epoted in [7] and coespondingly inceasing the feuency of opeation to 400 MHz (which is possible as long as pope memoy technology is adopted), it is possible to incease the maximum numbe of iteations suppoted by this achitectue to 28 fo wost case woking conditions, which fo DVB-S2 occus fo code with ate = 3/ 5. 7 Conclusions This aticle addesses the genealization of a state-ofthe-at M-kenel paallel stuctue fo LDPC-IRA DVB- S2 decoding, fo any intege facto of M = 360. The poposed achitectue adopts a patitioned pocessing of subsets of the Tanne gaph that keeps unchanged the efficient message memoy mapping stuctue without addessing unnecessay oveheads. This achitectue poves to be flexible and easily configuable accoding to the decode constaints and epesents a tade-off between silicon aea and decode thoughput above the euied 90 Mbps fo all DVB-S2 codes. Unde this context, five configuation designs with diffeent numbe of pocessing units have been synthesized using ASIC technology. They ange fom 360 to 45 FUs which epesents, espectively, an euivalent occupied aea of 21.2 and 7.7 mm 2. Although the pocess of geneating RAM memoies imposes constaints, the investigation caied out unde the context of this aticle allowed seveal inteesting conclusions that wee applied into the design of the LDPC decode cicuit. Re-dimensioning and eaanging the ode how memoy blocks ae gouped togethe allowed educing the global aea of the cicuit to a value as low as 6.2 mm 2. Additional impovements in aea could still be expeienced eithe by using a diffeent numbe of metal layes, o by adopting full custom RAM memoies in the cicuit design. Since in the pesent case nealy 97% of the cicuit s aea is occupied by memoy blocks and we used a geneic RAM geneato tool, the aea occupied by the cicuit can be futhe educed if we euie to the foundy the use of dedicated RAM memoy cells. This shows the competitiveness of the achitectue when compaed with state-ofthe-at solutions fo the same 90 nm technology. Moeove, the maximum feuency of opeation of the design hee poposed is smalle than those epoted by competitos, which justifies the low levels of powe consumption achieved of appoximately 85 mw. Acknowledgements This study was patially suppoted by the Potuguese Foundation fo Science and Technology (FCT), namely though the PIDDAC pogam funds and unde gants SFRH/BD/37495/2007 and SFRH/BD/38338/2007, and also by FCT poject PEst-OE/EEI/LA0008/2011. Autho details 1 Instituto de Telecomunicações, Pólo II - Univesidade de Coimba, Coimba, Potugal 2 Depatment of Electical and Compute Engineeing, FCTUC, Pólo II - Univesidade de Coimba, Coimba, Potugal 3 INESC-ID, R. Alves Redol, no. 9, Lisboa, Potugal 4 Depatment of Electical and Compute Engineeing, Instituto Supeio Técnico, Av. Rovisco Pais, no. 1, Lisboa, Potugal Competing inteests The authos declae that they have no competing inteests. Received: 12 May 2011 Accepted: 9 Mach 2012 Published: 9 Mach 2012 Refeences 1. RG Gallage, Low-density paity-check codes. IRE Tans Inf Theoy. 8, (1962). doi: /tit R Tanne, A ecusive appoach to low complexity codes. IEEE Tans Inf Theoy. 27(5), (1981). doi: /tit C Beou, A Glavieux, Nea optimum eo coecting coding and decoding: tubo-codes. IEEE Tans Commun. 44(10), (1996). doi: / D Mackay, R Neal, Nea shannon limit pefomance of low density paity check codes. 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