Galvanic Isolation System with Wireless Power Transfer for Multiple Gate Driver Supplies of a Medium-voltage Inverter

Transcription

1 IEEJ Jounal of Industy Applications Vol5 No3 pp06 4 DOI: 054/ieejjia506 Galvanic Isolation System with Wieless Powe Tansfe fo Multiple Gate Dive Supplies of a Medium-voltage Invete Keisuke Kusaka Student Membe, Koji Oikawa Membe Jun-ichi Itoh a Membe, Isamu Hasegawa Non-membe Kazunoi Moita Membe, Takeshi Kondo Non-membe (Manuscipt eceived Apil 30, 05, evised Sep, 05 Pape In this pape, a gate dive supply, which supplies powe to multiple gate dives, is demonstated Robust isolation is equied in the gate dive supplies of a medium-voltage invete in ode to dive high-voltage switching devices such as insulated-gate bipola tansistos The poposed isolation system achieves isolation with tansmission coils mounted on pinted cicuit boads Futhemoe, the isolation system tansmits powe fom one tansmitting boad to six eceiving boads In the conventional system, the numbe of eceives is limited to one In contast, multiple eceives ae acceptable in the poposed system These chaacteistics help educe the of the isolation system fo the gate dive supplies This pape pesents the fundamental chaacteistics of the isolation system The equivalent cicuit of the poposed system can be deived by applying the equivalent cicuit of a wieless powe tansfe system with a epeate coil In addtion, a design method fo the esonance capacitos is mathematically intoduced using the equivalent cicuit It is veified that an isolation system with multiple eceives can be designed using the same esonance conditions as an isolation system with a single eceive Moeove, the isolation system is expeimentally demonstated It is confimed that the isolation system tansmits powe with a maximum efficiency of 469% at an output powe of 66 W beyond an ai gap of 50 mm with only pinted cicuit boads Keywods: wieless powe tansfe, inductive coupling, isolation, medium-voltage invete, gate dive Intoduction In ecent yeas, the system voltage of a thee-phase medium-voltage invete fo industial applications has isen to 33 kv o 66 kv ( (5 In a medium-voltage invete, galvanic isolation is equied at each gate dive supply The standads of isolation, which ae published by the Intenational Electotechnical Commission (IEC, ae well-known safety egulations Fo example, the safety standads of the IEC equie a minimum cleaance of 4 mm and a ceepage distance of 8 mm unde the following conditions: the woking voltage of the invete is 80 kv, and the compaative tacking index (CTI is 00 CTI < 400 with a pollution degee of (6 In geneal, isolation tansfomes with coes ae commonly used fo isolation Howeve, they cause an incease in cost because isolation tansfomes ae typically custom built In addition, the isolation tansfome is lage in ode to obtain a high isolation voltage Fo example, a Coespondence to: Jun-ichi Itoh itoh@vosnagaokaut acjp Nagaoka Univesity of Technology 603-, Kamitomioka-machi, Nagaoka, Niigata , Japan MEIDENSHA CORPORATION 55, Kaminakamizo, Higashimakado, Numazu, Shizuoka , Japan the typical dimensions of the isolation tansfome, which has an isolation voltage of 0 kv ms fo 0 s, ae 00 mm 00 mm 00 mm at a weight of appoximately 55 kg (7 These tansfomes must be placed at each of the gate dive supplies In ode to achieve the cost eduction and downsizing of the isolation system, a single-chip DC-isolated gate dive integated cicuit (IC has been poposed (8 (0 It supplies powe using a micowave fom the bottom laye of a sapphie substate to the top laye In this method, the sapphie substate assumes galvanic isolation It can significantly downsize the isolation system Howeve, it does not satisfy the safety standads of the medium-voltage invete because the ceepage distance is not enough In (, galvanic isolation is assumed by an optical fibe The powe fo a gate dive is supplied though an optical fibe Howeve, the tansmitted powe is limited to 00 mw pe one fibe Meanwhile, JW Kola et al have poposed an isolation system using pinted cicuit boads (PCBs ( It achieves galvanic isolation with a coeless tansfome Howeve, one tansmitting side tansmits powe to only one eceiving side one-by-one ( in this system Thus, isolation systems ae also equied at each gate dive supply Theefoe a numbe of isolation systems ae equied in ode to supply powe This pevents the downsizing of isolation systems c 06 The Institute of Electical Enginees of Japan 06

2 Isolation System fo Gate Dives of Medium-voltage Invete Keisuke Kusaka et al In this pape, the galvanic isolation system with multiple eceives is demonstated and analyzed based on an equivalent cicuit The isolation system tansmits powe fom one tansmitting boad to six eceiving boads ( 6 beyond an ai gap of 50 mm The isolation system contibutes to the cost eduction and downsizing of the isolation system Moeove, the isolation with an ai gap of 50-mm easily meets the standads fo cleaance and ceepage distance when the system voltage of the invete is 66 kv Moeove, the 50 mm ai gap deceases the common-mode cuent, which is induced by the high-dv/dt switching of a medium-voltage invete This pape fist descibes the system configuation of the poposed isolation system Secondly, the equivalent cicuit of the wieless powe tansfe system with multiple PCBs is intoduced The validity of the equivalent cicuit model is evaluated by compaing the F-matix of the wieless powe tansfe system between the thee-dimensional (3-D electomagnetic analysis and the equivalent cicuit model Then, the evaluation of the equivalent cicuit and the design method of esonance capacitos fo efficient wieless powe tansfe ae mathematically claified Finally, the expeimental esults ae pesented Poposed Isolation System System Configuation Figue shows the concept of the poposed isolation system fo a medium-voltage invete The isolation system consists of one tansmitting boad and six eceiving boads The powe consumption in the gate dives is supplied though the isolation system fom a low-voltage powe supply of 4 V in a medium-voltage invete Incidentally, a wieless powe tansfe system with a high quality facto Q of the tansmission coils has been studied in ecent yeas (3 (7 Wieless powe tansfe systems use esonance in ode to compensate fo leakage inductance because weak magnetic coupling causes a lage leakage inductance (4 Common techniques ae used in the poposed system In the conventional system, the tansfome with a coe pevents the cost eduction and downsizing of the isolation system In contast, the isolation system is constucted using only PCBs in this system The PCBs can be manufactued easily and inexpensively in compaison with the tansfome This configuation contibutes to a weight saving of the isolation system The total weight of the isolation system fo six gate dives is appoximately 890 g In the isolation system, a tansmission fequency of 0 MHz is used because a high-fequency tansmission is equied in ode to decease the equied inductance fo esonance Moeove, the opeation at a high fequency above MHz limits the selection of MOSFETs Figue shows the positional elationship of the tansmitting boad and the eceiving boads The maximum size of the system is constained up to 300 mm 50 mm 50 mm due to the space limitations of the medium-voltage invete The eceiving boads ae placed at the top and bottom of the tansmitting boad Each distance between the eceiving boads and the tansmitting boad is kept at a minimum of 50 mm fo the galvanic isolation It contibutes a obust galvanic isolation and a low common-mode cuent though paasitic capacitances It is enough to fulfill the safety standads Fig Concept of the poposed isolation system Fig Placement of the tansmitting boad and eceiving boads Each boad is placed acoss an ai gap of 50 mm of the IEC (6 when the output voltage of the medium-voltage invete is 66 kv Note that an ai gap of 50 mm contains a sufficient magin towads poductization The numbe of eceiving boads can be inceased by expanding the tansmission boad Howeve, the expansion of the tansmission boad causes an incease of the equivalent seies esistance of the tansmission coil It will decease tansmission efficiency Besides, the geatest common denominato of the numbe of switches fo thee-phase invetes is six Thus, six eceiving boads ae placed in this pape Figues 3 and 4 show the shapes of the tansmitting coils and eceiving coils, espectively Tansmitting boad #0 consists of a high-fequency invete, a seies esonance capacito, and a tansmitting coil fo a wieless powe tansfe system The invete is opeated by a squae wave opeation with an output fequency of MHz On the othe hand, eceiving boads # 6 consist of eceiving coils, seies esonance capacitos, and diode bidge ectifies The thickness of the coppe film fo both boads is 75 μm Evaluation of Paasitic Capacitance In this section, the paasitic capacitance between the tansmitting boad and the eceiving boads is evaluated The paasitic capacitances between the tansmitting boad and the eceiving boads should be suppessed because paasitic capacitances educe the isolation pefomance The paasitic capacitances among the boads coespond to the capacitance between a pimay winding and a seconday winding in a conventional isolation system with a tansfome In paticula, 07 IEEJ Jounal IA, Vol5, No3, 06

3 Isolation System fo Gate Dives of Medium-voltage Invete Keisuke Kusaka et al Fig 3 (a Component side (b Solde side Schematics of the tansmitting boad (a Component side Fig 4 (b Solde side Schematics of the eceiving boad since the silicon cabide (SiC MOSFETs have begun to be used in place of conventional Si-IGBT, suppession of the paasitic capacitance is impotant A SiC-MOSFET will impove the efficiency of medium-voltage invete because a SiC-MOSFET geatly impoves the switching speed due to its high electonic mobility (8 (9 Thus, a lage commonmode cuent caused by high dv/dt flows into the contol cicuit though the paasitic capacitance between the windings The suppession of the paasitic capacitances is stongly equied Howeve, it is difficult to calculate the exact paasitic capacitance because the shapes of the conductos on the tansmitting boad and the eceiving boad ae complicated The measuement of the paasitic capacitances between the boads is also difficult since the paasitic capacitances ae vey small Thus, the paasitic capacitance is analyzed by an electomagnetic analysis (Agilent, ADS unde the wostcase assumptions that both the tansmitting boad and the eceiving boad ae coveed with coppe The electomagnetic analysis shows that the paasitic capacitances between the tansmitting boad and the eceiving boads with an ai-gap of 50 mm ae less than 44 pf This shows that the poposed isolation system deceases the paasitic capacitance in compaison with the conventional isolation system with a tansfome (0 ( 3 Analysis of Poposed Isolation System In this section, this pape fist pesents the equivalent cicuit of the multiple wieless powe tansfe system because the equivalent cicuit is equied in ode to design the esonance capacitance to compensate fo the leakage inductance The validity of the equivalent cicuit model is claified by a compaison of the F-matix between the equivalent cicuit model and a 3-D electomagnetic analysis Accoding to the equivalent cicuit, esonance capacitos that compensate fo the leakage inductance ae selected It is shown that the esonance conditions ae likewise given fo the isolation system with one eceive 3 Deivation of Equivalent Cicuit The poposed system supplies powe using a weak magnetic coupling fom the tansmitting coil to the each eceiving coils Fo this eason, a powe facto fom the view point of the output of the invete is extemely low In ode to compensate the leakage inductance using esonances, seies o paallel capacitos ae commonly used in the eseach field about a wieless powe tansfe (4 In this system, seies-seies compensation method is used The esonance capacitos (C 0 6 ae inseted in a seies to the each coil These esonance capacitos should be selected in ode to cancel out a eactance fom the view point of the output of the invete It means that the output powe facto of the invete should be unity Figue 5 shows the equivalent cicuit of the isolation system whee L le0 6 ae the leakage-inductances, L m 6 ae the magnetizing inductances, k ij is the coupling coefficient between boads #i and # j, N 0 6 ae the numbes of tuns, 0 6 ae the equivalent seies esistances, and a is the tun atio defined as N 6 /N 0 The method of the deivation of the equivalent cicuit is descibed in the next paagaph The magnetic coupling among the eceiving coils can be ignoed because the magnetic coupling between the eceiving coils, which ae placed in side by side such as the boads # and #, is appoximately k = 0005 The magnetic coupling between the coils # and # is thee times smalle than the magnetic coupling between the coils #0 and # Figues 6(a and (b show a schematic and the equivalent cicuit of a wieless powe tansfe system with epeate coil (, espectively, whee L A C ae the self-inductances of each coil The equivalent cicuit of the poposed system shown in Fig 5 is deived by applying the equivalent cicuit of the epeate coil in ( (3 The epeate coil was invented in ode to extend the tansmission distance ( (3 In the wieless powe tansfe system with a epeate coil, the powe supply, which has the inne impedance Z 0, is connected to the coil A The powe is supplied to the coil C though the coil B because the coil B is magnetically coupled to both the coil A and coil B Figues 6(c and (d show the schematic and the equivalent cicuit of a wieless powe tansfe system with multiple eceives, espectively By intechanging the connection of the powe supply fom coil A to coil B in Fig 6(b, the equivalent cicuit of the wieless powe tansfe system with 08 IEEJ Jounal IA, Vol5, No3, 06

4 Isolation System fo Gate Dives of Medium-voltage Invete Keisuke Kusaka et al Fig 5 Equivalent cicuit of the poposed isolation system without convetes Fig 7 system Definitions of the F-paamete in the isolation (a Wieless powe tansfe system with epeating coil (b Equivalent cicuit of a epeating coil without coss coupling between the coil A and coil C Fig 8 F-matix between the tansmitting boad #0 and eceiving boad # (c Wieless powe tansfe system with multiple eceives (d Equivalent cicuit of a multiple wieless powe tansfe system without coss coupling between coil A and coil C Fig 6 Equivalent cicuit of the wieless powe tansfe system with a epeate coil ( and the wieless powe tansfe system with multiple eceives multiple eceives is intoduced Because the diffeence of the wieless powe tansfe system with a epeating coil and the multiple eceives ae only the connection of the powe supply Thus the equivalent cicuit of a wieless powe tansfe system with multiple eceives is shown in Fig 6(d It is notable that the magnetizing inductances L AB and L BC ae connected in seies to the powe supply V B with the inne impedance of Z 0 in the wieless powe tansfe system with multiple eceives Since the magnetizing inductances ae connected in seies, the equivalent cicuit of the poposed system shown in Fig 5 is detemined The coil B in Fig 6(d coesponds to the tansmitting coil #0 The coils A and B coespond to the eceiving coils #-6 The powe is tansmitted fom the tansmitting coil to the six eceiving coils with the magnetizing inductances, which is connected in seies fom the view point of v inv asshowninfig5 3 Evaluation of the Equivalent Cicuit In ode to evaluate the validity of the equivalent cicuit, the F-matix (ABCD-matix of the fequency chaacteistics (which is defined by Eq ( analyzed by 3-D electomagnetic analysis (Agilent, Momentum is compaed with the F-matix calculated by the equivalent cicuit The F-matix shows the elationship of a system between the input pot i and output pot j based on voltage and cuent The suffixes i and j indicate the numbe of PCBs (i, j = 0,,, 6 Fo simplicity, the F- paamete fom one boad #i to anothe boad # j is indicated as F(i, j ( V i = F (i, j İ i ( ( V j Aij B = ij ( V j ( İ j C ij D ij İ j Figue 7 shows the definitions of the F-paametes in the poposed system In this evaluation, only the chaacteistics of the coils ae evaluated Thus, the ideal powe supply with esistances of 50 Ω fo the inne impedance is connected instead of the convetes The inne impedance is necessay because the F-paametes ae calculated fom the analysis esults of the scatteing paamete (S-paamete by a simulato Moeove, the esonance capacitos ae omitted because the evaluation of the equivalent cicuit of the tansmission coils is the main pupose of this section Figue 8 shows each of the F-paametes between the tansmitting boad and eceiving boad # The solid line shows the F-paamete analyzed fom 3-D electomagnetic analysis The dashed-dotted line shows the F-paamete calculated fom the equivalent cicuit The dotted line shows 09 IEEJ Jounal IA, Vol5, No3, 06

5 Isolation System fo Gate Dives of Medium-voltage Invete Keisuke Kusaka et al İ inv = V { inv ( Δ + R + j (ωl le + ωl m } { ( + R + j (ωl le + ωl m } { ( 6 + R 6 + j (ωl le6 + ωl m6 } 6 (3 0 + j ( ωl le0 + ωl m + ωl m + + ωl m6 jωl m jωl m jωl m6 Δ= ( ( jωl m + R + j ωl le + ωl m 0 0 ( ( jωl m 0 + R + j ωl le + ωl m 0 jωl m6 0 0 ( 6 + ( R 6 + j 0 ωl le6 + ωl m6 6 (4 the F-paamete calculated fom the equivalent cicuit with coection coefficients, which ae mentioned late The F- paamete with the 3-D electomagnetic analysis has a selfesonance at a fequency of appoximately 7 MHz Howeve, the equivalent cicuit model does not conside self-esonance because the self-esonance fequency is fa fom the opeating fequency This is one of the easons fo the eo between 3MHzand0MHz Moeove, the F-paamete with the equivalent cicuit has offsets of appoximately 0 db between 00 khz and 3 MHz The eason fo the eo is the diffeence between the numbes of the actual windings and effective windings This means that a potion of the windings is not effective to induce the voltage This is a specific poblem when a tansmitting coil is placed on PCBs The diffeence can be coected using a coection coefficient α The coected tun-atio a of the tansfome is epesented as Eq ( using the coection coefficient α a = α N ( N The dotted line shows the F-paamete with the equivalent cicuit consideing the coection coefficient in Fig 8 The coection coefficients, which ae deived by tial and eo, ae α 6 = 6, 8, 7, 6, 8, and 7, espectively, in the pototype The ole of the coection coefficients α is to compensate the diffeence between the actual numbe of tuns and the effective numbe of tuns Induced voltages at coils ae not popotional to the actual numbe of tuns because the adii of the eceiving coils ae not constant when a spial coil is used Thus a magnetic flux patially intelinks acoss the eceiving coils It is specific chaacteistic when a spial coil without magnetic coe is used Fo this eason, the coection coefficients ae necessay in a time-domain analysis in ode to analyze the cicuit pefomance The F-paamete of the equivalent cicuit consideing the coection coefficient shows ageement with one of the electomagnetic analyses between 00 khz and 3 MHz 33 Design of Resonance Capacitos Figue 9 shows the equivalent cicuit of the poposed system with the convetes In the following calculation, the ectifies ae assumed as load esistances R 6 fo simplicity The esonance capacitos ae designed to cancel out the eactance owing to the leakage inductance Fom the equivalent cicuit, the output cuent of the invete is expessed as Eq (3, whee Δ is Fig 9 Equivalent cicuit with the powe convetes Eq (4 The pime paametes ae the paametes efeing to the pimay side In ode to coect the load powe facto, the eactance of the Eq (3 has to be zeo Thus, the esonance conditions ae deived as Eqs (5 and (6, whee ω = π f is the output angula fequency of the powe supply, and L 0 6 ae the selfinductances of the coils Equations (5 and (6 indicate that the esonance capacitos should be selected to esonate with each self-inductance because the sum of the esonance leakage inductance and the magnetizing inductances is equal to each self-inductance This means that the esonance conditions of the isolation system with multiple eceives ae the same as those of the isolation system with one eceive C 0 = ω (L le0 + L m + L m + + L m6 = ω L 0 C 6 = ω ( L le 6 + L = m 6 (5 ω L (6 6 The output cuent of the invete is developed with the esonance conditions as Eq (7 and Eq (8, which clealy show that the unity input powe facto of the load is achieved by the esonance V inv İ inv (ω=ω e = Δ (ω=ω e ( +R ( +R ( 6 +R 6 (7 0 IEEJ Jounal IA, Vol5, No3, 06

6 Isolation System fo Gate Dives of Medium-voltage Invete Keisuke Kusaka et al Fig 0 Vecto diagam of the poposed isolation system unde the esonance conditions ( Δ (ω = ω e = 0 + R ( + R ( 6 + ( ( R 6 +ω L m + R 3 + R 3 ( 6 + R 6 ( ( +ω L m + R 3 + R 3 ( 6 + R 6 ( ( ( +ω L m6 + R + R ( 4 + R R 5 (8 If all of the paametes on the eceiving boads and the coupling coefficients ae the same, the invete output cuent, which is povided by Eq (3, can be simplified as İ inv = V inv Δ whee Δ is { ( Δ= 0 + j ωl le0 + 6ωL m + 6ω L m { ( + R + j (ωl le + ωl m } 6 (9 } { ( ( + R + j ωl le + ωl m 0 { ( ( + R + j ωl le + ωl m } 5 (0 } 6 Fig Table Pototype of the isolation system Specifications of the pototype Figue 0 shows the vecto diagam unde the esonance conditions Fo simplicity, all of the paametes on the eceiving sides (including the load esistance ae assumed to be the same among the eceiving boads Moeove, the fundamental components ae only consideed hee The output voltages V in 6 is expessed by Eq ( when all of the paametes on the eceiving boads and coupling coefficients ae the same Note that it is effective only when the AC esistance loads ae connected to the tansmitting coil diectly, not the ectifies ( jωl m R +R 5 V in 6 (ω=ω e = ( 6+6ω ( 5 V inv 0 +R L m +R ( 4 Expeimental Veifications 4 System Setup of the Pototype Figue shows a photogaph of the isolation system pototype The tansmitting boad, which is shown in Fig 3, and the eceiving Fig Opeation wavefoms of the poposed system with esistance loads of 38 Ω boads, which ae shown in Fig 4, ae placed as shown in Fig The chassis is made fom acylic except fo clinches because eddy cuent losses should be suppessed Table shows the specifications of the pototype The laminated ceamic capacitos fo esonance ae selected to satisfy the esonance conditions shown as Eqs (5 and (6 Note that the coupling coefficients between the boads ae simulated values because it is difficult to measue the coupling coefficient accuately 4 Fundamental Chaacteistics Figue epesents the opeation wavefoms of the poposed isolation system Note that the esistances of 38 Ω ae connected at the outputs of the system instead of the gate dives fo simplicity The invete is opeated at a fequency of 0 MHz The DC voltages ae obtained as the outputs of eceiving boad IEEJ Jounal IA, Vol5, No3, 06

7 Isolation System fo Gate Dives of Medium-voltage Invete Keisuke Kusaka et al Fig 3 Output voltage chaacteistic of the poposed isolation system The output voltage inceases with an incease in load esistance Fig 5 Measued efficiency chaacteistic of the poposed system The same esistance loads ae connected to all of the eceiving boads as loads Fig 4 Output powe chaacteistic of the poposed isolation system # The othe boads obtained DC voltages, similaly In theoy, the input voltage of v in 6 is 90 degees phase lead to the invete output voltage v inv accoding to Eq ( Howeve the phase diffeence between these voltages is smalle than theoetical calculation It is caused by the eo between the esonance fequency of each boad and the tansmission fequency because the ceamic capacitos have lage toleances on capacitances In ode to ovecome this poblem, highaccuacy capacitos with low tempeatue coefficient should be used Figues 3 and 4 show the output voltage and output powe chaacteistic of the poposed isolation system Each output voltage inceases gadually with an incease in load esistance The output voltages of the eceiving boads # and #5 ae highe than the othes because the coupling coefficients ae appoximately twice the values of the othes The diffeent coupling coefficientsaecausedby thepositionalelationship of the eceiving boads Fo this eason, the output powe is also diffeent with each boad Because the output voltage depends on the load, voltage egulatos ae necessay in the gate dive cicuits At light load, the output voltage is too low to dive the voltage egulatos Thus, it is necessay to consume powe above a cetain level in the gate dive cicuit Figue 5 epesents the measued total efficiency of the poposed system The total efficiency is defined by Eq (, whee P in is the input DC powe of the isolation system The total efficiency is the atio of the input powe and the sum of the output powe fo all of the eceiving boads Note that the same esistance loads ae connected to all of the eceiving boadsasaload η = Fig 6 P out(n n=,,,6 Expeimental setup with gate dives P in 00 ( The maximum efficiency is 469% at an output powe of 66 W In the isolation system fo a medium-voltage invete, low efficiency can be acceptable because the powe loss in the isolation system is consideably smalle than the ated powe of a medium-voltage invete (ie, MW Thus, the isolation system is designed to give pioity to the isolation pefomance ove the efficiency 43 Opeation with Gate Dives In this subsection, the pototype with the gate dives is tested Figue 6 shows the expeimental setup fo the expeiments of the poposed isolation system with the gate dives The gate dives (which ae opeated at a switching fequency of 0 khz at gate-emitte voltages of ±5 V and the IGBTs (C ge = 800 pf ae connected as a load Note that DC/DC convetes ae connected as voltage egulatos at the font end ofthegatedives TheDC/DC convetes output voltages of ±5 V Moeove, photocouples ae used in ode to dive the IGBTs despite the deficient isolation distance because the isolation of the PWM signal is not a main topic of this pape Figue 7 shows the opeation wavefoms with the IGBTs Even if the gate dives and IGBTs ae connected as a load, the opeation system achieves wieless powe tansfe beyond an ai gap of 50 mm Fom the expeimental esults, it is confimed that the poposed system can be used as an isolation system fo a medium-voltage invete 5 Conclusion A conventional galvanic isolation system fo a gate dive IEEJ Jounal IA, Vol5, No3, 06

8 Isolation System fo Gate Dives of Medium-voltage Invete Keisuke Kusaka et al (a Gate-emitte voltage with poposed isolation system (b Expanded opeation wavefoms of (a Fig 7 Opeation wavefoms of the poposed isolation system with the gate dives supply with PCBs has been developed Howeve, the cost eduction of the conventional system is limited because the tansmitting side tansmits powe to only one eceive In this pape, the equivalent cicuit of the multiple gate dive supplies using PCBs and esonant conditions wee discussed fo when the numbe of eceives inceases fom one to multiple The isolation system tansmits powe fom one tansmitting boad to six eceiving boads Due to this chaacteistic, the cost of the gate dive supplies can be deceased Fistly, an equivalent cicuit model was deived and evaluated based on the equivalent cicuit of the epeating coil system It was confimed that the F-paametes of the equivalent cicuit, which has six magnetizing inductance in seies in the tansmitting side, shows good ageement with the analysis esults of 3-D electomagnetic analysis The esonance conditions ae deived based on the intoduced equivalent cicuit Then, the isolation system was expeimentally demonstated Finally, the expeimental esults showed that the pototype tansmits powe beyond an ai gap of 50 mm using esonance Moeove, the isolation system achieves a maximum efficiency fom an input DC to output DC of 469% at a summed output powe of 66 W Refeences ( N Hatti, Y Kondo, and H Akagi: Five-Level Diode-Clamped PWM Convetes Connected Back-to-Back fo Moto Dives, IEEE Tans on Industy Applications, Vol44, No4, pp68 76 (008 ( N Hatti, K Hasegawa, and H Akagi: A 66-kV Tansfomeless Moto Dive Using a Five-Level Diode-Clamped PWM Invete fo Enegy Savings of Pumps and Blowes, IEEE Tans on Powe Electonics, Vol4, No3, pp (009 ( 3 K Sano and T Masahio: A Tansfomeless D-STATCOM Based on a Multivoltage Cascade convete Requiing No DC Souces, IEEE Tans on Powe Electonics, Vol7, No6, pp (0 ( 4 I Shigenoi and H Akagi: A Bidiectional Isolated DC-DC Convete as a Coe Cicuit of the Next-Geneation Medium-Voltage Powe Convesion System, IEEE Tans Powe Electonics, Vol, No, pp (009 ( 5 S Dieckehoff, S Benet, and D Kug: Powe Loss-Oiented Evaluation of High Voltage IGBTs and Multilevel Convetes in Tansfomeless Taction Applications, IEEE Tans Powe Electonics, Vol0, No6, pp (005 ( 6 Intenational Electotechnical Commission (IEC: Adjustable speed electical powe dive systems Pat 5-: safety equiements Electical, themal and enegy, IEC (007 ( 7 C Maxgut, J Biela, JW Kola, R Steine, and PK Steime: DC-DC Convete fo Gate Powe Supplies with an Optimal Ai Tansfome, in Poc Applied Powe Electonics Confeence and Exposition 00, pp (00 ( 8 S Nagai, N Negoo, T Fukuda, N Otsuka, H Sakai, T Ueda, T Tanaka, and D Ueda: A DC-isolated gate dive IC with dive-by-micowave technology fopowe switching devices, in Poc Intenational Solid-State Cicuits Confeence 0, pp (0 ( 9 S Nagai, T Fukuda, N Otsuka, D Ueda, N Negoo, H Sakai, T Ueda, and T Tanaka: A one-chip isolated gate dive with an electomagnetic esonant couple using a SPDT switch, in Poc 4th IEEE Intenational Symposium on Powe Semiconducto Devices and ICs 0, pp73 76 (0 (0 S Nagai, N Negoo, T Fukuda, H Sakai, T Ueda, T Tanaka, N Otsuka, and D Ueda: Dive-by-Micowave technologies fo isolated diect gate dives, in Poc IEEE Micowave Wokshop Seies on Innovative Wieless Powe Tansmission: Technologies, Systems, and Applications 0, pp67 70 (0 ( M Ishigaki and H Fujita: A Resonant Gate-Dive Cicuit fo Fast High- Voltage Powe Semiconducto Devices with Optical Isolation of Both Contol Signal and Powe Supply, IEEJ Tans IA, Vol9, No3, pp (009 (in Japanese ( R Steine, PK Steime, F Kisme, and JW Kola: Contactless Enegy tansmission fo an Isolated 00 W Gate Dive Supply of a Medium Voltage Convete, in Poc Annual Confeence of the IEEE Industial Electonics Society 009, pp (009 (3 A Kaalis, JD Joannopoulos, and M Soljacic: Efficient Wieless nonadiative mid-ange enegy tansfe, Annals of Physics, Vol33, No, pp34 48 (007 (4 SYR Hui, YX Zhong, and CK Lee: A Citical Review of Recent Pogess in Mid-Range Wieless Powe Tansfe, IEEE Tans on Powe Electonics, Vol9, No9, pp (0 ( 5 M Budhia, GA Covic, and JT Boys: Design and Optimization of Cicula Magnetic Stuctues fo Lumped Inductive Powe Tansfe Systems, IEEE Tans on Powe Electonics, Vol6, No, pp (0 ( 6 T Imua and Y Hoi: Maximizing Ai Gap and Efficiency of Magnetic Resonant Coupling fo Wieless Powe Tansfe Using Equivalent Cicuit and Neumann Fomula, IEEE Tans on Industial Electonics, Vol58, No0, pp (0 ( 7 S Lee and RD Loenz: Development and Validation of Model fo 95%- Efficiency 00-W Wieless Powe Tansfe Ove a 30-cm Ai-gap, IEEE Tans on Industy Applications, Vol47, No6, pp (0 (8 T Nakanishi and J Itoh: Evaluation of Contol Methods fo Isolated Theephase AC-DC convete using Modula Multilevel Convete Topology, in Poc Intenational Enegy Convesion Congess and Exhibition Asia 03, pp5 58 (03 (9 Z Tiefu, W Jun, AQ Jun, and A Agawal: Compaisons of SiC MOS- FET andsiigbtbasedmoto Dive Systems, in Poc 4nd IEEE Industy Applications Society Annual Meeting 007, pp (007 (0 Infineon: Datasheet of EiceDRIVER ED300C7-S (03 ( CT-CONCEPT Technologie GmbH: Datasheet of EiceMELTER SD- 300C7 (03 ( T Imua: Equivalent Cicuit fo Repeate Antenna fo Wieless Powe Tansfe via Magnetic Resonant Coupling Consideing Signed Coupling, in Poc 6th IEEE Conf On Industial Electonics and Applications 0, pp (0 (3 D Ahn and S Hong: A Study on Magnetic Field Repeate in Wieless Powe Tansfe, IEEE Tans on Industial Electonics, Vol60, No, pp (03 3 IEEJ Jounal IA, Vol5, No3, 06

9 Isolation System fo Gate Dives of Medium-voltage Invete Keisuke Kusaka et al Keisuke Kusaka (Student Membe eceived his BS and MS degees in electical, electonics and infomation engineeing fom Nagaoka Univesity of Technology, Niigata, Japan in 0 and 03, espectively He is cuently a PhD candidate at Nagaoka Univesity of Technology, Niigata, Japan His eseach inteests include an inductive powe tansfe and a highfequency powe convesion He is a membe of the Institute of Electical Enginees of Japan, the Institute of Electical and Electonics Enginees and the Society of Automotive Enginees of Japan Koji Oikawa (Membe eceived his MS and PhD degees in electical, electonics and infomation engineeing fom Nagaoka Univesity of Technology, Niigata, Japan in 00 and 03, espectively Since 03, he has been woking at Nagaoka Univesity of Technology as a postdoctoal fellowship He is a membe of IEEE and IEEJ His eseach inteests include powe convesion system especially DC-DC convetes and high fequency techniques fo powe convetes Isamu Hasegawa (Non-membe is cuently a Powe Electonics R&D Enginee with the MEIDENSHA CORPORA- TION Kazunoi Moita (Membe is cuently a Powe Electonics R&D Enginee with the MEIDENSHA CORPORATION Jun-ichi Itoh (Membe eceived his MS and PhD degees in electical and electonic systems engineeing fom Nagaoka Univesity of Technology, Niigata, Japan in 996 and 000, espectively Fom 996 to 004, he was with Fuji Electic copoate Reseach and Development Ltd, Tokyo, Japan Since 004, He has been with Nagaoka Univesity of Technology as an associate pofesso He eceived the IEEJ academic pomotion awad (IEEJ Technical Development Awad in 007 and the Isao Takahashi powe electonics awad in 00 His eseach inteests include matix convetes, DC/DC convetes, powe facto coection techniques and moto dives He is a membe of the Institute of Electical Enginees of Japan and the Society of Automotive Enginees of Japan Takeshi Kondo (Non-membe is cuently a Powe Electonics R&D Enginee with the MEIDENSHA CORPORATION 4 IEEJ Jounal IA, Vol5, No3, 06