Analysis and Design of a 1MHz LLC Resonant Converter with Coreless Transformer Driver

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Aubrey Pope
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1 Analysis and Design of a MHz C Resonant Convete with Coeless Tansfome Dive Mingping Mao, Dimita Tchobanov, Dong i 3, Matin Maez.,Tongji Univesity, Siping Rd 39, 9 Shanghai -China., Faunhofe Institute of Integated Systems and Device Technology, Schottkyst., 958 Elangen Gemany. 3, Nanjing Univesity of Aeonautics and Astonautics, Yudaost. 9, 6 Nanjing China. Tobias Gebe 4, Geald Deboy 4, eo oenz 5. 4, Infineon Technologies Astia AG, Villach, Austia. 5, Infineon Technologies China Co. td., Pudong, China Abstact In this pape, the analysis and design of a MHz C esonant convete is pesented. Zeo-voltage switching (ZVS) of the pimay MOSFETs (Infineon) and zeo-cuent switching (ZCS) of the ectifie diodes ae guaanteed ove the entie opeation ange, which damatically educe the switching loss and impove EMI pefomance. In addition, the low voltage stesses of MOSFETs and the ectifie diodes allow the designe to use the devices with bette conduction pefomance. The detailed design method fo the C esonant tank paametes is pesented in this pape, which fully guaantees the ZVS conditions. An integated dive solution is implemented by a novel half bidge dive IC EDI-F (Infineon) employing coeless tansfome (CT) technology. Finally, a MHz 5W C esonant convete pototype is implemented to veify the opeational pinciples and design method of the poposed convete. The developed pototype can opeate with a wide input voltage ange of 5-4V with maximum 9.7% efficiency at 4V and 5W output. Theefoe, the poposed convete is suitable fo high efficiency and high powe density application such as CD and PDP TV powe module. Keywods: C esonant convete, ZVS, quality facto Intoduction DC/DC convete with high powe density and high efficiency is inceasingly equied, e.g., in CD and PDP application. Compaed to conventional PWM convetes, which suffes fom deceased efficiency and deteioated EMI poblem at high switching fequency, esonant convete is a good altenative due to its well known advantages of high efficiency, high switching fequency and high powe density [][]. In this pape, a MHz C esonant convete suitable fo high efficiency and high powe density applications is analysed and implemented. Fistly, in the oveall designed opeation anges, the pimay MOSFETs ae tuned-on unde ZVS condition, and the seconday ectifie diodes ae tuned-on and tuned-off unde ZCS condition. Hence high switching fequency and high powe density ae easonable. Secondly, the pimay MOSFETs and the seconday ectifie diodes have low voltage stesses clamped by the input and output voltages, espectively. And so the designe can use the devices with bette conduction pefomance, and consequently smalle conduction loss can be achieved. Thidly, optimal design can be ealised at the nomal opeation point, moeove, opeation with a wide input voltage ange is achieved. Fouthly, the two esonant inductos of the C esonant tank can be easily integated in one magnetic coe without additional inducto, hence the powe density can be futhe inceased. In this pape, a detailed quantitative analysis of the C topology is povided, as well as the design method fo the C esonant tank paametes, which guaantee the ZVS condition and optimised opeational efficiency. To ealize an integated solution, a novel IC EDI-F employing coeless tansfome (CT) technology is used to dive the half bidge. The basic pinciple of CT is the implementation of a micoplana tansfome embedded within the semiconducto pocess. High insulation capability, no ageing, small package size, easy integation of additional logic functions, and cost effectiveness ae povided by EDI-F[6]. Also, The tansfome coe selection and the

2 contolle implementation ae biefly pesented in this pape. Opeation Pinciple The schematic of a half-bidge C esonant convete is shown in Fig.. The elements that make the esonant tank ae the leakage inductance, the magnetizing inductance m of the tansfome and the esonant capacito C. V dc Coeless Tansfome Dive IC EDI-F D C D m Fig. C esonant convete The DC chaacteistic of C esonant invete is shown in Fig.. Thee ae two citical esonant fequencies f and f ( f < f). The bigge one f is detemined by the esonant capacito C and leakage inductance. The othe smalle one f is detemined by C, and m. At nomal opeation condition, i.e. 4V dc input, the opeation point should be placed nea the esonant fequency f as shown in Fig., whee the voltage gain is unity and its load independent chaacteistic is obtained. Duing hold up time, input voltage dops, switching fequency is educed to egulate the output voltage [][3]. Gain of C esonant invete f f D 3 D 4 C o R load Nomalized switching fequency Incease l 5V dc input Nomal opeation point 4V dc input Fig. DC gain of C esonant invete Fom Fig., in ode to guaantee the output voltage egulation ove the entie ange of input dc l at full load is voltage, the loaded quality facto equied to be bigge than a citical value l _min, which guaantee the equied voltage gain and ZVS condition within the vaiation ange of load and input voltage. 3 Design Consideation and Pactical Implementation C esonant convete is to be used as one stage of font end AC/DC convete. In ode to povide the hold up time capability and decease the input capacito volume, the input voltage ange of the convete is to be designed widely fom 5V to 4V. 3. Resonant Paametes Design The voltage gain of the esonant tank can be descibed as equation () using the fist hamonic appoximation appoach. M f A f ( + A) ( ( ) ) + ( ) () f A+ With the following paametes definition: The atio of the inductance: A m () The cone fequency: ω π f (3) ( + m) C The chaacteistic impedance: + m Z ω( + m) (4) ωc C The equivalent input esistance of the tansfome cente-tapped ectifie: 8N R R (5) i π load The loaded quality facto at the cone fequency f : R + R (6) Z i m i C Due to the load independent chaacteistic at the maximum esonant fequency f, the switching fequency at nomal opeation point is specified as f : fnomal _ switch f (7) π C

3 Using (), the maximum switching fequency f can be calculated as (8), which occus at maximum input voltage and zeo load: M zeoload fnomal _ switch (8) / ( + A) ( + A ) f The minimal voltage gain is equied at maximum input DC link voltage: Vout Mmin N (9) V dclink _max et M zeoload M min, and assume the maximum switching fequency f is specified as a cetain value bigge than f nomal _ switch, fo example.4mhz, and the maximum possible input voltage as 45V, and then the inductance atio A can be calculated fom equation (8)(9): f _ A nomal switch () M min f The next impotant step is to check what is the minimal equied quality facto, which guaantee the ZVS condition is still available at all the allowed opeational conditions. The input impedance of the esonant cicuit is given by: jωr m i Z + jω + () jωc jωm + Ri The esonant fequency fesonant is defined as the fequency at which the phase shift angleψ of Z is zeo, which constitutes the bounday conditions between capacitive and inductive load. Fo > fesonant, ψ > and the esonant cicuit epesents an inductive load, which is ecommended fo the ZVS conditions fo MOSFETs [- 3]. Fom equation (), assuming the imaginay pat of Z is zeo, the nomalized esonant fequency is found to be: ( + A) l ( + A) + l ( + A) + 4 l ( + AA ) fesonant () f A As l, fesonant ( + A) A. Fo a fixed value of A given by () and loaded quality facto l, the actual nomalized switching fequency should be highe than fesonant, which guaantee the inductive load and consequently the ZVS condition. Fom equation (), the plots of against l at specified values of M esonant _tank ae obtained as shown in Fig.3. The bounday condition given by () is also plotted in Fig.3, and the aea beyond the bounday condition is desied fo ZVS condition. The maximum equied voltage gain, assuming minimal input dc link voltage 5V duing the holdup time, is obtained efeing to (9): M.55 (3) Requied Nomalized switching fequency M.93 M M. M.3 M oaded quality facto Bounday condition Fig.3 Selection of loaded quality facto Fom Fig.3, the minimal equied loaded quality facto can be diectly and appoximately obtained: l_min_ equied.3 (4) The shadow aea shown by Fig.3 is the designed opeation ange, which guaantee both the ZVS condition and the equied voltage gain within the vaiation ange of load and input dc link voltage. Anothe impotant conditions fo ZVS is that the tun off cuent should be big enough to dischage junction capacitos within the dead time. sin C V oss _ effective dc _ link Iesonant ψ (5) tdead Conside the ms esonant tank cuent equals to: P I esonant cosψ in V dc _ link π (6) Thus the following expession can be deived by (5) and (6): Coss _ effective Vdc _ link tgψ (7) π tdead Pin Whee Coss _ effective is a fixed effective output capacitance that gives the same chaging time as the output capacitance of a MOSFET while V DS is ising fom to 4V. Fom the input impedance equation (), tgψ can be given as functions of at fixed values of l :

4 A f tgψ l f A+ f f + l ( + A) ( ) (8) At nomal opeation condition, the elationship between actual tgψ and l is tgψ A ( + A) l (9) Using (8) and (9), and assuming C oss _ effective 4pF (Cool- Mos_SPP6N5C3), t ns, P 7W dead and Vdc _ link Vdc _ link _ nomal 4V, then, leaving some magin, the minimal equied loaded quality facto is obtained as l_min_ equied., which insues tgψ fully meets the equiement given by (7). In the actual expeiment, the equiement given by (7) can also be met by adjusting the dead time t dead. The efficiency of the C invete can be appoximately obtained as: η f () + + l ( A) R + i f switch Assuming the equivalent conduction loss esistance is constant, the maximum efficiency occus at f () l + A The efficiency optimisation is focused on nomal opeation point, 4V DC link input, whee the switching fequency is load independent and equals to f. Efficiency of C invete at 4V input esonant Fig.4 C invete efficiency oaded quality facto in Fom Fig.4, if the loaded quality facto fom to 3 fo full load condition is ealized, then the maximum efficiency fo C invete at full load and 4V input conditions can be obtained. The final conclusion can be given, taking some magin, l_min_ equied is selected. The component values of the esonant cicuit can be given as: l C f R Ri _min π f l π i _min + A m () + A 3. Tansfome Coe Selection The esonant convete can significantly educe the switching losses, thus impove the powe convesion efficiency. Howeve, at highe switching fequency, the tansfome coe exhibits inceased magnetic loss, which could offset the educed switching losses. Accodingly, many attempts have been made by coe manufactues to advance the state-of-the-at in the powe feite technology. The type of feite mateial chosen will influence the coe losses at given opeating conditions. N49 feite coe poduced by EPCOS has been selected fo its low magnetic powe losses, and its high fequency ange vaies fom 3kHz to MHz, and coe tempeatue up to C. Finite element analysis (FEA) is used to define the tansfome winding stategy, and consequently the expected leakage inductance and magnetizing inductance can be ealised. At the same time, the ac esistance also can be optimised. 3.3 Half Bidge Dive To educe the volume of the convete, integated dive solution is implemented, IC EDI-F (Infineon) employing coeless tansfome (CT) technology is used to dive the half bidge. The basic pinciple of CT is the implementation of a micoplana tansfome embedded within the semiconducto pocess. Compaed to othe conventional level shifting technologies based on optocouples, discete tansfomes o level shiftes, EDI-F with CT technology simultaneously featues high and safe isolation, low cost and no degadation ove time [6]. The EDI-F contains two dives fo an IGBT o MOSFET half-bidge, and the high side is galvanicly isolated fom the low side pat though a coeless tansfome system.

The integated opeational amplifie and compaato ae suitable to detect ove cuent and/o shot cicuit cuent. Extenal push-pull cicuit is used to enhance its dive capability at MHz switching fequency. 3.

MC3467 is a high pefomance esonant mode contolle designed fo zeo voltage switching DC/DC convete applications that utilize fequency modulated constant deadtime contol.

5 The integated opeational amplifie and compaato ae suitable to detect ove cuent and/o shot cicuit cuent. Extenal push-pull cicuit is used to enhance its dive capability at MHz switching fequency. 3.4 Contolle IC Contolle IC-MC3467 is used to implement the output voltage egulation against vaiations of the load and input voltage. MC3467 is a high pefomance esonant mode contolle designed fo zeo voltage switching DC/DC convete applications that utilize fequency modulated constant deadtime contol. 4 Expeiment Results To veify the opeational pinciples of the poposed convete, a 5W pototype is implemented as shown in Fig.5. Fig.7 MOSFET ZVS 5% Full load To evaluate the pefomance of the feedback contol, the load step esponse of the C esonant convete has been analysed. Fig.8 shows the esponse of the convete to a positive step of the load cuent. And cuent step slew ate.4a/us.fig.9 shows the esponse of the convete to a negative step of the load cuent. Fig.5 C esonant convete pototype Fig.6 and Fig.7 show the key wavefoms at fullload and 5%full load with an input voltage of 4V. Ch3 wavefom is the dive signal fo MOS- FET (CoolMos), Ch wavefom is the voltage acoss MOSFET. It s clea that MOSFET is tuned-on unde ZVS condition ove the entie ange of load. Fig.8 oad Vin4V fom 3%full load to full load Fig.6 MOSFET ZVS Full load Fig.9 oad Vin4V fom full load to 3%full load Nomally, C convete opeates between 35V to 4V input voltage. In Fig., efficiency measuements have been pefomed at these diffeent opeation points; the developed C esonant convete pototype exhibits high-efficiency in the nomal 4V opeation point.

6 Efficiency Efficiency Measuement 4V 375V 35V oad (%) Fig. Efficiency measuement esults Duing the hold up time, the input dc voltage is allowed to dop to 5V, output voltage of C esonant convete can still be egulated, howeve, it opeates fa away fom the esonant point, which means the convete is less efficient, nevetheless it only lasts fo about ms and will not cause exta themal poblem. [] Yang, B.: Topology Investigation fo Font End DC/DC Powe Convesion fo Distibuted Powe System. PhD thesis, Viginia Polytechnic Institute and State Univesity, 3 [3] Yang, B., ee, F.C., Zhang, A.J., and Huang, G.: C esonant convete fo font end DC/DC convesion. Poc. 7th Annual IEEE Confeence on applied powe electonics,, pp.8- [4] Simone, S.D., Adagna, C., Spini, C. and Gattavai, G.: Design-oiented steady state analysis of C esonant convetes based on FHA, Intenational Symposium on Powe Electonics, Electical Dives, Automation and Motion, 6, pp.-7 [5] u, B., iu, W., iang, Y., ee, F.C., and Wyk, J.D.: Optimal Design Methodology fo C Resonant Convete. Poc. th Annual IEEE Confeence on applied powe electonics, 6, pp [6] Muenze, M., Infineon Technology (Eupec).: Coeless Tansfome a New Technology fo Half Bidge Dive IC s. PCIM Nuembeg, 3. 5 Conclusion In this pape, a MHz C esonant convete is poposed fo high efficiency and high powe density application. The opeational pinciple of the poposed convete is analysed, and coesponding calculation esult is given. The design method fo the esonant tank paametes is also detailed. The half bidge dive IC and the tansfome coe selection fo MHz switching fequency have also been discussed, too. The ZVS of MOSFETs is guaanteed ove the entie opeation ange. To futhe confim its opeation and developed design method, a 4V/5W pototype is implemented, ZVS is ealised and high efficiency up to 9.7% is also achieved. The C esonant convete is an excellent altenative in high efficiency and high powe density application. 6 Acknowledgment The authos wish to acknowledge the funding of the Geman Ministy of Education and Reseach (BMBF) and all patnes fom Infineon Technologies Company and Faunhofe Institute of Integated Systems and Device Technology. 7 Refeences [] Kazimieczuk, M.K., and Czakowski, D.: Resonant Powe Convetes (John Wiley and Sons, 995), pp

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