Application-Specific Integrated Circuits (ASICs)

Transcription

1 Application-Specific Integrated Circuits (ASICs) 1 Gyan Prakash Pal, 2 Manishankar Gupta 1,2 Assistant Professor, Electronics & Communication Engineering Department 1,2 Shanti Institute of Technology, Meerut Abstract Application specific integrated circuits (ASICs) are usually non standard integrated circuits that have been designed for a specific use or application. ASIC contains a very large part of the electronics circuits significantly integrated on a single IC. So Large No of components are found in one ASIC. It means that cost of ASICs Design is usually very high. Despite the High cost, ASICs are cost effective for applications where volume of production is very high. Due to improvement in Design Techniques, size of ASIC has increased from 5000 gates to over 100 million. 1. Architecture Hierarchy of ASIC highest of full custom ASIC. Productivity is typically only 6 to 17 transistors per Day 1.2 Semi custom ASICs ASICs, for which all of the logic cells are predesigned & some (possible all) of the mask layers are customized are called semi custom ASICs. Using the predetermined cells from a cell library makes the design, much easier. It has mixed analog/digital ASIC. Two types of semi custom ASICs are: i) Standard cell-based ASICs ii) Gate-array-based ASICs 1.3 Standard-cell-Based ASICs A cell-based ASIC uses predesigned logic cells (e.g. AND gates, OR gates, multiplexers, and flip-plops,) known as standard cells, also pronounced as Sea Bick or CBIC. The CBIC are built of rows of standard cells like a wall built of bricks. The standard cell areas may be used in combination with microcontrollers or even microprocessors. A cell- based ASIC (CBIC) die with a single standard cell area (a flexible block) together with four fixed blocks 1.1 FULL CUSTOM ASICs Every transistor is designed & drawn by hand, usually the only way to design analog portions of ASICs. A full custom ASIC is one which includes all logic cells & mask layers that are customized. A microprocessor is an example of full- custom IC, gives the highest performance but the longest designing time & is very expensive, used to design very high performance systems. In a full custom ASIC an engineer designs some or all parts of the logic cells, circuits or layouts. This means the designer avoids the use of pretested & predesigned cells. It is because the existing cell libraries are not fast enough or the logic cells are not small enough or consume too much power. However, the NRE cost is The ASIC designer defines only the placement of the standard cells & the interconnection in a CBIC. However the standard cells can be placed anywhere on 40

2 the silicon; it means that all the mask layers of a CBIC are customized & are unique to a particular customer Benefits of CBICs are that designers save time, money and reduce risk by using a predesigned & pretested cell library. During the design of the cell library each & every transistor in every standard cell can be chosen to maximize speed or minimum area. 1.4 Gate array-based ASICs In a gate-array based ASIC, the transistors are predefined on the silicon wafer. The predefined pattern of transistors is called the base array. The smallest element that is replicated to make the base array is called the base or primitive cell. Fabrication is done with hard wired metal connection layer, this result in fast operation, no redesign flexibility, also called as masked gate array (MGA). The designer chooses from a gatearray library of predesigned & pretested logic cells. The logic cells in a gate array library are often called MACROS. 2. Types of MGA ASICs There are three types of Gate array based ASICs 1. Channeled gate arrays 2. Channel less gate arrays 3. Structured gate arrays 2.1 Channeled gate array In a channeled gate array space is left between the rows of transistors for wiring. It is similar to a CBIC as both uses the rows of cells separated by channels used for interconnect. difference between a channel less gate array & channeled gate array is that there are no predefined areas set aside for routing between cells on a channel less gate array, Instead we route only at the top of the gate array devices. When we use an area of transistors for routing in a channel less array, we do not make any contacts to the devices lying underneath; we simply leave the transistors unused. A channel less - gate array die 2.3 A structured- Gate array This design combines some features of CBICs & MGAs, also known as an embedded gate array or structured gate array. One of the limitations of the MGA is the fixed gate-array base cell. This makes the implementation of memory difficult & inefficient. A structured-gate array dies A channelized-gate array dies 2.2 A channel less gate array Only interconnects are customized, the interconnect uses predefined spaces between rows of base cells. The key 2.4 Features of structured gate array An embedded gate array improves the implementation of memory & increased performance of a CBIC but with the lower cost & faster turnaround. The only Disadvantage of an embedded gate array is that the embedded function is usually fixed. For example, if an 41

3 embedded gate array contains an area set aside for a 32 k-bit memory, but we need only a 16 k-bit memory, then we have to waste half of the embedded memory function. 3. Programmable Logic Devices Programmable logic devices (PLDs) are standard ICs that are available in standard configurations. However, PLDs may be configured or programmed to create a part customized to a specific application & so they also belong to the family of ASICs. It requires no customized mask layers or logic cells, but gives fast design. A single large block of programmable interconnect is used. A matrix of logic macro cells that usually consist of programmable array logic are followed by a flip-flop or latch. The simplest type of Programmable IC is a Readonly memory (ROM/PROM). An electrically programmable ROM or EPROM uses programmable MOS transistors whose characteristics are changed by applying a high voltage. One can erase an EPROM either by using another high voltage (an electrically erasable PROM /EEPROM) or by exposing the device to UV light. (UV-erasable PROM/UVPROM) 4. Field Programmable Gate arrays (FPGAs) Design is based on programming of the basic logic cells & their interconnection as shown. The core is a regular array of programmable basic logic cells that can implement combinational as well as sequential logic (flip-flops). A matrix of programmable interconnect surrounds the basic logic cells and Programmable I/O cells surrounds the core. Designing usually takes only few hours but speed is slow due to p/o resistance & capacitance of the program switch. 5. Features of ASICs There are some features of ASICs: 1. Low (NRE) cost 2. Low power consumption 3. Less complex (As only few layers to fabricate) 4. High performance 6. ASIC Drawbacks There are some drawbacks of ASICs: Inflexible design Deployed Systems cannot be upgraded Mistakes in product development are costly Updates requires a redesign Complex & expensive development tool 7. Comparison FPGAs are approximately 3 times less dense & 5 times more expensive than their mask programmed gate array equivalents. Production volume: For low production volumes the NRE costs are the dominant factor, while for high production volumes the cost per chip is the dominant factor Logic Design comparison 4.1 Types of FPGAs 8. Design Flow of ASIC 1. Design entry: Using a hardware Description language (HDL) or Schematic entry 2. Logic synthesis: Produces a net-list of corresponding logic cells & their connections 3. System partitioning: Divide a large system into ASIC sized pieces 42

4 4. Pre-layout simulation: Check to see if the design functions correctly 5. Floor planning: Arrange the blocks of the net-list on the chip 6. Placement: Decide the locations of cells in a block 7. Routing: Make the connections between cells & blocks 8. Extraction: Determine the resistance & capacitance of the interconnect 9. Post layout simulation: It is used to check to see whether the design still works with the added loads of interconnect or not. 9. Conclusion Each of the ASIC Design type occupies a vital role in IC system market place. Full custom Designs are appropriate for high volume markets where the Large NRE cost can be neglected over a high production volume. Full custom Design typically consume less power & operates at higher speeds than the other design styles. But In case of FPGA, It offers low NRE cost & a very low production time. However, they have low speed of operation, low logic density & high cost per chip. References: [1] Ian Kuon, Jonathan Rose, Measuring the Gap between FPGAs and ASICs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 2, pp , February 2007 [2] A. Albert Raj, T. Latha, VLSI Design, PHI Publication [3] Michael John Sebastian Smith, Application-Specific Integrated Circuits, Pearson Education [4] Romya Bhatnagar, Malik M. Anwer, Manish Design and Analytical Comparison of Various Controllers Used in PWM Inverter, pp , IJSRET Volume 1 Issue 3, June 2012 [5] Gyan Prakash Pal, Sadhana Pal, Amit Kumar Gupta, Vinayak Yadav Internal Scan Test Methodology of Sequential Circuits, pp , IJSRET Volume 1 Issue 5, August 2012 [6] Romya Bhatnagar, Malik M. Anwer, Manish Design and Analytical Comparison of Various Controllers Used in PWM Inverter, pp , IJSRET Volume 1 Issue 3, June 2012 [7] Gyan Prakash Pal, Sadhana Pal, Amit Kumar Gupta, Vinayak Yadav Internal Scan Test Methodology of Sequential Circuits, pp , IJSRET Volume 1 Issue 5, August 2012 [8] Dr. Balkeshwar Singh, Role of Industrial Robots in Lean Manufacturing System, pp , IJSRET Volume 1 Issue 5, August 2012 [9] Om Prakash, R.K.Prasad, Dr.B.S.Rai, Akhil Kaushik Analysis and Design of Logic Gates Using Static and Domino Logic Technique, pp , IJSRET Volume 1 Issue 5, August 2012 [10] Ching-Won Fong, Yang Ku Hong PIC Microcontroller: CCP modules, pp , IJSRET Volume 1 Issue 9, December 2012 [11] Om Prakash, Dr.B.S.Rai, Dr.Arun Kumar Design and analysis of low power energy- efficient, domino logic circuit for high speed applications, pp- 1-4, IJSRET Volume 1 Issue 12, March 2013 [12] Santhanayaki.T, Dr.K.R.Valluvan Identification of Sags and Swells Using PIC Microcontroller, pp , IJSRET Volume 1 Issue 12, March 2013 [13] Sunil Kumar Ojha,Subrato Howlader Low-Power CMOS SRAM Cell with Sleep Transistors to Control Leakage Currents, pp , IJSRET Volume 2 Issue 1, April 2013 [14] U.Palani, M.Sujith, P.Pugazhendiran Implementation of Memory Based Multiplication Using Micro wind Software, pp , IJSRET Volume 2 Issue 2, May 2013 [15] Namrata Gupta Designing of Full Adder Circuits for Low Power, pp , IJSRET Volume 2 Issue 4, July 2013 [16] Neeraj Kumar Mishra Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checking for 32 bit address Using HDLC Block pp , IJSRET Volume 2 Issue 5, August 2013 [17] Anisha babu Measurement and Evaluation of Side Channel Attack on Asynchronous S Box, pp , IJSRET Volume 2 Issue 5, August 2013 [18] Shivani Duggal, Ms.Preeti Arora Design of Shortest Path Algorithm Based on Adjacency Matrix Reduction with LEACH as Benchmark, pp , IJSRET Volume 2 Issue 5, August 2013 [19] Ramit Lala Modified Neural Networks for Face and Eye Recognition, pp- 6-11, IJSRET Volume 1 Issue 9, December

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