FAMILY PACKAGE TABLE PACKAGE TYPES UNIVERSAL SHUTDOWN CHANNELS MSOP PDIP SOIC TSSOP

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1 Wide Bandwidth... 1 MHz High Output Drive I OH ma at V DD 1.5 V I OL ma at.5 V High Slew Rate SR V/µs SR V/µs Wide Supply Range V to 16 V Supply Current ma/channel Ultralow Shutdown Mode I DD µa/channel Low Input Noise Voltage nv Hz Input Offset Voltage...6 µv Ultra-Small Packages 8 or 1 Pin MSOP (TLC8/1/2/3) description SLOS254E JUNE 1999 REVISED APRIL 26 Operational Amplifier The first members of TI s new BiMOS general-purpose operational amplifier family are the TLC8x. The BiMOS family concept is simple: provide an upgrade path for BiFET users who are moving away from dual-supply to single-supply systems and demand higher ac and dc performance. With performance rated from 4.5 V to 16 V across commercial ( C to 7 C) and an extended industrial temperature range ( 4 C to 125 C), BiMOS suits a wide range of audio, automotive, industrial, and instrumentation applications. Familiar features like offset nulling pins, and new features like MSOP packages and shutdown modes, enable higher levels of performance in a variety of applications. Developed in TI s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input impedance, low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum performance features of both. AC performance improvements over the TL8x BiFET predecessors include a bandwidth of 1 MHz (an increase of 3%) and voltage noise of 8.5 nv/ Hz (an improvement of 6%). DC improvements include an ensured V ICR that includes ground, a factor of 4 reduction in input offset voltage down to 1.5 mv (maximum) in the standard grade, and a power supply rejection improvement of greater than 4 db to 13 db. Added to this list of impressive features is the ability to drive ±5-mA loads comfortably from an ultrasmall-footprint MSOP package, which positions the TLC8x as the ideal high-performance general-purpose operational amplifier family. FAMILY PACKAGE TABLE DEVICE NO. OF PACKAGE TYPES UNIVERSAL SHUTDOWN CHANNELS MSOP PDIP SOIC TSSOP EVM BOARD TLC Yes TLC TLC Refer to the EVM Selection Guide TLC Yes (Lit# SLOU6) TLC TLC Yes + Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright 2 26 Texas Instruments Incorporated 1

2 SLOS254E JUNE 1999 REVISED APRIL 26 TLC8 and TLC81 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE SMALL OUTLINE (D) (DGN) C to 7 C 4 C to 125 C TLC8CD TLC81CD TLC8ID TLC81ID TLC8AID TLC81AID TLC8CDGN TLC81CDGN TLC8IDGN TLC81IDGN SYMBOL xxtiacw xxtiacy xxtiacx xxtiacz PLASTIC DIP (P) TLC8CP TLC81CP TLC8IP TLC81IP TLC8AIP TLC81AIP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC8CDR). TA C to 7 C 4 C to 125 C TLC82 and TLC83 AVAILABLE OPTIONS PACKAGED DEVICES SMALL MSOP OUTLINE (D) (DGN) SYMBOL (DGQ) SYMBOL TLC82CD TLC83CD TLC82ID TLC83ID TLC82AID TLC83AID TLC82CDGN TLC82IDGN xxtiadz xxtiaea TLC83CDGQ TLC83IDGQ xxtiaeb xxtiaec PLASTIC DIP (N) TLC83CN TLC83IN TLC83AIN This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC82CDR). xx represents the device date code. PLASTIC DIP (P) TLC82CP TLC82IP TLC82AIP TA C to 7 C 4 C to 125 C TLC84 and TLC85 AVAILABLE OPTIONS PACKAGED DEVICES SMALL OUTLINE (D) TLC84CD TLC85CD TLC84ID TLC85ID TLC84AID TLC85AID PLASTIC DIP (N) TLC84CN TLC85CN TLC84IN TLC85IN TLC84AIN TLC85AIN TSSOP (PWP) TLC84CPWP TLC85CPWP TLC84IPWP TLC85IPWP TLC84AIPWP TLC85AIPWP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC84CDR). For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at 2

3 SLOS254E JUNE 1999 REVISED APRIL 26 TLC8x PACKAGE PINOUTS TLC8 D, DGN, OR P PACKAGE (TOP VIEW) TLC81 D, DGN, OR P PACKAGE (TOP VIEW) TLC82 D, DGN, OR P PACKAGE (TOP VIEW) NULL IN IN+ GND SHDN V DD OUT NULL NULL IN IN+ GND NC V DD OUT NULL 1OUT 1IN 1IN+ GND V DD 2OUT 2IN 2IN+ TLC83 DGQ PACKAGE (TOP VIEW) TLC83 D OR N PACKAGE (TOP VIEW) TLC84 D OR N PACKAGE (TOP VIEW) 1OUT 1IN 1IN+ GND 1SHDN V DD 2OUT 2IN 2IN+ 2SHDN 1OUT 1IN 1IN+ GND NC 1SHDN NC V DD 2OUT 2IN 2IN+ NC 2SHDN NC 1OUT 1IN 1IN+ V DD 2IN+ 2IN 2OUT OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT TLC84 PWP PACKAGE (TOP VIEW) TLC85 D OR N PACKAGE (TOP VIEW) TLC85 PWP PACKAGE (TOP VIEW) 1OUT 1IN 1IN+ VDD 2IN+ 2IN 2OUT NC NC NC OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT NC NC NC 1OUT 1IN 1IN+ V DD 2IN+ 2IN 2OUT 1/2SHDN OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT 3/4SHDN 1OUT 1IN 1IN+ VDD 2IN+ 2IN 2OUT 1/2SHDN NC NC OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT 3/4SHDN NC NC NC No internal connection TYPICAL PIN 1 INDICATORS Pin 1 Printed or Molded Dot Pin 1 Stripe Pin 1 Bevel Edges Pin 1 Molded U Shape 3

4 SLOS254E JUNE 1999 REVISED APRIL 26 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V DD (see Note 1) V Differential input voltage range, V ID ±V DD Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : C suffix C to 7 C I suffix C to 125 C Maximum junction temperature, T J C Storage temperature range, T stg C to 15 C Lead temperature 1,6 mm (1/16 inch) from case for 1 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND. PACKAGE recommended operating conditions Supply voltage, VDD DISSIPATION RATING TABLE θjc ( C/W) θja ( C/W) TA 25 C POWER RATING D (8) mw D (14) mw D (16) mw DGN (8) W DGQ (1) W N (14, 16) mw P (8) mw PWP (2) W MIN MAX UNIT Single supply V Split supply ±2.25 ±8 Common-mode input voltage, VICR GND VDD 2 V Shutdown on/off voltage level Operating free-air temperature, TA Relative to the voltage on the GND terminal of the device. VIH 2 VIL.8 C-suffix 7 I-suffix V C 4

5 SLOS254E JUNE 1999 REVISED APRIL 26 electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT TLC8/1/2/3, 25 C TLC84/5 Full range 3 VIO Input offset voltage VDD = 5 V, µvv VIC = 2.5 V, TLC8/1/2/3A, 25 C VO O = 2.5 V, TLC84/5A Full range 2 RS = 5 Ω Temperature coefficient of input αvio 1.2 µv/ C C offset voltage IIO IIB Input offset current Input bias current VICR Common-mode input voltage RS = 5 Ω VOH High-level output voltage VIC = 2.5 V VOL Low-level output voltage VIC = 2.5 V IOS Short-circuit output current 25 C TLC8XC 1 pa VDD = 5 V, Full range TLC8XI 7 VIC = 2.5 V, VO = 2.5 V, 25 C 3 5 RS = 5 Ω TLC8XC 1 pa Full range TLC8XI 7 IOH = 1 ma IOH = 2 ma IOH = 35 ma IOH = 5 ma IOL = 1 ma IOL = 2 ma IOL = 35 ma IOL = 5 ma 25 C Full range to 3. to 3. to 3.5 to C Full range C Full range 3.5 V 25 C V Full range C C to 85 C 3 25 C Full range C Full range C V Full range.7 25 C C to 85 C Sourcing 25 C 1 Sinking 25 C 1 VOH = 1.5 V from positive rail 25 C 57 IO Output current VOL =.5 V from negative rail 25 C 55 Full range is C to 7 C for C suffix and 4 C to 125 C for I suffix. If not specified, full range is 4 C to 125 C..7 ma ma 5

6 SLOS254E JUNE 1999 REVISED APRIL 26 electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) (continued) AVD PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Large-signal differential voltage amplification VO(PP) = 3 V, RL = 1 kω 25 C 1 12 Full range 1 ri(d) Differential input resistance 25 C 1 GΩ CIC Common-mode input capacitance f = 1 khz 25 C 22.9 pf zo Closed-loop output impedance f = 1 khz, AV = 1 25 C.25 Ω CMRR Common-mode rejection ratio VIC = to 3 V, RS = 5 Ω ksvr 25 C 8 11 Full range 8 Supply voltage rejection ratio VDD = 4.5 V to 16 V, VIC = VDD /2, 25 C 8 1 ( VDD / VIO) No load Full range 8 IDD Supply current (per channel) VO = 2.5 V, No load 25 C Full range 3.5 Supply current in shutdown IDD(SHDN) mode (per channel) SHDN.8 V (TLC8, TLC83, TLC85) 25 C Full range Full range is C to 7 C for C suffix and 4 C to 125 C for I suffix. If not specified, full range is 4 C to 125 C. db db db ma µaa 6

7 SLOS254E JUNE 1999 REVISED APRIL 26 operating characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted) SR+ SR Vn PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Positive slew rate at unity gain Negative slew rate at unity gain Equivalent input noise voltage VO(PP) =.8 V, CL = 5 pf, 25 C 1 16 RL = 1 kω Full range 9.5 VO(PP) =.8 V, CL = 5 pf, 25 C RL = 1 kω Full range 1 f = 1 Hz 25 C 12 f = 1 khz 25 C 8.5 V/µs V/µs nv/ Hz In Equivalent input noise current f = 1 khz 25 C.6 fa / Hz AV = 1.2% VO(PP) = 3 V, THD + N Total harmonic distortion plus noise RL = 1 kω and 25 Ω, AV = 1 25 C.12% f = 1 khz AV = 1.85% t(on) Amplifier turnon time 25 C.15 µs t(off) Amplifier turnoff time RL = 1 kω 25 C 1.3 µs ts φm Gain-bandwidth product f = 1 khz, RL = 1 kω 25 C 1 MHz Settling time Phase margin Gain margin V(STEP)PP = 1 V, AV = 1, CL = 1 pf, RL = 1 kω V(STEP)PP = 1 V, AV = 1, CL = 47 pf, RL = 1 kω RL = 1 kω, RL = 1 kω, RL = 1 kω, RL = 1 kω,.1%.18.1%.1% 25 C %.39 CL = 5 pf CL = pf CL = 5 pf CL = pf Full range is C to 7 C for C suffix and 4 C to 125 C for I suffix. If not specified, full range is 4 C to 125 C. Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. 25 C 25 C µss db 7

8 SLOS254E JUNE 1999 REVISED APRIL 26 electrical characteristics at specified free-air temperature, V DD = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT TLC841/2/3, 25 C TLC84/5 Full range 3 VIO Input offset voltage VDD = 12 V µvv VIC = 6 V, TLC841/2/3A, 25 C VO O = 6 V, TLC84/5A Full range 2 RS = 5 Ω Temperature coefficient of input αvio 1.2 µv/ C C offset voltage IIO IIB Input offset current Input bias current VICR Common-mode input voltage RS = 5 Ω VOH High-level output voltage VIC = 6 V VOL Low-level output voltage VIC = 6 V IOS Short-circuit output current 25 C TLC8xC 1 pa VDD = 12 V Full range TLC8xI 7 VIC = 6 V, VO = 6 V, 25 C 2 5 RS = 5 Ω TLC8xC 1 pa Full range TLC8xI 7 IOH = 1 ma IOH = 2 ma IOH = 35 ma IOH = 5 ma IOL = 1 ma IOL = 2 ma IOL = 35 ma IOL = 5 ma 25 C Full range to 1. to 1. to 1.5 to C Full range C Full range 1.7 V 25 C V Full range C C to 85 C C Full range C Full range.5 25 C.4.52 V Full range.6 25 C C to 85 C Sourcing 25 C 15 Sinking 25 C 15 VOH = 1.5 V from positive rail 25 C 57 IO Output current VOL =.5 V from negative rail 25 C 55 Full range is C to 7 C for C suffix and 4 C to 125 C for I suffix. If not specified, full range is 4 C to 125 C..65 ma ma 8

9 SLOS254E JUNE 1999 REVISED APRIL 26 electrical characteristics at specified free-air temperature, V DD = 12 V (unless otherwise noted) (continued) AVD PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Large-signal differential voltage amplification VO(PP) = 8 V, RL = 1 kω 25 C Full range 12 ri(d) Differential input resistance 25 C 1 GΩ CIC Common-mode input capacitance f = 1 khz 25 C 21.6 pf zo Closed-loop output impedance f = 1 khz, AV = 1 25 C.25 Ω CMRR Common-mode rejection ratio VIC = to 1 V, RS = 5 Ω ksvr 25 C 8 11 Full range 8 Supply voltage rejection ratio VDD = 4.5 V to 16 V, VIC = VDD /2, 25 C 8 1 ( VDD / VIO) No load Full range 8 IDD Supply current (per channel) VO = 7.5 V, No load 25 C Full range 3.5 Supply current in shutdown IDD(SHDN) mode (TLC8, TLC83, SHDN.8 V TLC85) (per channel) 25 C Full range Full range is C to 7 C for C suffix and 4 C to 125 C for I suffix. If not specified, full range is 4 C to 125 C. db db db ma µaa 9

10 SLOS254E JUNE 1999 REVISED APRIL 26 operating characteristics at specified free-air temperature, V DD = 12 V (unless otherwise noted) SR+ SR Vn PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Positive slew rate at unity gain Negative slew rate at unity gain Equivalent input noise voltage VO(PP) = 2 V, CL = 5 pf, 25 C 1 16 RL = 1 kω Full range 9.5 VO(PP) = 2 V, CL = 5 pf, 25 C RL = 1 kω Full range 1 f = 1 Hz 25 C 14 f = 1 khz 25 C 8.5 V/µs V/µs nv/ Hz In Equivalent input noise current f = 1 khz 25 C.6 fa / Hz AV = 1.2% VO(PP) = 8 V, THD + N Total harmonic distortion plus noise RL = 1 kω and 25 Ω, AV = 1 25 C.5% f = 1 khz AV = 1.22% t(on) Amplifier turnon time 25 C.47 µs t(off) Amplifier turnoff time RL = 1 kω 25 C 2.5 µs ts φm Gain-bandwidth product f = 1 khz, RL = 1 kω 25 C 1 MHz Settling time Phase margin Gain margin V(STEP)PP = 1 V, AV = 1, CL = 1 pf, RL = 1 kω V(STEP)PP = 1 V, AV = 1, CL = 47 pf, RL = 1 kω RL = 1 kω, RL = 1 kω, RL = 1 kω, RL = 1 kω,.1%.17.1%.1% 25 C %.29 CL = 5 pf CL = pf CL = 5 pf CL = pf Full range is C to 7 C for C suffix and 4 C to 125 C for I suffix. If not specified, full range is 4 C to 125 C. Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. 25 C 25 C µss db 1

11 SLOS254E JUNE 1999 REVISED APRIL 26 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Common-mode input voltage 1, 2 IIO Input offset current Free-air temperature 3, 4 IIB Input bias current Free-air temperature 3, 4 VOH High-level output voltage High-level output current 5, 7 VOL Low-level output voltage Low-level output current 6, 8 Zo Output impedance Frequency 9 IDD Supply current Supply voltage 1 PSRR supply rejection ratio Frequency 11 CMRR Common-mode rejection ratio Frequency 12 Vn Equivalent input noise voltage Frequency 13 VO(PP) Peak-to-peak output voltage Frequency 14, 15 Crosstalk Frequency 16 Differential voltage gain Frequency 17, 18 Phase Frequency 17, 18 φm Phase margin Load capacitance 19, 2 SR THD + N Gain margin Load capacitance 21, 22 Gain-bandwidth product Supply voltage 23 Slew rate Total harmonic distortion plus noise Supply voltage Free-air temperature 24 25, 26 Frequency 27, 28 Peak-to-peak output voltage 29, 3 Large-signal follower pulse response 31, 32 Small-signal follower pulse response 33 Large-signal inverting pulse response 34, 35 Small-signal inverting pulse response 36 Shutdown forward isolation Frequency 37, 38 Shutdown reverse isolation Frequency 39, 4 Shutdown supply current Supply voltage 41 Free-air temperature 42 Shutdown pulse 43,

12 SLOS254E JUNE 1999 REVISED APRIL 26 TYPICAL CHARACTERISTICS V IO Input Offset Voltage µ V INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE 1 VDD = 5 V 8 TA = 25 C VICR Common-Mode Input Voltage V Figure 1 V IO Input Offset Voltage µ V INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE VDD = 12 V TA = 25 C VICR Common-Mode Input Voltage V Figure 2 / I IO Input Bias and Input Offset Current pa I IB INPUT BIAS CURRENT AND INPUT OFFSET CURRENT FREE-AIR TEMPERATURE VDD = 5 V IIB TA Free Air Temperature C Figure 3 IIO / I IO Input Bias and Input Offset Current pa I IB INPUT BIAS CURRENT AND INPUT OFFSET CURRENT FREE-AIR TEMPERATURE VDD = 12 V TA Free-Air Temperature C Figure 4 IIO IIB V OH High-Level Output Voltage V HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT VDD = 5 V TA = 4 C TA = 7 C TA = 125 C IOH - High-Level Output Current - ma Figure 5 V OL Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VDD = 5 V TA = 7 C TA = 125 C TA = 4 C IOL - Low-Level Output Current - ma Figure HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT 1. LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT 1 OUTPUT IMPEDANCE FREQUENCY V OH High-Level Output Voltage V TA = 125 C TA = 7 C VDD = 12 V TA = 4 C IOH - High-Level Output Current - ma Figure 7 V OL Low-Level Output Voltage V TA = 125 C TA = 7 C TA = 4 C.1 VDD = 12 V IOL - Low-Level Output Current - ma Figure 8 Z o Output Impedance Ω k VDD = 5 V and 12 V AV = 1 AV = 1 AV = 1 1k 1k f - Frequency - Hz Figure 9 1M 1M 12

13 SLOS254E JUNE 1999 REVISED APRIL 26 TYPICAL CHARACTERISTICS I DD Supply Current ma SUPPLY CURRENT SUPPLY VOLTAGE TA = 4 C TA = 7 C TA = 125 C AV = SHDN = VDD Per Channel VDD Supply Voltage - V Figure 1 Supply Rejection Ratio db PSRR POWER SUPPLY REJECTION RATIO FREQUENCY VDD = 5 V 1 1k VDD = 12 V 1k f Frequency Hz Figure 11 1k 1M 1M CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO FREQUENCY k VDD = 5 V and 12 V 1k 1k 1M 1M f - Frequency - Hz Figure 12 nv/ Hz V n Equivalent Input Noise Voltage EQUIVALENT INPUT NOISE VOLTAGE FREQUENCY VDD = 5 V 1 1 VDD = 12 V 1k 1k f Frequency Hz Figure 13 1k V O(PP) Peak-to-Peak Output Voltage V k PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY VDD = 12 V VDD = 5 V THD+N < = 5% RL = 6 Ω 1k 1M 1M f - Frequency - Hz Figure 14 V O(PP) Peak-to-Peak Output Voltage V k PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY VDD = 12 V VDD = 5 V THD+N < = 5% RL= 1 kω 1k 1M 1M f - Frequency - Hz Figure 15 Crosstalk db VDD = 5 V and 12 V AV = 1 RL = 1 kω VI(PP) = 2 V For All Channels CROSSTALK FREQUENCY k 1k f Frequency Hz Figure 16 1k 13

14 SLOS254E JUNE 1999 REVISED APRIL 26 TYPICAL CHARACTERISTICS DIFFERENTIAL VOLTAGE GAIN AND PHASE FREQUENCY 8 DIFFERENTIAL VOLTAGE GAIN AND PHASE FREQUENCY 8 Different Voltage Gain db A VD k 1k Gain VDD = ±2.5 V RL = 1 kω CL = pf 1k 1M f Frequency Hz Figure 17 Phase 1M M Phase Different Voltage Gain db A VD k 1k Gain VDD = ±6 V RL = 1 kω CL = pf TA = 25 C 1k 1M f Frequency Hz Figure 18 Phase 1M M Phase 4 35 PHASE MARGIN LOAD CAPACITANCE Rnull = Ω Rnull = 1 Ω 45 4 PHASE MARGIN LOAD CAPACITANCE Rnull = Ω GAIN MARGIN LOAD CAPACITANCE Rnull = Ω φ m Phase Margin VDD = 5 V RL = 1 kω Rnull = 5 Ω Rnull = 2 Ω φ m Phase Margin Rnull = 1 Ω VDD = 12 V RL = 1 kω Rnull = 5 Ω Rnull = 2 Ω G Gain Margin db VDD = 5 V RL = 1 kω Rnull = 5 Ω Rnull = 1 Ω Rnull = 2 Ω 1 CL Load Capacitance pf Figure CL Load Capacitance pf Figure CL Load Capacitance pf Figure 21 1 φ m Phase Margin db GAIN MARGIN LOAD CAPACITANCE Rnull = 5 Ω VDD = 12 V RL = 1 kω Rnull = Ω CL Load Capacitance pf Figure 22 Rnull = 1 Ω Rnull = 2 Ω 1 GBWP - Gain Bandwidth Product - MHz GAIN BANDWIDTH PRODUCT SUPPLY VOLTAGE CL = 11 pf RL = 6 Ω RL = 1 kω VDD - Supply Voltage - V Figure 23 SR Slew Rate V/ µ s SLEW RATE SUPPLY VOLTAGE RL = 6 Ω and 1 kω CL = 5 pf AV = 1 Slew Rate Slew Rate VDD - Supply Voltage - V Figure

15 SLOS254E JUNE 1999 REVISED APRIL 26 TYPICAL CHARACTERISTICS SR Slew Rate V/ µ s SLEW RATE FREE-AIR TEMPERATURE Slew Rate Slew Rate + VDD = 5 V RL= 6 Ω and 1 kω CL = 5 pf AV = 1 SR Slew Rate V/ µ s SLEW RATE FREE-AIR TEMPERATURE Slew Rate + VDD = 12 V RL= 6 Ω and 1 kω CL = 5 pf AV = 1 Slew Rate Total Harmonic Distortion + Noise %.1 TOTAL HARMONIC DISTORTION PLUS NOISE FREQUENCY 1.1 AV = 1 AV = 1 AV = 1 VDD = 5 V VO(PP) = 2 V RL = 1 kω TA - Free-Air Temperature - C Figure TA - Free-Air Temperature - C Figure k 1k f Frequency Hz Figure 27 1k Total Harmonic Distortion + Noise %.1.1 TOTAL HARMONIC DISTORTION PLUS NOISE FREQUENCY AV = 1 AV = 1 AV = k 1k f Frequency Hz Figure 28 VDD = 12 V VO(PP) = 8 V RL = 1 kω LARGE SIGNAL FOLLOWER PULSE RESPONSE 1k Total Harmonic Distortion + Noise % TOTAL HARMONIC DISTORTION PLUS NOISE PEAK-TO-PEAK OUTPUT VOLTAGE VDD = 5 V AV = 1 f = 1 khz RL = 6 Ω RL = 25 Ω RL = 1 kω VO(PP) Peak-to-Peak Output Voltage V Figure 29 LARGE SIGNAL FOLLOWER PULSE RESPONSE Total Harmonic Distortion + Noise % TOTAL HARMONIC DISTORTION PLUS NOISE PEAK-TO-PEAK OUTPUT VOLTAGE VDD = 12 V AV = 1 f = 1 khz VO(PP) Peak-to-Peak Output Voltage V Figure 3 RL = 6 Ω RL = 25 Ω RL = 1 kω SMALL SIGNAL FOLLOWER PULSE RESPONSE VI (1 V/Div) VI (5 V/Div) VI(1mV/Div) Output Voltage V V O VO (5 mv/div) VDD = 5 V RL = 6 Ω and 1 kω CL = 8 pf Output Voltage V V O VO (2 V/Div) VDD = 12 V RL = 6 Ω and 1 kω CL = 8 pf V O Output Voltage V VO(5mV/Div) VDD = 5 V and 12 V RL = 6 Ω and 1 kω CL = 8 pf t Time µs Figure t Time µs Figure t Time µs Figure

16 SLOS254E JUNE 1999 REVISED APRIL 26 TYPICAL CHARACTERISTICS LARGE SIGNAL INVERTING PULSE RESPONSE LARGE SIGNAL INVERTING PULSE RESPONSE SMALL SIGNAL INVERTING PULSE RESPONSE Output Voltage V V O VI (2 V/div) VDD = 5 V RL = 6 Ω and 1 kω CL = 8 pf Output Voltage V V O VI (5 V/div) VDD = 12 V RL = 6 Ω and 1 kω CL = 8 pf Output Voltage V V O VI (1 mv/div) VDD = 5 V and 12 V RL = 6 Ω and 1 kω CL = 8 pf VO (5 mv/div) VO (5 mv/div) VO (2 V/Div) t Time µs Figure t Time µs Figure t Time µs Figure 36 Sutdown Forward Isolation - db SHUTDOWN FORWARD ISOLATION FREQUENCY RL = 1 kω VDD = 5 V CL= pf VI(PP) =.1, 2.5, and 5 V RL = 6 Ω Sutdown Forward Isolation - db SHUTDOWN FORWARD ISOLATION FREQUENCY RL = 1 kω VDD = 12 V CL= pf VI(PP) =.1, 8, 12 V RL = 6 Ω Sutdown Reverse Isolation - db SHUTDOWN REVERSE ISOLATION FREQUENCY RL = 1 kω VDD = 5 V CL= pf VI(PP) =.1, 2.5, and 5 V RL = 6 Ω 2 1 1k 1k 1k 1M 1M f - Frequency - Hz Figure 37 1M 2 1 1k 1k 1k 1M 1M f - Frequency - Hz Figure 38 1M 2 1 1k 1k 1k 1M 1M f - Frequency - Hz Figure 39 1M Sutdown Reverse Isolation - db k SHUTDOWN REVERSE ISOLATION FREQUENCY RL = 1 kω VDD = 12 V CL= pf VI(PP) =.1, 8, 12 V RL = 6 Ω 1k 1k 1M 1M f - Frequency - Hz Figure 4 1M I DD(SHDN) Shutdown Supply Current - µ A SHUTDOWN SUPPLY CURRENT SUPPLY VOLTAGE Shutdown On RL = open VIN = VDD/ VDD - Supply Voltage - V Figure 41 I DD(SHDN) Shutdown Supply Current - µ A SHUTDOWN SUPPLY CURRENT FREE-AIR TEMPERATURE AV = 1 VIN = VDD/2 VDD = 12 V VDD = 5 V TA - Free-Air Temperature - C Figure

17 SLOS254E JUNE 1999 REVISED APRIL 26 TYPICAL CHARACTERISTICS I DD Supply Current ma SHUTDOWN PULSE Shutdown Pulse VDD = 5 V CL= 8 pf IDD RL = 1 kω IDD RL = 6 Ω SD Off t - Time - µs Figure Shutdown Pulse - V I DD Supply Current ma SHUTDOWN PULSE Shutdown Pulse VDD = 12 V CL= 8 pf IDD RL = 1 kω IDD RL = 6 Ω SD Off t - Time - µs Figure Shutdown Pulse - V PARAMETER MEASUREMENT INFORMATION _ + Rnull RL CL Figure 45 APPLICATION INFORMATION input offset voltage null circuit The TLC8 and TLC81 has an input offset nulling function. Refer to Figure 46 for the diagram. IN IN + + N1 1 kω N2 OUT R1 NOTE A: R1 = 5.6 kω for offset voltage adjustment of ±1 mv. R1 = 2 kω for offset voltage adjustment of ±3 mv. VDD Figure 46. Input Offset Voltage Null Circuit 17

18 SLOS254E JUNE 1999 REVISED APRIL 26 driving a capacitive load APPLICATION INFORMATION When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 1 pf, it is recommended that a resistor be placed in series (R NULL ) with the output of the amplifier, as shown in Figure 47. A minimum value of 2 Ω should work well for most applications. RF Input RG _ + RNULL Output CLOAD Figure 47. Driving a Capacitive Load offset voltage The output offset voltage, (V OO ) is the sum of the input offset voltage (V IO ) and both input bias currents (I IB ) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF RG IIB RS VI + + VO IIB+ V OO V IO 1 R F R G I IB R S 1 R F R G I IB R F Figure 48. Output Offset Voltage Model 18

19 high speed CMOS input amplifiers SLOS254E JUNE 1999 REVISED APRIL 26 APPLICATION INFORMATION The TLC8x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance of the order of 2 pf. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance. For example, a gain of 1, a source resistance of 1 kω, and a feedback resistance of 1 kω add an additional pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater input capacitance. This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their unity-gain bandwidth. However, the TLC8x with its 1-MHz bandwidth means that this pole normally occurs at frequencies where there is on the order of 5dB gain left and the phase shift adds considerably. The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the feedback resistance is increased, the gain peaking increases at a lower frequency and the 18 phase shift crossover point also moves down in frequency, decreasing the phase margin. For the TLC8x, the maximum feedback resistor recommended is 5 kω; larger resistances can be used but a capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance pole. The TLC83 with a 1-V step response has an 8% overshoot with a natural frequency of 3.5 MHz when configured as a unity gain buffer and with a 1-kΩ feedback resistor. By adding a 1-pF capacitor in parallel with the feedback resistor, the overshoot is reduced to 4% and eliminates the natural frequency, resulting in a much faster settling time (see Figure 49). The 1-pF capacitor was chosen for convenience only. Load capacitance had little effect on these measurements due to the excellent output drive capability of the TLC8x. V O Output Voltage V VOUT VIN With CF = 1 pf VDD = ±5 V AV = +1 RF = 1 kω RL = 6 Ω CL = 22 pf t - Time - µs V I Input Voltage V IN 1 pf 1 kω _ + 5 Ω 6 Ω 22 pf Figure V Step Response 19

20 SLOS254E JUNE 1999 REVISED APRIL 26 general configurations APPLICATION INFORMATION When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 5). RG RF VI R1 V O V I C1 + f 3dB 1 R F R G 1 1 sr1c1 VO 1 2 R1C1 Figure 5. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 1 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. VI R1 R2 C2 C1 + _ R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q =.77) f 1 3dB 2 RC RG RF RG = ( RF 1 2 Q ) Figure Pole Low-Pass Sallen-Key Filter 2

21 SLOS254E JUNE 1999 REVISED APRIL 26 APPLICATION INFORMATION shutdown function Three members of the TLC8x family (TLC8/3/5) have a shutdown terminal (SHDN) for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 125 µa/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal needs to be pulled to V DD (not system ground) to disable the operational amplifier. The amplifier s output with a shutdown pulse is shown in Figure 43 and Figure 44. The amplifier is powered with a single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are measured from the 5% point of the shutdown pulse to the 5% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. Figure 37 through Figure 4 show the amplifier s forward and reverse isolation in shutdown. The operational amplifier is configured as a voltage follower (A V = 1). The isolation performance is plotted across frequency using.1 V PP, 2.5 V PP, and 5 V PP input signals at ±2.5 V supplies and.1 V PP, 8 V PP, and 12 V PP input signals at ±6 V supplies. circuit layout considerations To achieve the levels of high performance of the TLC8x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. Ground planes It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling Use a 6.8-µF tantalum capacitor in parallel with a.1-µf ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a.1-µf ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the.1-µf capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than.1 inches between the device power terminals and the ceramic capacitors. Sockets Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. Surface-mount passive components Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. 21

22 SLOS254E JUNE 1999 REVISED APRIL 26 general design considerations APPLICATION INFORMATION The TLC8x is available in a thermally-enhanced family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE B: The thermal pad is electrically isolated from all terminals in the package. Figure 52. Views of Thermally-Enhanced DGN Package The package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. Soldering the to the printed circuit board (PCB) is always required, even with applications that have low power dissipation. This soldering provides the necessary thermal and mechanical connection between the lead frame die pad and the PCB. Although there are many ways to properly heatsink the package, the following steps illustrate the recommended approach. 22

23 SLOS254E JUNE 1999 REVISED APRIL 26 APPLICATION INFORMATION general design considerations (continued) The must be connected to the most negative supply voltage (GND pin potential) of the device. 1. Prepare the PCB with a top side etch pattern (see the landing patterns at the end of this data sheet). There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLC8x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal plane that is at the same potential as the ground pin of the device. 5. When connecting these holes to this internal plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLC8x package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the TLC8x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given θ JA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula: P D T MAX T A JA Where: P D = Maximum power dissipation of TLC8x IC (watts) T MAX = Absolute maximum junction temperature (15 C) T A = Free-ambient air temperature ( C) θ JA = θ JC + θ CA θ JC = Thermal coefficient from junction to case θ CA = Thermal coefficient from case to ambient air ( C/W) 23

24 SLOS254E JUNE 1999 REVISED APRIL 26 APPLICATION INFORMATION general design considerations (continued) Maximum Dissipation W MAXIMUM POWER DISSIPATION FREE-AIR TEMPERATURE DGN Package Low-K Test PCB θ JA = 52.3 C/W PDIP Package Low-K Test PCB θ JA = 14 C/W PWP Package Low-K Test PCB θ JA = 29.7 C/W SOT-23 Package Low-K Test PCB θ JA = 324 C/W T J = 15 C SOIC Package Low-K Test PCB θ JA = 176 C/W TA Free-Air Temperature C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 53. Maximum Dissipation Free-Air Temperature The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ JA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper package. 24

25 macromodel information SLOS254E JUNE 1999 REVISED APRIL 26 APPLICATION INFORMATION Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 54 are generated using the TLC8x typical electrical and operating characteristics at T A = 25 C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 2% (in most cases): Maximum positive output voltage swing Unity-gain frequency Maximum negative output voltage swing Common-mode rejection ratio Slew rate Phase margin Quiescent power dissipation DC output resistance Input bias current AC output resistance Open-loop voltage amplification Short-circuit output current limit NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). PSpice and Parts are trademarks of MicroSim Corporation. 25

26 SLOS254E JUNE 1999 REVISED APRIL 26 APPLICATION INFORMATION VDD RP 2 IN IN + 1 DP 3 RSS ISS 1 J1 J2 11 RD1 C1 12 RD2 VC DC + R2 53 EGND 9 + VB 6 GCM 99 + FB C2 GA 9 RO2 HLIM 7 + VLIM 8 + DLP DLN VLP VLN + GND VAD + + VE * TLC8X_5V 5V operational amplifier macromodel subcircuit * created using Parts release 8. on 12/16/99 at 14:3 * Parts is a MicroSim product. * * connections: non-inverting input * inverting input * positive power supply * negative power supply * output *.subckt TLC8X_5V * c E 12 c E 12 css E 15 dc 5 53 dy de 54 5 dy dlp 9 91 dx dln 92 9 dx dp 4 3 dx egnd 99 poly(2) (3,) (4,).5.5 fb 7 99 poly(5) vb vc ve vlp vln E6 1E3 1E3 14E6 14E6 4 6 *DEVICE=TLC8X_5V, OPAMP, PJF, INT 54 DE OUT ga E 6 gcm E 6 ioff 6 dc 1.212E 6 iss 3 1 dc 13.4E 6 hlim 9 vlim 1K j jx1 j jx2 r E3 rd E3 rd E3 ro ro rp E3 rss E6 vb 9 dc vc 3 53 dc ve 54 4 dc vlim 7 8 dc vlp 91 dc vln 92 dc model dx D(Is=8.E 18).model dy D(Is=8.E 18 Rs=1m Cjo=1p).model jx1 PJF(Is=8.E 15 Beta=1.241E 3 Vto= 1).model jx2 PJF(Is=8.E 15 Beta=1.241E 3 Vto= 1).ends 5 RO1 Figure 54. Boyle Macromodel and Subcircuit 26

27 PACKAGE OPTION ADDENDUM 18-Sep-28 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty TLC8AIDR ACTIVE SOIC D 8 25 Green (RoHS & TLC8AIDRG4 ACTIVE SOIC D 8 25 Green (RoHS & TLC8AIP ACTIVE PDIP P 8 5 Pb-Free TLC8AIPE4 ACTIVE PDIP P 8 5 Pb-Free TLC8CD ACTIVE SOIC D 8 75 Green (RoHS & TLC8CDG4 ACTIVE SOIC D 8 75 Green (RoHS & TLC8CDGNR ACTIVE MSOP- TLC8CDGNRG4 ACTIVE MSOP- DGN 8 25 Green (RoHS & DGN 8 25 Green (RoHS & TLC8CDR ACTIVE SOIC D 8 25 Green (RoHS & TLC8CDRG4 ACTIVE SOIC D 8 25 Green (RoHS & TLC8ID ACTIVE SOIC D 8 75 Green (RoHS & TLC8IDG4 ACTIVE SOIC D 8 75 Green (RoHS & TLC8IDGNR ACTIVE MSOP- TLC8IDGNRG4 ACTIVE MSOP- DGN 8 25 Green (RoHS & DGN 8 25 Green (RoHS & TLC8IDR ACTIVE SOIC D 8 25 Green (RoHS & TLC8IDRG4 ACTIVE SOIC D 8 25 Green (RoHS & TLC8IP ACTIVE PDIP P 8 5 Pb-Free TLC8IPE4 ACTIVE PDIP P 8 5 Pb-Free TLC81AID ACTIVE SOIC D 8 75 Green (RoHS & TLC81AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & TLC81AIDR ACTIVE SOIC D 8 25 Green (RoHS & TLC81AIDRG4 ACTIVE SOIC D 8 25 Green (RoHS & TLC81AIP ACTIVE PDIP P 8 5 Pb-Free Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Addendum-Page 1

28 PACKAGE OPTION ADDENDUM 18-Sep-28 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty TLC81AIPE4 ACTIVE PDIP P 8 5 Pb-Free TLC81CD ACTIVE SOIC D 8 75 Green (RoHS & TLC81CDG4 ACTIVE SOIC D 8 75 Green (RoHS & TLC81CDGN ACTIVE MSOP- TLC81CDGNG4 ACTIVE MSOP- TLC81CDGNR ACTIVE MSOP- TLC81CDGNRG4 ACTIVE MSOP- DGN 8 8 Green (RoHS & DGN 8 8 Green (RoHS & DGN 8 25 Green (RoHS & DGN 8 25 Green (RoHS & TLC81CDR ACTIVE SOIC D 8 25 Green (RoHS & TLC81CDRG4 ACTIVE SOIC D 8 25 Green (RoHS & TLC81CP ACTIVE PDIP P 8 5 Pb-Free TLC81CPE4 ACTIVE PDIP P 8 5 Pb-Free TLC81ID ACTIVE SOIC D 8 75 Green (RoHS & TLC81IDG4 ACTIVE SOIC D 8 75 Green (RoHS & TLC81IDGNR ACTIVE MSOP- TLC81IDGNRG4 ACTIVE MSOP- DGN 8 25 Green (RoHS & DGN 8 25 Green (RoHS & TLC81IDR ACTIVE SOIC D 8 25 Green (RoHS & TLC81IDRG4 ACTIVE SOIC D 8 25 Green (RoHS & TLC81IP ACTIVE PDIP P 8 5 Pb-Free TLC81IPE4 ACTIVE PDIP P 8 5 Pb-Free TLC82AID ACTIVE SOIC D 8 75 Green (RoHS & TLC82AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & TLC82AIDR ACTIVE SOIC D 8 25 Green (RoHS & TLC82AIDRG4 ACTIVE SOIC D 8 25 Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Addendum-Page 2

29 PACKAGE OPTION ADDENDUM 18-Sep-28 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty TLC82AIP ACTIVE PDIP P 8 5 Pb-Free TLC82AIPE4 ACTIVE PDIP P 8 5 Pb-Free TLC82CD ACTIVE SOIC D 8 75 Green (RoHS & TLC82CDG4 ACTIVE SOIC D 8 75 Green (RoHS & TLC82CDGN ACTIVE MSOP- TLC82CDGNG4 ACTIVE MSOP- TLC82CDGNR ACTIVE MSOP- TLC82CDGNRG4 ACTIVE MSOP- DGN 8 8 Green (RoHS & DGN 8 8 Green (RoHS & DGN 8 25 Green (RoHS & DGN 8 25 Green (RoHS & TLC82CDR ACTIVE SOIC D 8 25 Green (RoHS & TLC82CDRG4 ACTIVE SOIC D 8 25 Green (RoHS & TLC82CP ACTIVE PDIP P 8 5 Pb-Free TLC82CPE4 ACTIVE PDIP P 8 5 Pb-Free TLC82ID ACTIVE SOIC D 8 75 Green (RoHS & TLC82IDG4 ACTIVE SOIC D 8 75 Green (RoHS & TLC82IDGN ACTIVE MSOP- TLC82IDGNG4 ACTIVE MSOP- TLC82IDGNR ACTIVE MSOP- TLC82IDGNRG4 ACTIVE MSOP- DGN 8 8 Green (RoHS & DGN 8 8 Green (RoHS & DGN 8 25 Green (RoHS & DGN 8 25 Green (RoHS & TLC82IDR ACTIVE SOIC D 8 25 Green (RoHS & TLC82IDRG4 ACTIVE SOIC D 8 25 Green (RoHS & TLC82IP ACTIVE PDIP P 8 5 Pb-Free TLC82IPE4 ACTIVE PDIP P 8 5 Pb-Free Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TLC83AID ACTIVE SOIC D 14 5 Green (RoHS & Addendum-Page 3

30 PACKAGE OPTION ADDENDUM 18-Sep-28 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TLC83AIDG4 ACTIVE SOIC D 14 5 Green (RoHS & TLC83AIN ACTIVE PDIP N Pb-Free TLC83AINE4 ACTIVE PDIP N Pb-Free TLC83CD ACTIVE SOIC D 14 5 Green (RoHS & TLC83CDG4 ACTIVE SOIC D 14 5 Green (RoHS & TLC83CDGQR ACTIVE MSOP- TLC83CDGQRG4 ACTIVE MSOP- DGQ 1 25 Green (RoHS & DGQ 1 25 Green (RoHS & TLC83CDR ACTIVE SOIC D Green (RoHS & TLC83CDRG4 ACTIVE SOIC D Green (RoHS & TLC83CN ACTIVE PDIP N Pb-Free TLC83CNE4 ACTIVE PDIP N Pb-Free TLC83IDGQ ACTIVE MSOP- TLC83IDGQG4 ACTIVE MSOP- DGQ 1 8 Green (RoHS & DGQ 1 8 Green (RoHS & TLC83IN ACTIVE PDIP N Pb-Free TLC83INE4 ACTIVE PDIP N Pb-Free TLC84AID ACTIVE SOIC D 14 5 Green (RoHS & TLC84AIDG4 ACTIVE SOIC D 14 5 Green (RoHS & TLC84AIDR ACTIVE SOIC D Green (RoHS & TLC84AIDRG4 ACTIVE SOIC D Green (RoHS & TLC84AIN ACTIVE PDIP N Pb-Free TLC84AINE4 ACTIVE PDIP N Pb-Free TLC84AIPWP ACTIVE HTSSOP PWP 2 7 Green (RoHS & TLC84AIPWPG4 ACTIVE HTSSOP PWP 2 7 Green (RoHS & Cu NiPdAu Cu NiPdAu Level-2-26C-1 YEAR Level-2-26C-1 YEAR TLC84AIPWPR ACTIVE HTSSOP PWP 2 2 Green (RoHS & Level-2-26C-1 YEAR Addendum-Page 4

31 PACKAGE OPTION ADDENDUM 18-Sep-28 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TLC84AIPWPRG4 ACTIVE HTSSOP PWP 2 2 Green (RoHS & TLC84CD ACTIVE SOIC D 14 5 Green (RoHS & TLC84CDG4 ACTIVE SOIC D 14 5 Green (RoHS & TLC84CDR ACTIVE SOIC D Green (RoHS & TLC84CDRG4 ACTIVE SOIC D Green (RoHS & TLC84CN ACTIVE PDIP N Pb-Free TLC84CNE4 ACTIVE PDIP N Pb-Free TLC84CPWP ACTIVE HTSSOP PWP 2 7 Green (RoHS & TLC84CPWPG4 ACTIVE HTSSOP PWP 2 7 Green (RoHS & TLC84CPWPR ACTIVE HTSSOP PWP 2 2 Green (RoHS & TLC84CPWPRG4 ACTIVE HTSSOP PWP 2 2 Green (RoHS & TLC84ID ACTIVE SOIC D 14 5 Green (RoHS & TLC84IDG4 ACTIVE SOIC D 14 5 Green (RoHS & TLC84IDR ACTIVE SOIC D Green (RoHS & TLC84IDRG4 ACTIVE SOIC D Green (RoHS & TLC84IPWP ACTIVE HTSSOP PWP 2 7 Green (RoHS & TLC84IPWPG4 ACTIVE HTSSOP PWP 2 7 Green (RoHS & TLC84IPWPR ACTIVE HTSSOP PWP 2 2 Green (RoHS & TLC84IPWPRG4 ACTIVE HTSSOP PWP 2 2 Green (RoHS & TLC85AID ACTIVE SOIC D 16 4 Green (RoHS & TLC85AIDG4 ACTIVE SOIC D 16 4 Green (RoHS & TLC85AIDR ACTIVE SOIC D Green (RoHS & TLC85AIDRG4 ACTIVE SOIC D Green (RoHS & TLC85AIN ACTIVE PDIP N Pb-Free TLC85AINE4 ACTIVE PDIP N Pb-Free Call TI Call TI Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR Addendum-Page 5

32 PACKAGE OPTION ADDENDUM 18-Sep-28 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty TLC85AIPWP ACTIVE HTSSOP PWP 2 7 Green (RoHS & TLC85AIPWPG4 ACTIVE HTSSOP PWP 2 7 Green (RoHS & TLC85CD ACTIVE SOIC D 16 4 Green (RoHS & TLC85CDG4 ACTIVE SOIC D 16 4 Green (RoHS & TLC85CDR ACTIVE SOIC D Green (RoHS & TLC85CDRG4 ACTIVE SOIC D Green (RoHS & TLC85CN ACTIVE PDIP N Pb-Free TLC85CNE4 ACTIVE PDIP N Pb-Free TLC85CPWP ACTIVE HTSSOP PWP 2 7 Green (RoHS & TLC85CPWPG4 ACTIVE HTSSOP PWP 2 7 Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR Level-2-26C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free, Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free : TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC84 : Automotive: TLC84-Q1 Addendum-Page 6