TLV2302, TLV2304 FAMILY OF NANOPOWER OPERATIONAL AMPLIFIERS AND OPEN DRAIN COMPARATORS

Transcription

1 TLV, TLV SLOS DECEMBER Micro-Power Operation....μA Input Common-Mode Range Exceeds the Rails.... V to V CC 5 V Supply Voltage Range....5 V to 6 V Rail-to-Rail Input/Output (Amplifier) Reverse Battery Protection Up to 8 V Gain Bandwidth Product khz (Amplifier) Open-Drain CMOS Output Stage (Comparator) Specified Temperature Range T A = C to 5 C... Industrial Grade Ultrasmall Packaging 8-Pin MSOP (TLV) Universal Op-Amp EVM (See the SLOU6 for More Information) I CC Supply Current μ A SUPPLY CURRENT SUPPLY VOLTAGE Op Amp VI = VCC/ Comparator VID = V Rp = MΩ (pullup to VCC) The TLVx combines sub-micropower operational amplifier and comparator into a single package that produces excellent micropower signal conditioning with only. μa of supply current. This combination gives the designer more board space and reduces part counts in systems that require an operational amplifier and comparator. The low supply current makes it an ideal choice for battery-powered portable applications where quiescent current is the primary concern. Reverse battery protection guards the amplifier from an over-current condition due to improper battery installation. For harsh environments, the inputs can be taken 5 V above the positive supply rail without damage to the device. The TLVx s low supply current is coupled with extremely low input bias currents enabling them to be used with mega-ohm resistors making them ideal for portable, long active life, applications. DC accuracy is ensured with a low typical offset voltage as low as 9 μv, CMRR of 9 db and minimum open loop gain of V/mV at.7 V. The maximum recommended supply voltage is as high as 6 V and ensured operation down to.5 V, with electrical characteristics specified at.7 V, 5 V, and 5 V. The.5-V operation makes it compatible with Li-Ion battery-powered systems and many micropower microcontrollers available today including TI s MSP. All members are available in PDIP and SOIC with the duals (one op-amp and one comparator) in the small MSOP package, and the quads (two operational amplifiers and two comparators) in the TSSOP package. DEVICE VCC (V) VIO (μv) A SELECTION OF OUTPUT COMPARATORS ICC/Ch (μa) GBW (khz) SR (V/μs) tplh (μs) tphl (μs) tf (μs) RAIL-TO- RAIL OUTPUT STAGE TLVx I/O OD TLV7x I/O PP TLVx I/O TLVx I/O TLVx I OD TLV7x I PP All specifications are typical values measured at 5 V. ICC is specified as one op-amp and one comparator VCC Supply Voltage V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Instruments Incorporated POST OFFICE BOX 655 DALLAS, TEXAS 7565

2 TLV, TLV SLOS DECEMBER TA VIOmax AT 5 C TLV AVAILABLE OPTIONS SMALL OUTLINE (D) PACKAGED DEVICES MSOP (DGK) MSOP SYMBOLS PLASTIC DIP (P) - C to 5 C μv TLVID TLVIDGK xxtiaqg TLVIP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLVIDR). TA TLV AVAILABLE OPTIONS PACKAGED DEVICES VIOmax SMALL OUTLINE TSSOP AT 5 C (D) (PW) PLASTIC DIP (N) C to 5 C μv TLVID TLVIPW TLVIN This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLVIDR). AOUT AIN AIN GND TLV D, DGK, OR P PACKAGE TLVx PACKAGE PINOUTS (TOP VIEW) COUT CIN 8 V CC CIN 7 COUT V CC 6 CIN CIN 5 5 CIN CIN 6 COUT 7 TLV D, N, OR PW PACKAGE (TOP VIEW) 9 8 AOUT AIN AIN GND AIN AIN AOUT POST OFFICE BOX 655 DALLAS, TEXAS 7565

3 TLV, TLV SLOS DECEMBER absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Differential input voltage, V ID V CC Input voltage range, V I (see Notes and ) to V CC 5 V Input current range, I I (any input) ± ma Output current range, I O ± ma Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : I suffix C to 5 C Maximum junction temperature, T J C Storage temperature range, T stg C to 5 C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values, except differential voltages, are with respect to GND. Input voltage range is limited to V max or VCC 5 V, whichever is smaller. PACKAGE recommended operating conditions Supply voltage, VCC DISSIPATION RATING TABLE ΘJC ΘJA TA 5 C ( C/W) ( C/W) POWER RATING POWER RATING D (8) mw mw D () 6.9. mw. mw DGK (8) mw 96. mw N () 78 6 mw.5 mw P (8) mw. mw PW () mw mw MIN MAX UNIT Single supply.5 6 Split supply ±.5 ±8 Common-mode input voltage range, VICR Amplifier and comparator. VCC5 V Operating free-air temperature, TA 5 C V POST OFFICE BOX 655 DALLAS, TEXAS 7565

4 TLV, TLV SLOS DECEMBER electrical characteristics at recommended operating conditions, V CC =.7, 5 V, and 5 V (unless otherwise noted) amplifier dc performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT 5 C 9 VIO Input offset voltage VO =VCC/ V, VIC = VCC/ V, Full range 6 αvio Offset voltage draft RS = 5 Ω 5 C μv/ C mode VIC = to VCC, CMRR Common-mode rejection ratio RS = 5 Ω AVD Large-signal g differential voltage amplification VCC = 7V.7 VCC = 5V VCC =7V.7 V, VO(pp) =5V.5 V, RL = 5 kω, VO(pp) = V, RL = 5 kω, VO(pp) = 8 V, RL = 5 kω Power supply rejection ratio V = VCC/ V, No load PSRR IC (ΔVCC/ΔVIO) Full range is C to 5 C. amplifier and comparator input characteristics IIO IIB VCC = 7to5V.7 VCC = 5to5V 5 C 55 7 Full range 5 5 C 6 8 Full range 55 5 C 66 9 Full range 6 5 C Full range 5 C Full range 5 C Full range 5 C 9 Full range 85 5 C 9 Full range 9 PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Input offset current Input bias current 5 C 5 5 μv db V/mV to 7 C pa VO =VCC/ V, VIC = VCC/ V, Full range 5 Rp = MΩ (pullup to VCC), 5 C 5 RS = 5 Ω to 7 C 55 pa Full range ri(d) Differential input resistance 5 C MΩ Ci(c) Common-mode input capacitance Full range is C to 5 C. f = khz 5 C pf db POST OFFICE BOX 655 DALLAS, TEXAS 7565

5 TLV, TLV SLOS DECEMBER electrical characteristics at recommended operating conditions, V CC =.7, 5 V, and 5 V (unless otherwise noted) (continued) amplifier output characteristics PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VIC = VCC/, VOH High-level output voltage IOH = 5 μa VCC = 7V.7 VCC = 5V VOL Low-level output voltage VIC =VCC/ VCC/, IOL =5μA 5 C Full range.5 5 C Full range.8 5 C Full range.8 5 C 8 6 Full range IO Output current VO =.5 V from rail 5 C ± μa Full range is C to 5 C. amplifier dynamic performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT UGBW Unity gain bandwidth RL = 5 kω, CL = pf 5 C 5.5 khz SR Slew rate at unity gain VO(pp) =.8 V, RL = 5 kω, CL = pf 5 C.5 V/ms φm ts Phase margin Gain margin Settling time RL = 5 kω, CL = pf 5 C VCC =.7 or 5 V, V(STEP)PP = V, CL = pf,.%.8 AV =, RL = kω 5 C,.% 6. V(STEP)PP =V V, CL = pf, AV =, RL = kω.% 6 V mv 5 db ms Vn In Equivalent input noise voltage Equivalent input noise current f =. to Hz 5. μvpp 5 C f = Hz 5 nv/ Hz f = Hz 5 C 8 fa/ Hz supply current PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ICC VCC =.7 V or 5 V 5 C. Supply current (one op-amp and one Rp = No pullup, 5 C..7 comparator) Output state high Full range. μa Reverse supply current VCC = 8 V, VI = V, VO = open 5 C 5 na Full range is C to 5 C. POST OFFICE BOX 655 DALLAS, TEXAS

6 TLV, TLV SLOS DECEMBER electrical characteristics at recommended operating conditions, V CC =.7, 5 V, and 5 V (unless otherwise noted) (continued) comparator dc performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VIO Input offset voltage VIC= VCC/, RS = 5 Ω, Rp =MΩ (pullup to VCC) αvio Offset voltage drift VIC= to VCC, CMRR Common-modemode rejection ratio RS = 5 Ω AVD Large-signal differential voltage amplification Power supply rejection ratio V = VCC/ V, PSRR IC (ΔV CC/ΔVIO) No load Full range is C to 5 C. comparator output characteristics IOZ VCC =7V.7 VCC = 5V 5 C 5 5 Full range 7 μv 5 C μv/ C 5 C 55 7 Full range 5 5 C 6 76 Full range 55 5 C Full range 6 Rp = MΩ (pullup to VCC) 5 C V/mV VCC = 7to5V.7 VCC = 5to5V 5 C 75 Full range 7 5 C 85 5 Full range 8 PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT High-impedance output leakage current VIC = VCC/, VO = VCC, VID = V 5 C 5 pa 5 C 8 VOL Low-level output voltage VIC = VCC/, IOL = 5 μa, VID = V mv Full range Full range is C to 5 C. db db switching characteristics at recommended operating conditions, V CC =.7 V, 5 V, 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Overdrive = mv 75 t(plh) ( Propagation delay time, low-to-high-level output f = khz, Overdrive = mv 5 C 55 VSTEP = V, Overdrive = 5 mv 5 CL = pf, Overdrive = mv Propagation delay time, Rp = MΩ (pullup to VCC) t(phl) Overdrive = mv 5 C 6 high-to-low-level output Overdrive = 5 mv tf Fall time CL = pf 5 C 5 μs NOTE: The response time specified is the interval between the input step function and the instant when the output crosses. V. μs 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

7 TLV, TLV SLOS DECEMBER TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Common-mode input voltage, IIB IIO ICC Amplifier Input bias current Input offsetcurrent Supply current Free-air temperature, 5, 7 Common-mode input voltage, 6 Free-air temperature, 5, 7 Common-mode input voltage, 6 Supply voltage 8 Free-air temperature 9 CMRR Common-mode rejection ratio Frequency VOH High-level output voltage High-level output current, VOL Low-level output voltage Low-level output current, VO(PP) Output voltage, peak-to-peak Frequency 5 PSRR Power supply rejection ratio Frequency 6 Voltage noise over a Second Period 7 φm Phase margin Capacitive load 8 AVD Differential voltage gain Frequency 9 Phase Frequency 9 Gain bandwidth product Supply voltage SR Slew rate Free-air temperature Comparator Large signal follower pulse response Small signal follower pulse response Large signal inverting pulse response Small signal inverting pulse response 5 VOL Low-level output voltage Low-level output current 6, 7 Open collector leakage current Free-air temperature 8 Output fall time Supply voltage 9 Low-to-high level output response for various input overdrives, High-to-low level output response for various input overdrives, POST OFFICE BOX 655 DALLAS, TEXAS

8 TLV, TLV SLOS DECEMBER AMPLIFIER AND COMPARATOR TYPICAL CHARACTERISTICS V IO Input Offset Voltage V μ I IB /I IO Input Bias / Offset Current pa 8 6 INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE VCC =.7 V VICR Common-Mode Input Voltage V Figure INPUT BIAS/OFFSET CURRENT COMMON-MODE INPUT VOLTAGE VCC =.7 V TA = 5 C IIO IIB VICR Common Mode Input Voltage V Figure V IO Input Offset Voltage V μ I IB /I IO Input Bias / Offset Current pa INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE TA = 5 C VICR Common-Mode Input Voltage V Figure INPUT BIAS/OFFSET CURRENT FREE-AIR TEMPERATURE VIC =.5 V IIO IIB TA Free-Air Temperature C Figure 5 I IB /I IO Input Bias / Offset Current pa I IB /I IO Input Bias / Offset Current pa 6 5 INPUT BIAS / OFFSET CURRENT FREE-AIR TEMPERATURE VCC =.7 V VIC =.5 V IIO IIB TA Free-Air Temperature C Figure INPUT BIAS/OFFSET CURRENT COMMON-MODE INPUT VOLTAGE TA = 5 C IIO IIB VICR Common Mode Input Voltage V Figure 6 I IB / I IO Input Bias/Offset Current pa 8 6 INPUT BIAS/OFFSET CURRENT FREE-AIR TEMPERATURE IIO IIB I CC Supply Current μ A SUPPLY CURRENT SUPPLY VOLTAGE TA = C TA = 7 C TA = C Op Amp, VI = VCC/ Comparator, VID = V Rp = MΩ (pullup to VCC) I CC Supply Current μ A SUPPLY CURRENT FREE-AIR TEMPERATURE VCC =.7, 5, & 5 V Op Amp VI = VCC/ AV = Comparator VID = V Rp = MΩ (pullup to VCC) TA Free-Air Temperature C Figure VCC Supply Voltage V Figure TA Free-Air Temperature C Figure 9 8 POST OFFICE BOX 655 DALLAS, TEXAS 7565

9 TLV, TLV SLOS DECEMBER AMPLIFIER TYPICAL CHARACTERISTICS CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO FREQUENCY 8 6 VCC=.7, 5, 5 V RF= kω RI= kω k k f Frequency Hz Figure V OH High-Level Output Voltage V HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT VCC =.7 V TA = C TA = C TA = 5 C TA = 7 C TA = 5 C. 5 5 IOH High-Level Output Current μa Figure V OL Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VCC =.7 V TA =5 C TA = C TA = C TA = 7 C TA = 5 C 5 5 IOL Low-Level Output Current μa Figure V OH High-Level Output Voltage V HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT T A = C TA = C TA = 5 C TA = 7 C TA = 5 C. 5 5 IOH High-Level Output Current μa Figure V OL Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT TA = C TA = C TA = 5 C TA = 7 C TA = 5 C 5 5 IOL Low-Level Output Current μa Figure Output Voltage Peak-to-Peak V V O(PP) OUTPUT VOLTAGE PEAK-TO-PEAK FREQUENCY VCC =.7 V RL = kω CL = pf k f Frequency Hz Figure 5 PSRR Power Supply Rejection Ratio db POWER SUPPLY REJECTION RATIO FREQUENCY VCC =.7, 5, & 5 V k k f Frequency Hz Figure 6 Input Referred Voltage Noise V μ VOLTAGE NOISE OVER A SECOND PERIOD 5 6 t Time s Figure 7 f =. Hz to Hz Phase Margin PHASE MARGIN CAPACITIVE LOAD VCC =.7, 5, & 5 V RL= 5 kω k k CL Capacitive Load pf Figure 8 POST OFFICE BOX 655 DALLAS, TEXAS

10 TLV, TLV SLOS DECEMBER AMPLIFIER TYPICAL CHARACTERISTICS Differential Voltage Gain db A VD DIFFERENTIAL VOLTAGE GAIN AND PHASE FREQUENCY VCC=.7, 5, 5 V RL=5 kω CL= pf TA=5 C 5 k k f Frequency Hz Figure Phase GBWP Gain Bandwidth Product khz GAIN BANDWIDTH PRODUCT SUPPLY VOLTAGE RL = kω CL = pf f = khz VCC Supply Voltage V Figure SR Slew Rate V/ ms SLEW RATE FREE-AIR TEMPERATURE VCC = 5, 5 V SR SR VCC =.7 V VCC =.7, 5, 5 V TA Free-Air Temperature C Figure V O Output Voltage V LARGE SIGNAL FOLLOWER PULSE RESPONSE VIN VO 5 6 t Time ms Figure AV = RL = kω CL = pf V IN Input Voltage V V O Output Voltage mv SMALL SIGNAL FOLLOWER PULSE RESPONSE VIN VO t Time μs Figure VCC =.7, 5, & 5 V AV = RL = kω CL = pf 5 5 V IN Input Voltage mv V O Output Voltage V LARGE SIGNAL INVERTING PULSE RESPONSE VIN AV = RL = kω CL = pf VO t Time ms Figure V IN Input Voltage V V O Output Voltage mv SMALL SIGNAL INVERTING PULSE RESPONSE VIN VCC =.7, 5, & 5 V AV = RL = kω CL = pf VO t Time ms Figure 5 V IN Input Voltage mv POST OFFICE BOX 655 DALLAS, TEXAS 7565

11 TLV, TLV SLOS DECEMBER COMPARATOR TYPICAL CHARACTERISTICS V OL Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VCC =.7 V VID = V TA = 7 C TA = C TA = C V OL Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VID = V TA = 7 C TA = C TA = C IOL Low-Level Output Current ma IOL Low-Level Output Current ma Figure 6 Figure 7 OPEN COLLECTOR LEAKAGE CURRENT FREE-AIR TEMPERATURE I OZ Open Collector Leakage Current pa VID = V VCC =.7 V, 5 V TA Free-Air Temperature C t f Output Fall Time μ s CL = 5 pf OUTPUT FALL TIME SUPPLY VOLTAGE CL = pf VID= V to V Rp = MΩ (pullup to VCC) Input Fall Time = 5 ns VCC Supply Voltage V Figure 8 Figure 9 V O Output Voltage V LOW-TO-HIGH LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES 5 mv mv VCC =.7 V CL = pf RP = MΩ (Pullup to VCC) t Time μs mv..5 V ID Differential Input Voltage V V O Output Voltage V 5 LOW-TO-HIGH LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES 5 mv mv t Time μs mv CL = pf RP = MΩ (Pullup to VCC) V ID Differential Input Voltage V Figure Figure POST OFFICE BOX 655 DALLAS, TEXAS 7565

12 TLV, TLV SLOS DECEMBER COMPARATOR TYPICAL CHARACTERISTICS V O Output Voltage V HIGH-TO-LOW LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES 5 mv mv mv VCC =.7 V CL = pf Rp = MΩ (pullup to VCC) t Time μs..5 V ID Differential Input Voltage V V O Output Voltage V 6 5 HIGH-TO-LOW LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES 5 mv mv mv CL = pf Rp = MΩ (pullup to VCC) t Time μs..5 Differential V ID Input Voltage V Figure Figure APPLICATION INFORMATION reverse battery protection The TLV/ is protected against reverse battery voltage up to 8 V. When subjected to reverse battery condition, the supply current is typically less than na at 5 C (inputs grounded and outputs open). This current is determined by the leakage of six Schottky diodes and will therefore increase as the ambient temperature increases. When subjected to reverse battery conditions and negative voltages applied to the inputs or outputs, the input ESD structure will turn on this current should be limited to less than ma. If the inputs or outputs are referred to ground, rather than midrail, no extra precautions need be taken. common-mode input range The TLV/ has rail-rail input and outputs. For common-mode inputs from. V to V CC.8 V a PNP differential pair will provide the gain. For inputs between V CC.8 V and V CC, two NPN emitter followers buffering a second PNP differential pair provide the gain. This special combination of NPN/PNP differential pair enables the inputs to be taken 5 V above the rails; because as the inputs go above V CC, the NPNs switch from functioning as transistors to functioning as diodes. This will lead to an increase in input bias current. The second PNP differential pair continues to function normally as the inputs exceed V CC. The TLV/ has a negative common-input range that exceeds ground by mv. If the inputs are taken much below this, reduced open loop gain will be observed with the ultimate possibility of phase inversion. POST OFFICE BOX 655 DALLAS, TEXAS 7565

13 TLV, TLV SLOS DECEMBER APPLICATION INFORMATION offset voltage The output offset voltage, (V OO ) is the sum of the input offset voltage (V IO ) and both input bias currents (I IB ) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage. RF RG IIB RS VI VO V OO V IO R F R G I IB R S R F R G I IB R F IIB Figure. Output Offset Voltage Model general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 5). RG RF f db RC VI R C VO V O V I R F R G src Figure 5. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. VI R R C C _ R = R = R C = C = C Q = Peaking Factor (Butterworth Q =.77) f db RC RG RF RG = ( RF Q ) Figure 6. -Pole Low-Pass Sallen-Key Filter POST OFFICE BOX 655 DALLAS, TEXAS 7565

14 TLV, TLV SLOS DECEMBER circuit layout considerations APPLICATION INFORMATION To achieve the levels of high performance of the TLVx, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. Ground planes It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling Use a 6.8-μF tantalum capacitor in parallel with a.-μf ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a.-μf ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the.-μf capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than. inches between the device power terminals and the ceramic capacitors. Sockets Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. Surface-mount passive components Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. POST OFFICE BOX 655 DALLAS, TEXAS 7565

15 general power dissipation considerations TLV, TLV SLOS DECEMBER APPLICATION INFORMATION For a given θ JA, the maximum power dissipation is shown in Figure 7 and is calculated by the following formula: T T P MAX A D JA Where: P D = Maximum power dissipation of TLVx IC (watts) T MAX = Absolute maximum junction temperature (5 C) T A = Free-ambient air temperature ( C) θ JA = θ JC θ CA θ JC = Thermal coefficient from junction to case θ CA = Thermal coefficient from case to ambient air ( C/W) Maximum Power Dissipation W MAXIMUM POWER DISSIPATION FREE-AIR TEMPERATURE SOIC Package Low-K Test PCB θ JA = 76 C/W PDIP Package Low-K Test PCB θ JA = C/W T J = 5 C MSOP Package Low-K Test PCB θ JA = 6 C/W TA Free-Air Temperature C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 7. Maximum Power Dissipation Free-Air Temperature POST OFFICE BOX 655 DALLAS, TEXAS

16 TLV, TLV SLOS DECEMBER APPLICATION INFORMATION amplifier macromodel information Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note ) and subcircuit in Figure 8 are generated using the TLVx typical electrical and operating characteristics at T A = 5 C. Using this information, output simulations of the following key parameters can be generated to a tolerance of % (in most cases): Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit NOTE : G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 5 (97). 99 VCC rp rc rc ree cee egnd fb ro c 7 c IN vlim 9 r 6 vc 8 IN q q vb ga gcm ioff ro dp 5 re re dlp dln VOUT iee VCC 5 ve de.subckt X_5V X 5 * c 9.89E c 6 7.E cee E dc 5 5 dy de 5 5 dy dlp 9 9 dx dln 9 9 dx dp dx egnd 99 poly() (,) (,).5.5 fb 7 99 poly(5) vb vc ve vlp vln 6.E6 E E 6E6 6E6 ga 6.6E 6 gcm E iee dc 5.5E 9 ioff 6 dc 5e hlim 9 vlim K q qx q qx r 6 9.E dc vlp hlim vln rc 978.8E rc 978.8E re.6e re.6e ree E9 ro 8 5 ro 7 99 rp.8e6 vb 9 dc vc 5 dc.885 ve 5 dc.885 vlim 7 8 dc vlp 9 dc 5 vln 9 dc 5.model dx D(Is=8.E 8).model dy D(Is=8.E 8 Rs=m Cjo=p).model qx NPN(Is=8.E 8 Bf=7.7E).model qx NPN(Is=8.E 8 Bf=7.7E).ends Figure 8. Boyle Macromodels and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

17 PACKAGE OPTION ADDENDUM -Aug-8 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan TLVID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) TLVIDGK ACTIVE VSSOP DGK 8 8 Green (RoHS & no Sb/Br) TLVIDGKG ACTIVE VSSOP DGK 8 8 Green (RoHS & no Sb/Br) TLVIDGKR ACTIVE VSSOP DGK 8 5 Green (RoHS & no Sb/Br) TLVIDR ACTIVE SOIC D 8 5 Green (RoHS & no Sb/Br) TLVIP ACTIVE PDIP P 8 5 Green (RoHS & no Sb/Br) TLVID ACTIVE SOIC D 5 Green (RoHS & no Sb/Br) TLVIDR ACTIVE SOIC D 5 Green (RoHS & no Sb/Br) TLVIN ACTIVE PDIP N 5 Green (RoHS & no Sb/Br) () Lead/Ball Finish (6) MSL Peak Temp () Op Temp ( C) Device Marking (/5) CU NIPDAU Level--6C-UNLIM - to 5 I CU NIPDAU Level--6C-UNLIM - to 5 AQG CU NIPDAU Level--6C-UNLIM - to 5 AQG CU NIPDAU Level--6C-UNLIM - to 5 AQG CU NIPDAU Level--6C-UNLIM - to 5 I CU NIPDAU N / A for Pkg Type - to 5 TLVI CU NIPDAU Level--6C-UNLIM - to 5 I CU NIPDAU Level--6C-UNLIM - to 5 I CU NIPDAU N / A for Pkg Type - to 5 TLVI Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all RoHS substances, including the requirement that RoHS substance do not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS79B low halogen requirements of <=ppm threshold. Antimony trioxide based flame retardants must also meet the <=ppm threshold requirement. () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page

18 PACKAGE OPTION ADDENDUM -Aug-8 () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

19 PACKAGE MATERIALS INFORMATION -Aug-7 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A (mm) B (mm) K (mm) P (mm) W (mm) Pin Quadrant TLVIDGKR VSSOP DGK Q TLVIDR SOIC D Q TLVIDR SOIC D Q Pack Materials-Page

20 PACKAGE MATERIALS INFORMATION -Aug-7 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLVIDGKR VSSOP DGK TLVIDR SOIC D TLVIDR SOIC D Pack Materials-Page

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