TLV2241, TLV2242, TLV2244 FAMILY OF 1-µA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS

Transcription

1 Micropower Operation... µa/channel Rail-to-Rail Input/Output Gain Bandwidth Product khz Supply Voltage Range....5 V to V Specified Temperature Range T A = C to 7 C... Commercial Grade T A = 4 C to 5 C... Industrial Grade Ultrasmall Packaging 5-Pin SOT-3 (TLV4) 8-Pin MSOP (TLV4) Universal OpAmp EVM description The TLV4x family of single-supply operational amplifiers offers very low supply current of only µa per channel. The low supply current is coupled with extremely low input bias currents enabling them to be used with mega-ω resistors making them ideal for portable, long active life, applications. DC accuracy is ensured with a low typical offset voltage as low as 6 µv, CMRR of db, and minimum open loop gain of V/mV at.7 V. TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER The maximum recommended supply voltage is as high as V and ensured operation down to.5 V, with electrical characteristics specified at.7 V, 5 V and V. The.5-V operation makes it compatible with Li-Ion battery-powered systems and many micropower microcontrollers available today including TI s MSP43. DEVICE FAMILY PACKAGE TABLE DEVICE NO. OF Ch PACKAGE TYPES UNIVERSAL PDIP SOIC SOT-3 TSSOP MSOP EVM TLV Refer to the EVM TLV Selection Guide TLV (Lit# SLOU6) SELECTION OF SINGLE SUPPLY OPERATIONAL AMPLIFIER PRODUCTS VDD (V) VIO (mv) BW (MHz) SLEW RATE (V/µs) VCC Supply Voltage V IDD (PER CHANNEL) (µa) RAIL-TO-RAIL TLV4x I/O TLV4x I/O TLV O TLV45x I/O TLV5x O All specifications are typical values measured at 5 V. This device also offers 8-V reverse battery protection and 5-V over-the-rail operation on the inputs. I CC Supply Current µ A/Ch Operational Amplifier SUPPLY CURRENT SUPPLY VOLTAGE AV = VIN = VCC / TA =5 C + Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 7565

2 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER TA C to 7 C 4 C to 5 C VIOmax AT 5 C 3 µv TLV4 AVAILABLE OPTIONS SMALL OUTLINE (D) PACKAGED DEVICES SOT-3 SYMBOLS (DBV) PLASTIC DIP (P) TLV4CD TLV4ID TLV4IDBV VBEI TLV4IP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV4CDR). This package is available in a 5 piece mini-reel. To order this package, add a T suffix to the part number (e.g., TLV4DBVT). This package is also available in a 3 piece reel, add a R suffix to the part number (e.g., TLV4DBVR). TA C to 7 C 4 C to 5 C VIOmax AT 5 C 3 µv TLV4 AVAILABLE OPTIONS PACKAGED DEVICES SMALL OUTLINE (D) MSOP (DGK) SYMBOLS PLASTIC DIP (P) TLV4CD TLV4ID TLV4IDGK xxtiale TLV4IP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV4CDR). TA C to 7 C 4 C to 5 C TLV44 AVAILABLE OPTIONS PACKAGED DEVICES VIOmax SMALL OUTLINE PLASTIC DIP AT 5 C (D) (N) 3 µv TSSOP (PW) TLV44CD TLV44ID TLV44IN TLV44IPW This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV44CDR). TLV4 DBV PACKAGE (TOP VIEW) TLV4x PACKAGE PINOUTS TLV4 D OR P PACKAGE (TOP VIEW) TLV4 D, DGK, OR P PACKAGE (TOP VIEW) OUT GND IN VCC IN NC IN IN+ GND NC V CC OUT NC OUT IN IN+ GND V CC OUT IN IN+ NC No internal connection TLV44 D, N, OR PW PACKAGE (TOP VIEW) OUT IN IN+ V CC IN+ IN OUT OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT POST OFFICE BOX DALLAS, TEXAS 7565

3 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note ) V Differential input voltage, V ID ± V CC Input current, I I (any input) ± ma Output current, I O ± ma Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : C suffix C to 7 C I suffix C to 5 C Maximum junction temperature, T J C Storage temperature range, T stg C to 5 C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltage values, except differential voltages, are with respect to GND PACKAGE recommended operating conditions Supply voltage, VCC DISSIPATION RATING TABLE ΘJC ΘJA TA 5 C TA = 5 C ( C/W) ( C/W) POWER RATING POWER RATING D (8) mw 4 mw D (4) mw 4.4 mw DBV (5) mw 77. mw DGK (8) mw 96. mw N (4) mw 3.5 mw P (8) 4 4 mw 4.4 mw PW (4) mw 44 mw MIN MAX UNIT Single supply.5 Split supply ±.5 ±6 Common-mode input voltage range, VICR VCC V Operating free-air temperature, TA C-suffix 7 I-suffix 4 5 V C POST OFFICE BOX DALLAS, TEXAS

4 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER electrical characteristics at recommended operating conditions, V CC =.7, 5 V, and V (unless otherwise noted) dc performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VIO Input offset voltage VO = VCC/ V, VIC =VCC/ V, RS =5Ω Ω αvio Offset voltage drift 5 C 6 3 Full range 45 µv 5 C 3 µv/ C 5 C 55 VCC =7V.7 Full range 5 CMRR Common-mode mode rejection ratio VIC = to VCC, RS = 5 Ω VCC = 5 V 5 C 6 Full range 53 VCC =V 5 C 6 Full range 55 VCC =7V.7 V, VO(pp) =V V, RL = 5 kω 5 C 4 Full range 3 db AVD Large-signal g differential voltage amplification VCC =5V V, VO(pp) =3V V, RL = 5 kω 5 C 5 Full range V/mV VCC =V V, VO(pp) =6V V, RL = 5 kω 5 C 7 5 Full range Full range is C to 7 C for the C suffix and 4 C to 5 C for the I suffix. If not specified, full range is 4 C to 5 C. input characteristics PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT 5 C 5 5 IIO Input offset current TLV4xC 3 pa Full range VO = VCC/ V, TLV4xI 4 VIC = VCC/ V, RS = 5 Ω 5 C 5 IIB Input bias current TLV4xC TLV4xI Full range 55 pa ri(d) Differential input resistance 5 C 3 MΩ Ci(c) Common-mode input capacitance f = khz 5 C 3 pf Full range is C to 7 C for the C suffix and 4 C to 5 C for the I suffix. If not specified, full range is 4 C to 5 C. Specifications at 5 V are ensured by design and device testing at.7 V and V. 4 POST OFFICE BOX DALLAS, TEXAS 7565

5 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER electrical characteristics at recommended operating conditions, V CC =.7, 5 V, and V (unless otherwise noted) (continued) output characteristics VOH VOL PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT High-level output voltage Low-level output voltage VIC = VCC/, IOH = µa VIC = VCC/, IOH = 5 µa VCC =7V.7 VCC =5V VCC =V VCC =7V.7 VCC =5V VCC =V VIC = VCC/, IOL = µa VIC = VCC/, IOL = 5 µa 5 C Full range.63 5 C Full range C Full range.93 5 C.6.65 Full range.6 5 C Full range C.9.95 Full range.9 5 C 9 5 Full range 8 5 C 8 3 Full range 6 IO Output current VO =.5 V from rail 5 C ± µa Full range is C to 7 C for the C suffix and 4 C to 5 C for the I suffix. If not specified, full range is 4 C to 5 C. power supply PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ICC Supply current (per channel) VO = VCC/ PSRR Power supply rejection ratio ( VCC/ VIO) VCC =.7 to 5 V, VIC = VCC/ V, No load, V mv 5 C 98 VCC =7Vor5V.7 V Full range 5 na 5 C 5 VCC =V Full range 55 TLV4xC TLV4xI 5 C 7 Full range VCC = 5 to V, VIC = VCC/ V, 5 C 7 No load Full range 7 Full range is C to 7 C for the C suffix and 4 C to 5 C for the I suffix. If not specified, full range is 4 C to 5 C. Specifications at 5 V are ensured by design and device testing at.7 V and V. 65 db 6 db db POST OFFICE BOX DALLAS, TEXAS

6 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER electrical characteristics at recommended operating conditions, V CC =.7, 5 V, and V (unless otherwise noted) (continued) dynamic performance PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT UGBW Unity gain bandwidth RL = 5 kω, CL = pf 5 C 5.5 khz SR Slew rate at unity gain VO(pp) =.8 V, RL = 5 kω, CL = pf 5 C V/ms φm ts Phase margin Gain margin Settling time noise/distortion performance Vn Equivalent input noise voltage RL = 5 kω, CL = pf 5 C VCC =.7 or 5 V, V(STEP)PP = V, CL = pf,.%.84 AV =, RL = kω 5 C VCC = V,.% 6. V(STEP)PP =V V, CL = pf, AV =, RL = kω.% db PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT f = Hz 8 f = Hz 5 C 5 ms nv/ Hz In Equivalent input noise current f = Hz 8 fa/ Hz Specifications at 5 V are ensured by design and device testing at.7 V and V. 6 POST OFFICE BOX DALLAS, TEXAS 7565

7 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Common-mode input voltage,, 3 IIB IIO Input bias current Input offset current Free-air temperature 4, 6, 8 Common-mode input voltage 5, 7, 9 Free-air temperature 4, 6, 8 Common-mode input voltage 5, 7, 9 CMRR Common-mode rejection ratio Frequency VOH High-level output voltage High-level output current, 3, 5 VOL Low-level output voltage Low-level output current, 4, 6 VO(PP) Output voltage peak-to-peak Frequency 7 Zo Output impedance Frequency 8 ICC Supply current Supply voltage 9 PSRR Power supply rejection ratio Frequency AVD Differential voltage gain Frequency Phase Frequency Gain-bandwidth product Supply voltage SR Slew rate Free-air temperature 3 φm Phase margin Capacitive load 4 Gain margin Capacitive load 5 Voltage noise over a Second Period 6 Large-signal voltage follower 7, 8, 9 Small-signal voltage follower 3 Large-signal inverting pulse response 3, 3, 33 Small-signal inverting pulse response 34 Crosstalk Frequency 35 POST OFFICE BOX DALLAS, TEXAS

8 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER TYPICAL CHARACTERISTICS V IO Input Offset Voltage V µ I IB /I IO Input Bias / Offset Current pa I IB /I IO Input Bias / Offset Current pa INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE VCC =.7 V TA = 5 C VICR Common-Mode Input Voltage V Figure TA Free-Air Temperature C Figure INPUT BIAS / OFFSET CURRENT FREE-AIR TEMPERATURE VCC =.7 V VIC =.35 V IIO IIB INPUT BIAS / OFFSET CURRENT COMMON-MODE INPUT VOLTAGE VCC = 5 V TA = 5 C IIO IIB VICR Common Mode Input Voltage V Figure 7 V IO Input Offset Voltage V µ I IB /I IO Input Bias / Offset Current pa I IB /I IO Input Bias / Offset Current pa 3 INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE VCC = 5 V TA = 5 C VICR Common-Mode Input Voltage V Figure INPUT BIAS / OFFSET CURRENT COMMON MODE INPUT VOLTAGE VCC =.7 V TA = 5 C IIO IIB VICR Common Mode Input Voltage V Figure 5 INPUT BIAS / OFFSET CURRENT FREE-AIR TEMPERATURE VCC = V VIC = 7.5 V IIO IIB TA Free-Air Temperature C Figure 8 V IO Input Offset Voltage V µ I IB /I IO Input Bias / Offset Current pa I IB /I IO Input Bias / Offset Current pa INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE VCC = V TA = 5 C VICR Common-Mode Input Voltage V Figure 3 INPUT BIAS / OFFSET CURRENT FREE-AIR TEMPERATURE VCC = 5 V VIC =.5 V IIO IIB TA Free-Air Temperature C Figure 6 INPUT BIAS / OFFSET CURRENT COMMON-MODE INPUT VOLTAGE VCC = V TA = 5 C IIO IIB VICR Common-Mode Input Voltage V Figure 9 8 POST OFFICE BOX DALLAS, TEXAS 7565

9 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER TYPICAL CHARACTERISTICS CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO FREQUENCY VCC=.7, 5, V RF= kω RI= kω k k f Frequency Hz Figure V OH High-Level Output Voltage V HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT VCC =.7 V TA = 4 C TA = C TA = 5 C TA = 7 C TA = 5 C. 5 5 IOH High-Level Output Current µa Figure V OL Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VCC =.7 V TA =5 C TA = C TA = 4 C TA = 7 C TA = 5 C 5 5 IOL Low-Level Output Current µa Figure HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT V OH High-Level Output Voltage V VCC = 5 V T A = 4 C TA = C TA = 5 C TA = 7 C TA = 5 C V OL Low-Level Output Voltage V VCC = 5 V TA = C TA = 4 C TA = 5 C TA = 7 C TA = 5 C 5 5 V OH High-Level Output Voltage V TA = C TA = 5 C TA = 7 C TA = 5 C TA = 4 C VCC = V IOH High-Level Output Current µa Figure 3 IOL Low-Level Output Current µa Figure 4 IOH High-Level Output Current µa Figure 5 V OL Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VCC = V TA = 4 C TA = C TA = 5 C TA = 7 C TA = 5 C 5 5 IOL Low-Level Output Current µa Figure 6 Output voltage Peak to Peak V V O(PP) OUTPUT VOLTAGE PEAK-TO-PEAK FREQUENCY VCC = 5 V VCC =.7 V VCC = V RL = kω CL = pf TA = 5 C k f Frequency Hz Figure 7 Z o Output Impedance Ω k k OUTPUT IMPEDANCE FREQUENCY AV= AV= VCC=.7, 5, V TA=5 C k k f Frequency Hz Figure 8 POST OFFICE BOX DALLAS, TEXAS

10 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER TYPICAL CHARACTERISTICS I CC Supply Current µ A/Ch SUPPLY CURRENT SUPPLY VOLTAGE.6 TA = 5 C.4 TA = 7 C TA =5 C TA = C. AV = TA = 4 C VIN = VCC / VCC Supply Voltage V Figure 9 PSRR Power Supply Rejection Ratio db POWER SUPPLY REJECTION RATIO FREQUENCY VCC =.7, 5, & V TA = 5 C k k f Frequency Hz Figure Differential Voltage Gain db A VD DIFFERENTIAL VOLTAGE GAIN AND PHASE FREQUENCY VCC=.7, 5, V RL=5 kω CL= pf TA=5 C 45 k k f Frequency Hz Figure 9 45 Phase GBWP Gain Bandwidth Product khz GAIN BANDWIDTH PRODUCT SUPPLY VOLTAGE TA = 5 C RL = kω CL = pf f = khz VCC Supply Voltage V Figure SLEW RATE FREE-AIR TEMPERATURE PHASE MARGIN CAPACITIVE LOAD SR+ 7 SR Slew Rate V/ ms VCC = 5, V SR VCC =.7 V VCC =.7, 5, V Phase Margin VCC =.7, 5, & V RL= 5 kω TA = 5 C TA Free-Air Temperature C Figure 3 k k CL Capacitive Load pf Figure 4 POST OFFICE BOX DALLAS, TEXAS 7565

11 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER TYPICAL CHARACTERISTICS GAIN MARGIN CAPACITIVE LOAD VOLTAGE NOISE OVER A SECOND PERIOD Gain Margin db RL= 5 kω TA = 5 C VCC = V VCC =.7, 5 V Input Referred Voltage Noise V µ VCC = 5 V f =. Hz to Hz TA = 5 C k k CL Capacitive Load pf Figure t Time s Figure LARGE SIGNAL FOLLOWER PULSE RESPONSE LARGE SIGNAL FOLLOWER PULSE RESPONSE V IN Input Voltage V 3 VIN VO t Time ms VCC =.7 V AV = RL = kω CL = pf TA = 5 C V O Output Voltage V V IN Input Voltage V VIN VO t Time ms VCC = 5 V AV = RL = kω CL = pf TA = 5 C 4 3 V O Output Voltage V Figure 7 Figure 8 LARGE SIGNAL FOLLOWER PULSE RESPONSE SMALL SIGNAL FOLLOWER PULSE RESPONSE V IN Input Voltage V VIN VO VCC = V AV = RL = kω CL = pf TA = 5 C t Time ms Figure V O Output Voltage V V IN Input Voltage mv VIN VO t Time µs Figure 3 VCC =.7, 5, & V AV = RL = kω 8 CL = pf TA = 5 C 6 4 V O Output Voltage mv POST OFFICE BOX DALLAS, TEXAS 7565

12 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER TYPICAL CHARACTERISTICS V IN Input Voltage V V IN Input Voltage V LARGE SIGNAL INVERTING PULSE RESPONSE VIN VCC =.7 V.5 AV = RL = kω. CL = pf TA = 5 C.5 VO t Time ms Figure 3 LARGE SIGNAL INVERTING PULSE RESPONSE 9 68 VIN 36 4 VCC = V 3 AV = RL = kω CL = pf TA = 5 C VO t Time ms Figure 33 V O Output Voltage V V O Output Voltage V V IN Input Voltage V V IN Input Voltage mv LARGE SIGNAL INVERTING PULSE RESPONSE VIN VCC = 5 V AV = RL = kω CL = pf TA = 5 C VO t Time ms Figure 3 SMALL SIGNAL INVERTING PULSE RESPONSE VIN VCC =.7, 5, & V AV = RL = kω CL = pf TA = 5 C VO t Time ms Figure V O Output Voltage V V O Output Voltage mv Crosstalk db VCC =.7, 5, & V All Channels RL = kω CL = pf VIN = VPP VCC =.7, 5 V CROSSTALK FREQUENCY VCC = V 4 k k f Frequency Hz Figure 35 POST OFFICE BOX DALLAS, TEXAS 7565

13 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER APPLICATION INFORMATION offset voltage The output offset voltage, (V OO ) is the sum of the input offset voltage (V IO ) and both input bias currents (I IB ) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF RG IIB V OO V IO.. R F R G.. I IB R S.. R F R G.. I IB R F RS VI + + VO IIB+ Figure 36. Output Offset Voltage Model general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 37). RG RF f 3dB RC VI R C + VO V O V I. R F R G.. src. Figure 37. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. VI R R C C + _ R = R = R C = C = C Q = Peaking Factor (Butterworth Q =.77) f 3dB RC RG RF RG = ( RF Q ) Figure 38. -Pole Low-Pass Sallen-Key Filter POST OFFICE BOX DALLAS, TEXAS

14 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER circuit layout considerations APPLICATION INFORMATION To achieve the levels of high performance of the TLV4x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. Ground planes It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling Use a 6.8-µF tantalum capacitor in parallel with a.-µf ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a.-µf ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the.-µf capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than. inches between the device power terminals and the ceramic capacitors. Sockets Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. Surface-mount passive components Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. 4 POST OFFICE BOX DALLAS, TEXAS 7565

15 general power dissipation considerations TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER APPLICATION INFORMATION For a given θ JA, the maximum power dissipation is shown in Figure 39 and is calculated by the following formula: P D. T MAX T A JA. Where: P D = Maximum power dissipation of THS4x IC (watts) T MAX = Absolute maximum junction temperature (5 C) T A = Free-ambient air temperature ( C) θ JA = θ JC + θ CA θ JC = Thermal coefficient from junction to case θ CA = Thermal coefficient from case to ambient air ( C/W) Maximum Power Dissipation W MAXIMUM POWER DISSIPATION FREE-AIR TEMPERATURE SOIC Package Low-K Test PCB θ JA = 76 C/W PDIP Package Low-K Test PCB θ JA = 4 C/W T J = 5 C MSOP Package Low-K Test PCB θ JA = 6 C/W.5 SOT-3 Package Low-K Test PCB θ JA = 34 C/W TA Free-Air Temperature C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 39. Maximum Power Dissipation Free-Air Temperature POST OFFICE BOX DALLAS, TEXAS

16 TLV4, TLV4, TLV44 FAMILY OF -µa/ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS SLOS39C JULY REVISED - NOVEMBER macromodel information APPLICATION INFORMATION Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note ) and subcircuit in Figure 4 are generated using the TLV4x typical electrical and operating characteristics at T A = 5 C. Using this information, output simulations of the following key parameters can be generated to a tolerance of % (in most cases): Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit NOTE : G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 353 (974) VCC+ + rp rc rc ree cee egnd fb ro c 7 + c IN+ + vlim 9 r 6 vc 8 IN q q + vb ga gcm ioff ro dp re re dlp dln VOUT iee VCC ve de.subckt 4X_5V X * c E c E cee E dc 5 53 dy de 54 5 dy dlp 9 9 dx dln 9 9 dx dp 4 3 dx egnd 99 poly() (3,) (4,).5.5 fb 7 99 poly(5) vb vc ve vlp vln 6.44E6 E3 E3 6E6 6E6 ga 6.6E 6 gcm E iee 4 dc 54.54E 9 ioff 6 dc 5e hlim 9 vlim K q 3 qx q 4 qx r 6 9.E3 dc + vlp + hlim vln + rc E3 rc E3 re E3 re E3 ree E9 ro 8 5 ro 7 99 rp E6 vb 9 dc vc 3 53 dc.8835 ve 54 4 dc.8835 vlim 7 8 dc vlp 9 dc 54 vln 9 dc 54.model dx D(Is=8.E 8).model dy D(Is=8.E 8 Rs=m Cjo=p).model qx NPN(Is=8.E 8 Bf=7.7E).model qx NPN(Is=8.E 8 Bf=7.7E).ends Figure 4. Boyle Macromodels and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. 6 POST OFFICE BOX DALLAS, TEXAS 7565

17 PACKAGE OPTION ADDENDUM 4-Aug-8 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan TLV4ID ACTIVE SOIC D 8 75 Green (RoHS TLV4IDBVR ACTIVE SOT-3 DBV 5 3 Green (RoHS TLV4IDBVRG4 ACTIVE SOT-3 DBV 5 3 Green (RoHS TLV4IDBVT ACTIVE SOT-3 DBV 5 5 Green (RoHS TLV4IDR ACTIVE SOIC D 8 5 Green (RoHS TLV4IP ACTIVE PDIP P 8 5 Green (RoHS TLV4CD ACTIVE SOIC D 8 75 Green (RoHS TLV4CDR ACTIVE SOIC D 8 5 Green (RoHS TLV4ID ACTIVE SOIC D 8 75 Green (RoHS TLV4IDGK ACTIVE VSSOP DGK 8 8 Green (RoHS TLV4IDGKR ACTIVE VSSOP DGK 8 5 Green (RoHS TLV4IDGKRG4 ACTIVE VSSOP DGK 8 5 Green (RoHS TLV4IDR ACTIVE SOIC D 8 5 Green (RoHS TLV4IP ACTIVE PDIP P 8 5 Green (RoHS TLV44CD ACTIVE SOIC D 4 5 Green (RoHS TLV44ID ACTIVE SOIC D 4 5 Green (RoHS TLV44IDR ACTIVE SOIC D 4 5 Green (RoHS () Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/5) CU NIPDAU Level--6C-UNLIM -4 to 5 4I CU NIPDAU Level--6C-UNLIM -4 to 5 VBEI CU NIPDAU Level--6C-UNLIM -4 to 5 VBEI CU NIPDAU Level--6C-UNLIM -4 to 5 VBEI CU NIPDAU Level--6C-UNLIM -4 to 5 4I CU NIPDAU N / A for Pkg Type -4 to 5 TLV4I CU NIPDAU Level--6C-UNLIM to 7 4C CU NIPDAU Level--6C-UNLIM to 7 4C CU NIPDAU Level--6C-UNLIM -4 to 5 4I CU NIPDAU Level--6C-UNLIM -4 to 5 ALE CU NIPDAU Level--6C-UNLIM -4 to 5 ALE CU NIPDAU Level--6C-UNLIM -4 to 5 ALE CU NIPDAU Level--6C-UNLIM -4 to 5 4I CU NIPDAU N / A for Pkg Type -4 to 5 TLV4I CU NIPDAU Level--6C-UNLIM to 7 TLV44C CU NIPDAU Level--6C-UNLIM -4 to 5 TLV44I CU NIPDAU Level--6C-UNLIM -4 to 5 TLV44I Samples Addendum-Page

18 PACKAGE OPTION ADDENDUM 4-Aug-8 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan TLV44IN ACTIVE PDIP N 4 5 Green (RoHS TLV44IPW ACTIVE TSSOP PW 4 9 Green (RoHS TLV44IPWR ACTIVE TSSOP PW 4 Green (RoHS () Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/5) CU NIPDAU N / A for Pkg Type -4 to 5 TLV44I CU NIPDAU Level--6C-UNLIM -4 to 5 44I CU NIPDAU Level--6C-UNLIM -4 to 5 44I Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all RoHS substances, including the requirement that RoHS substance do not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS79B low halogen requirements of <=ppm threshold. Antimony trioxide based flame retardants must also meet the <=ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

19 PACKAGE OPTION ADDENDUM 4-Aug-8 Addendum-Page 3

20 PACKAGE MATERIALS INFORMATION -Oct-8 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A (mm) B (mm) K (mm) P (mm) W (mm) Pin Quadrant TLV4IDBVR SOT-3 DBV Q3 TLV4IDBVT SOT-3 DBV Q3 TLV4IDR SOIC D Q TLV4CDR SOIC D Q TLV4IDGKR VSSOP DGK Q TLV4IDR SOIC D Q TLV44IDR SOIC D Q TLV44IPWR TSSOP PW Q Pack Materials-Page

21 PACKAGE MATERIALS INFORMATION -Oct-8 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV4IDBVR SOT-3 DBV TLV4IDBVT SOT-3 DBV TLV4IDR SOIC D TLV4CDR SOIC D TLV4IDGKR VSSOP DGK TLV4IDR SOIC D TLV44IDR SOIC D TLV44IPWR TSSOP PW Pack Materials-Page

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23 SCALE 4. PACKAGE OUTLINE DBV5A SOT mm max height SMALL OUTLINE TRANSISTOR C C PIN INDEX AREA B A.45 MAX 5.9 X X C A B 4 (.).5 TYP..5 GAGE PLANE. TYP.8 8 TYP.6 TYP.3 SEATING PLANE 44839/C 4/7 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y4.5M.. This drawing is subject to change without notice. 3. Refernce JEDEC MO-78.

24 DBV5A EXAMPLE BOARD LAYOUT SOT mm max height SMALL OUTLINE TRANSISTOR 5X (.) PKG 5X (.6) 5 SYMM (.9) X (.95) 3 4 (R.5) TYP (.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:5X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL.7 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED).7 MIN ARROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 44839/C 4/7 NOTES: (continued) 4. Publication IPC-735 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

25 DBV5A EXAMPLE STENCIL DESIGN SOT mm max height SMALL OUTLINE TRANSISTOR 5X (.6) 5X (.) PKG 5 X(.95) SYMM (.9) 3 4 (R.5) TYP (.6) SOLDER PASTE EXAMPLE BASED ON.5 mm THICK STENCIL SCALE:5X 44839/C 4/7 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-755 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design.

26 SCALE 4. PACKAGE OUTLINE DBV5A SOT mm max height SMALL OUTLINE TRANSISTOR C C PIN INDEX AREA B A.45 MAX 5.9 X X C A B 4 (.).5 TYP..5 GAGE PLANE. TYP.8 8 TYP.6 TYP.3 SEATING PLANE 44839/C 4/7 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y4.5M.. This drawing is subject to change without notice. 3. Refernce JEDEC MO-78.

27 DBV5A EXAMPLE BOARD LAYOUT SOT mm max height SMALL OUTLINE TRANSISTOR 5X (.) PKG 5X (.6) 5 SYMM (.9) X (.95) 3 4 (R.5) TYP (.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:5X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL.7 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED).7 MIN ARROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 44839/C 4/7 NOTES: (continued) 4. Publication IPC-735 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

28 DBV5A EXAMPLE STENCIL DESIGN SOT mm max height SMALL OUTLINE TRANSISTOR 5X (.6) 5X (.) PKG 5 X(.95) SYMM (.9) 3 4 (R.5) TYP (.6) SOLDER PASTE EXAMPLE BASED ON.5 mm THICK STENCIL SCALE:5X 44839/C 4/7 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-755 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design.

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