TLC070, TLC071, TLC072, TLC073, TLC074, TLC075, TLC07xA FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY OPERATIONAL AMPLIFIERS

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1 Wide Bandwidth... MHz High Output Drive I OH... 7 ma at V DD. V I OL... ma at. V High Slew Rate SR V/µs SR... 9 V/µs Wide Supply Range.... V to 6 V Supply Current....9 ma/channel Ultralow Power Shutdown Mode I DD... µa/channel Low Input Noise Voltage...7 nv Hz Input Offset Voltage...6 µv Ultra-Small Packages 8 or Pin MSOP (TLC7///3) description TLC7, TLC7, TLC7, TLC73, TLC7, TLC7, TLC7xA Operational Amplifier The first members of TI s new BiMOS general-purpose operational amplifier family are the TLC7x. The BiMOS family concept is simple: provide an upgrade path for BiFET users who are moving away from dual-supply to single-supply systems and demand higher ac and dc performance. With performance rated from. V to 6 V across commercial ( C to 7 C) and an extended industrial temperature range ( C to C), BiMOS suits a wide range of audio, automotive, industrial and instrumentation applications. Familiar features like offset nulling pins, and new features like MSOP PowerPAD packages and shutdown modes, enable higher levels of performance in a variety of applications. Developed in TI s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input impedance low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum performance features of both. AC performance improvements over the TL7x BiFET predecessors include a bandwidth of MHz (an increase of 3%) and voltage noise of 7 nv/ Hz (an improvement of 6%). DC improvements include a factor of reduction in input offset voltage down to. mv (maximum) in the standard grade, and a power supply rejection improvement of greater than db to 3 db. Added to this list of impressive features is the ability to drive ±-ma loads comfortably from an ultrasmall-footprint MSOP PowerPAD package, which positions the TLC7x as the ideal high-performance general-purpose operational amplifier family. FAMILY PACKAGE TABLE DEVICE NO. OF PACKAGE TYPES UNIVERSAL SHUTDOWN CHANNELS MSOP PDIP SOIC TSSOP EVM BOARD TLC Yes TLC TLC Refer to the EVM Selection Guide TLC73 Yes (Lit# SLOU6) TLC7 TLC7 6 6 Yes + Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Instruments Incorporated POST OFFICE BOX 633 DALLAS, TEXAS 76

2 TLC7 and TLC7 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE SMALL OUTLINE SYMBOL (D) (DGN) C to 7 C C to C TLC7CD TLC7CD TLC7ID TLC7ID TLC7AID TLC7AID TLC7CDGN TLC7CDGN TLC7IDGN TLC7IDGN xxtiacs xxtiacu xxtiact xxtiacv PLASTIC DIP (P) TLC7CP TLC7CP TLC7IP TLC7IP TLC7AIP TLC7AIP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC7CDR). TA C to 7 C C to C TLC7 and TLC73 AVAILABLE OPTIONS PACKAGED DEVICES SMALL MSOP OUTLINE (D) (DGN) SYMBOL (DGQ) SYMBOL TLC7CD TLC73CD TLC7ID TLC73ID TLC7AID TLC73AID TLC7CDGN TLC7IDGN xxtiadv xxtiadw TLC73CDGQ TLC73IDGQ xxtiadx xxtiady PLASTIC DIP (N) TLC73CN TLC73IN TLC73AIN This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC7CDR). xx represents the device date code. PLASTIC DIP (P) TLC7CP TLC7IP TLC7AIP TA C to 7 C C to C TLC7 and TLC7 AVAILABLE OPTIONS PACKAGED DEVICES SMALL OUTLINE (D) TLC7CD TLC7CD TLC7ID TLC7ID TLC7AID TLC7AID PLASTIC DIP (N) TLC7CN TLC7CN TLC7IN TLC7IN TLC7AIN TLC7AIN TSSOP (PWP) TLC7CPWP TLC7CPWP TLC7IPWP TLC7IPWP TLC7AIPWP TLC7AIPWP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC7CDR). POST OFFICE BOX 633 DALLAS, TEXAS 76

3 TLC7x PACKAGE PINOUTS TLC7 D, DGN OR P PACKAGE (TOP VIEW) TLC7 D, DGN OR P PACKAGE (TOP VIEW) TLC7 D, DGN, OR P PACKAGE (TOP VIEW) NULL IN IN+ GND SHDN V DD OUT NULL NULL IN IN+ GND NC V DD OUT NULL OUT IN IN+ GND V DD OUT IN IN+ TLC73 DGQ PACKAGE (TOP VIEW) TLC73 D OR N PACKAGE (TOP VIEW) TLC7 D OR N PACKAGE (TOP VIEW) OUT IN IN+ GND SHDN V DD OUT IN IN+ SHDN OUT IN IN+ GND NC SHDN NC V DD OUT IN IN+ NC SHDN NC OUT IN IN+ V DD IN+ IN OUT OUT IN IN+ GND 3IN+ 3IN 3OUT TLC7 PWP PACKAGE (TOP VIEW) TLC7 D OR N PACKAGE (TOP VIEW) TLC7 PWP PACKAGE (TOP VIEW) OUT IN IN+ VDD IN+ IN OUT NC NC NC OUT IN IN+ GND 3IN+ 3IN 3OUT NC NC NC OUT IN IN+ V DD IN+ IN OUT /SHDN OUT IN IN+ GND 3IN+ 3IN 3OUT 3/SHDN OUT IN IN+ VDD IN+ IN OUT /SHDN NC NC OUT IN IN+ GND 3IN+ 3IN 3OUT 3/SHDN NC NC NC No internal connection POST OFFICE BOX 633 DALLAS, TEXAS 76 3

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V DD (see Note ) V Differential input voltage range, V ID ±V DD Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : C suffix C to 7 C I suffix C to C Maximum junction temperature, T J C Storage temperature range, T stg C to C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltage values, except differential voltages, are with respect to GND. PACKAGE recommended operating conditions Supply voltage, VDD DISSIPATION RATING TABLE θjc ( C/W) θja ( C/W) TA C POWER RATING D (8) mw D () mw D (6) mw DGN (8) W DGQ () W N (, 6) mw P (8) mw PWP () W MIN MAX UNIT Single supply. 6 V Split supply ±. ±8 Common-mode input voltage, VICR +. VDD.8 V Shutdown on/off voltage level Operating free-air temperature, TA Relative to the voltage on the GND terminal of the device. VIH VOL.8 C-suffix 7 I-suffix V C POST OFFICE BOX 633 DALLAS, TEXAS 76

5 electrical characteristics at specified free-air temperature, V DD = V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT V, VIO Input offset voltage VDD = VIC =. V, VO =. V, RS = Ω αvio IIO IIB VICR Temperature coefficient of input offset voltage Input offset current Input bias current Common-mode mode input voltage VDD =V V, VIC =. V, VO =. V, RS = Ω VOH High-level output voltage VIC =. V VOL Low-level output voltage VIC =. V IOS Short-circuit output current TLC7///3 TLC7///3A TLC7/ TLC7/A TLC7XC TLC7XI TLC7XC TLC7XI C 6 Full range C 7 Full range C 39 9 Full range 3 C 39 Full range µv. µv/ C C.7 Full range pa 7 C. Full range CMRR > 7 db, RS = Ω C. to. CMRR > db, RS = Ω Full range. to. IOH = ma C..3 Full range 3.9 IOH = ma IOH = 3 ma IOH = ma IOL =ma IOL =ma IOL =3mA IOL = ma C 3.7 Full range 3. pa 7 C V Full range 3. C C to 8 C 3 C.8. Full range.3 C.3.39 Full range. C.3. V Full range.7 C.8.63 C to 8 C Sourcing C Sinking C VOH =. V from positive rail C 7 IO Output current VOL =. V from negative rail C Full range is C to 7 C for C suffix and C to C for I suffix. If not specified, full range is C to C..7 V ma ma POST OFFICE BOX 633 DALLAS, TEXAS 76

6 electrical characteristics at specified free-air temperature, V DD = V (unless otherwise noted) (continued) AVD PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Large-signal g differential voltage amplification VO(PP) =3V V, RL = kω C Full range ri(d) Differential input resistance C GΩ CIC Common-mode input capacitance f = khz C.9 pf zo Closed-loop output impedance f = khz, AV = C. Ω CMRR Common-mode mode rejection ratio VIC = to 3 V, RS = Ω ksvr C Full range Supply voltage rejection ratio VDD =. V to 6 V, VIC = VDD /, C 9 3 ( VDD / VIO) No load Full range 9 IDD Supply current (per channel) VO =. V, No load C.9. Full range 3. Supply current in shutdown C IDD(SHDN) mode (per channel) SHDN 8V.8 (TLC7, TLC73, TLC7) Full range Full range is C to 7 C for C suffix and C to C for I suffix. If not specified, full range is C to C. db db db ma µa 6 POST OFFICE BOX 633 DALLAS, TEXAS 76

7 operating characteristics at specified free-air temperature, V DD = V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VO(PP) =.8 V, CL = pf, C 6 SR+ Positive slew rate at unity gain RL = kω Full range 9. VO(PP) =.8 V, CL = pf, C. 9 SR Negative slew rate at unity gain RL = kω Full range Vn Equivalent input noise voltage f = Hz C f = khz C 7 V/µs V/µs nv/ Hz In Equivalent input noise current f = khz C.6 fa / Hz THD + N t(on) t(off) ts φm Total harmonic distortion plus noise Amplifier turnon time Amplifier turnoff time 3V, AV =.% VO(PP) = RL = kω and Ω, AV = C.% f = khz AV =.8% RL =kω C. µs C.3 µs Gain-bandwidth product f = khz, RL = kω C MHz Settling time Phase margin Gain margin V(STEP)PP = V, AV =, CL = pf, RL = kω V(STEP)PP = V, AV V =, CL = 7 pf, RL = kω RL = kω, RL = kω, RL = kω, RL = kω,.%.8.%.% C.39.8.%.39 CL = pf CL = pf CL = pf CL = pf Full range is C to 7 C for C suffix and C to C for I suffix. If not specified, full range is C to C. Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. C C µs db POST OFFICE BOX 633 DALLAS, TEXAS 76 7

8 electrical characteristics at specified free-air temperature, V DD = V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VIO Input offset voltage VDD = V VIC = 6 V, VO = 6 V, RS = Ω αvio IIO IIB VICR Temperature coefficient of input offset voltage Input offset current Input bias current Common-mode mode input voltage VDD =V VIC = 6 V, VO = 6 V, RS = Ω VOH High-level output voltage VIC = 6 V VOL Low-level output voltage VIC = 6 V IOS Short-circuit output current TLC7///3 TLC7///3A TLC7/ TLC7/A TLC7xC TLC7xI TLC7xC TLC7xI C 6 Full range C 7 Full range C 39 9 Full range 3 C 39 Full range µv. µv/ C C.7 Full range pa 7 C. Full range CMRR > 7 db, RS = Ω C. to. CMRR > db, RS = Ω Full range. to. IOH = ma C.. Full range IOH = ma IOH = 3 ma IOH = ma IOL =ma IOL =ma IOL =3mA IOL = ma C.8.9 Full range.7 pa 7 C.6.7 V Full range.3 C.. C to 8 C.3 C.7. Full range.3 C.3. Full range. C.. V Full range.6 C..6 C to 8 C Sourcing C Sinking C VOH =. V from positive rail C 7 IO Output current VOL =. V from negative rail C Full range is C to 7 C for C suffix and C to C for I suffix. If not specified, full range is C to C..6 V ma ma 8 POST OFFICE BOX 633 DALLAS, TEXAS 76

9 electrical characteristics at specified free-air temperature, V DD = V (unless otherwise noted) (continued) AVD PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT Large-signal g differential voltage amplification VO(PP) =8V V, RL = kω C Full range ri(d) Differential input resistance C GΩ CIC Common-mode input capacitance f = khz C.6 pf zo Closed-loop output impedance f = khz, AV = C. Ω CMRR Common-mode mode rejection ratio VIC = to V, RS = Ω ksvr C Full range Supply voltage rejection ratio VDD =. V to 6 V, VIC = VDD /, C 9 3 ( VDD / VIO) No load Full range 9 IDD Supply current (per channel) VO = 7. V, No load C..9 Full range 3. Supply current in shutdown C IDD(SHDN) mode (TLC7, TLC73, SHDN.8 V TLC7) (per channel) Full range Full range is C to 7 C for C suffix and C to C for I suffix. If not specified, full range is C to C. db db db ma µa POST OFFICE BOX 633 DALLAS, TEXAS 76 9

10 operating characteristics at specified free-air temperature, V DD = V (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VO(PP) = V, CL = pf, C 6 SR+ Positive slew rate at unity gain RL = kω Full range 9. VO(PP) = V, CL = pf, C. 9 SR Negative slew rate at unity gain RL = kω Full range Vn Equivalent input noise voltage f = Hz C f = khz C 7 V/µs V/µs nv/ Hz In Equivalent input noise current f = khz C.6 fa / Hz THD + N t(on) t(off) ts φm Total harmonic distortion plus noise Amplifier turnon time Amplifier turnoff time 8V, AV =.% VO(PP) = RL = kω and Ω, AV = C.% f = khz AV =.% RL =kω C.7 µs C. µs Gain-bandwidth product f = khz, RL = kω C MHz Settling time Phase margin Gain margin V(STEP)PP = V, AV =, CL = pf, RL = kω V(STEP)PP = V, AV V =, CL = 7 pf, RL = kω RL = kω, RL = kω, RL = kω, RL = kω,.%.7.%.% C..7.%.9 CL = pf CL = pf CL = pf CL = pf Full range is C to 7 C for C suffix and C to C for I suffix. If not specified, full range is C to C. Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. C C µs db POST OFFICE BOX 633 DALLAS, TEXAS 76

11 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Common-mode input voltage, IIO Input offset current Free-air temperature 3, IIB Input bias current Free-air temperature 3, VOH High-level output voltage High-level output current, 7 VOL Low-level output voltage Low-level output current 6, 8 Zo Output impedance Frequency 9 IDD Supply current Supply voltage PSRR Power supply rejection ratio Frequency CMRR Common-mode rejection ratio Frequency Vn Equivalent input noise voltage Frequency 3 VO(PP) Peak-to-peak output voltage Frequency, Crosstalk Frequency 6 Differential voltage gain Frequency 7, 8 Phase Frequency 7, 8 φm Phase margin Load capacitance 9, SR THD+N Gain margin Load capacitance, Gain-bandwidth product Supply voltage 3 Slew rate Supply voltage Free-air temperature, 6 Total harmonic distortion plus noise Frequency 7, 8 Peak-to-peak output voltage 9, 3 Large-signal follower pulse response 3, 3 Small-signal follower pulse response 33 Large-signal inverting pulse response 3, 3 Small-signal inverting pulse response 36 Shutdown forward isolation Frequency 37, 38 Shutdown reverse isolation Frequency 39, Shutdown supply current Supply voltage Free-air temperature Shutdown pulse 3, POST OFFICE BOX 633 DALLAS, TEXAS 76

12 TYPICAL CHARACTERISTICS V IO Input Offset Voltage µ V INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE VDD = V TA = C VICR Common-Mode Input Voltage V Figure V IO Input Offset Voltage µ V INPUT OFFSET VOLTAGE COMMON-MODE INPUT VOLTAGE VDD = V TA = C VICR Common-Mode Input Voltage V Figure / I IO Input Bias and Input Offset Current pa I IB 6 8 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT FREE-AIR TEMPERATURE VDD = V TA Free Air Temperature C Figure 3 IIB IIO / I IO Input Bias and Input Offset Current pa I IB 6 8 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT FREE-AIR TEMPERATURE VDD = V TA Free-Air Temperature C Figure IIO IIB V OH High-Level Output Voltage V HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT VDD = V TA = C TA = 7 C TA = C. 3 3 IOH - High-Level Output Current - ma Figure V OL Low-Level Output Voltage V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VDD = V TA = C TA = 7 C TA = C 3 3 IOL - Low-Level Output Current - ma Figure 6. HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT. LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT OUTPUT IMPEDANCE FREQUENCY V OH High-Level Output Voltage V TA = C TA = 7 C TA = C VDD = V IOH - High-Level Output Current - ma Figure 7 V OL Low-Level Output Voltage V TA = C TA = 7 C TA = C. VDD = V. 3 3 IOL - Low-Level Output Current - ma Figure 8 Z o Output Impedance Ω.. k VDD = V and V AV = AV = AV = k k f - Frequency - Hz Figure 9 M M POST OFFICE BOX 633 DALLAS, TEXAS 76

13 TYPICAL CHARACTERISTICS I DD Supply Current ma TA = C SUPPLY CURRENT SUPPLY VOLTAGE TA = 7 C TA = C. AV = SHDN = VDD Per Channel VDD Supply Voltage - V Figure Power Supply Rejection Ratio db PSRR POWER SUPPLY REJECTION RATIO FREQUENCY 8 6 VDD = V k VDD = V k f Frequency Hz Figure k M M CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO FREQUENCY 8 6 k VDD = V and V k k M M f - Frequency - Hz Figure nv/ Hz V n Equivalent Input Noise Voltage EQUIVALENT INPUT NOISE VOLTAGE FREQUENCY 3 3 VDD = V VDD = V k k f Frequency Hz Figure 3 k V O(PP) Peak-to-Peak Output Voltage V 8 6 k PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY VDD = V VDD = V THD+N < = % RL = 6 Ω k M M f - Frequency - Hz Figure V O(PP) Peak-to-Peak Output Voltage V 8 6 k PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY VDD = V VDD = V THD+N < = % RL = kω k M M f - Frequency - Hz Figure Crosstalk db 6 8 CROSSTALK FREQUENCY VDD = V and V AV = RL = kω VI(PP) = V For All Channels 6 k k f Frequency Hz Figure 6 k POST OFFICE BOX 633 DALLAS, TEXAS 76 3

14 TYPICAL CHARACTERISTICS DIFFERENTIAL VOLTAGE GAIN AND PHASE FREQUENCY 8 DIFFERENTIAL VOLTAGE GAIN AND PHASE FREQUENCY 8 Different Voltage Gain db A VD k k Gain VDD = ±. V RL = kω CL = pf k M f Frequency Hz Figure 7 Phase M M Phase Different Voltage Gain db A VD k k Gain VDD = ±6 V RL = kω CL = pf k M f Frequency Hz Figure 8 Phase M M Phase 3 PHASE MARGIN LOAD CAPACITANCE Rnull = Ω Rnull = Ω PHASE MARGIN LOAD CAPACITANCE Rnull = Ω 3. GAIN MARGIN LOAD CAPACITANCE Rnull = Ω φ m Phase Margin 3 VDD = V RL = kω Rnull = Ω Rnull = Ω φ m Phase Margin 3 3 Rnull = Ω VDD = V RL = kω Rnull = Ω Rnull = Ω G Gain Margin db 3... VDD = V RL = kω Rnull = Ω Rnull = Ω Rnull = Ω CL Load Capacitance pf Figure 9 CL Load Capacitance pf Figure CL Load Capacitance pf Figure φ m Phase Margin db GAIN MARGIN LOAD CAPACITANCE Rnull = Ω VDD = V RL = kω Rnull = Ω Rnull = Ω Rnull = Ω CL Load Capacitance pf Figure GBWP - Gain Bandwidth Product - MHz GAIN BANDWIDTH PRODUCT SUPPLY VOLTAGE CL = pf RL = 6 Ω RL = kω VDD - Supply Voltage - V Figure 3 SR Slew Rate V/ µ s SLEW RATE SUPPLY VOLTAGE RL = 6 Ω and kω CL = pf AV = Slew Rate Slew Rate VDD - Supply Voltage - V Figure POST OFFICE BOX 633 DALLAS, TEXAS 76

15 TYPICAL CHARACTERISTICS SR Slew Rate V/ µ s SLEW RATE FREE-AIR TEMPERATURE Slew Rate Slew Rate + VDD = V RL = 6 Ω and kω CL = pf AV = SR Slew Rate V/ µ s SLEW RATE FREE-AIR TEMPERATURE Slew Rate + VDD = V RL = 6 Ω and kω CL = pf AV = Slew Rate Total Harmonic Distortion + Noise %. TOTAL HARMONIC DISTORTION PLUS NOISE FREQUENCY. AV = AV = AV = VDD = V RL = kω VO(PP) = V TA - Free-Air Temperature - C Figure TA - Free-Air Temperature - C Figure 6. k k f Frequency Hz Figure 7 k Total Harmonic Distortion + Noise %.. TOTAL HARMONIC DISTORTION PLUS NOISE FREQUENCY AV = AV = AV =. k k f Frequency Hz Figure 8 VDD = V RL = kω VO(PP) = V LARGE SIGNAL FOLLOWER PULSE RESPONSE k Total Harmonic Distortion + Noise % TOTAL HARMONIC DISTORTION PLUS NOISE PEAK-TO-PEAK OUTPUT VOLTAGE... VDD = V AV = f = khz RL = 6 Ω RL = Ω RL = kω VO(PP) Peak-to-Peak Output Voltage V Figure 9 LARGE SIGNAL FOLLOWER PULSE RESPONSE Total Harmonic Distortion + Noise % TOTAL HARMONIC DISTORTION PLUS NOISE PEAK-TO-PEAK OUTPUT VOLTAGE... VDD = V AV = f = khz VO(PP) Peak-to-Peak Output Voltage V Figure 3 RL = 6 Ω RL = Ω RL = kω SMALL SIGNAL FOLLOWER PULSE RESPONSE VI ( V/Div) VI ( V/Div) VI(mV/Div) Output Voltage V V O VO ( mv/div) VDD = V RL = 6 Ω and kω CL = 8 pf Output Voltage V V O VO ( V/Div) VDD = V RL = 6 Ω and kω CL = 8 pf V O Output Voltage V VO(mV/Div) VDD = V and V RL = 6 Ω and kω CL = 8 pf t Time µs Figure t Time µs Figure t Time µs Figure 33 POST OFFICE BOX 633 DALLAS, TEXAS 76

16 TYPICAL CHARACTERISTICS LARGE SIGNAL INVERTING PULSE RESPONSE LARGE SIGNAL INVERTING PULSE RESPONSE SMALL SIGNAL INVERTING PULSE RESPONSE Output Voltage V V O VI ( V/div) VDD = V RL = 6 Ω and kω CL = 8 pf Output Voltage V V O VI ( V/div) VDD = V RL = 6 Ω and kω CL = 8 pf Output Voltage V V O VI ( mv/div) VDD = & V RL = 6 Ω and kω CL = 8 pf VO ( mv/div) VO ( mv/div) VO ( V/Div) t Time µs Figure t Time µs Figure t Time µs Figure 36 Sutdown Forward Isolation - db 8 6 SHUTDOWN FORWARD ISOLATION FREQUENCY RL = kω VDD = V CL= pf VI(PP) =.,., and V RL = 6 Ω Sutdown Forward Isolation - db 8 6 SHUTDOWN FORWARD ISOLATION FREQUENCY RL = kω VDD = V CL= pf VI(PP) =., 8, and V RL = 6 Ω Sutdown Reverse Isolation - db 8 6 SHUTDOWN REVERSE ISOLATION FREQUENCY RL = kω VDD = V CL= pf VI(PP) =.,., and V RL = 6 Ω k k k M M f - Frequency - Hz Figure 37 M k k k M M f - Frequency - Hz Figure 38 M k k k M M f - Frequency - Hz Figure 39 M Sutdown Reverse Isolation - db 8 6 k SHUTDOWN REVERSE ISOLATION FREQUENCY RL = kω VDD = V CL= pf VI(PP) =., 8, and V RL = 6 Ω k k M M f - Frequency - Hz Figure M I DD(SHDN) Shutdown Supply Current - µ A SHUTDOWN SUPPLY CURRENT SUPPLY VOLTAGE Shutdown On RL = open VIN = VDD/ VDD - Supply Voltage - V Figure I DD(SHDN) Shutdown Supply Current - µ A SHUTDOWN SUPPLY CURRENT FREE-AIR TEMPERATURE AV = VIN = VDD/ VDD = V VDD = V TA - Free-Air Temperature - C Figure 6 POST OFFICE BOX 633 DALLAS, TEXAS 76

17 TYPICAL CHARACTERISTICS I DD Supply Current ma SHUTDOWN PULSE Shutdown Pulse VDD = V CL= 8 pf IDD RL = kω IDD RL = 6 Ω SD Off t - Time - µs Figure 3 6 Shutdown Pulse - V I DD Supply Current ma SHUTDOWN PULSE Shutdown Pulse VDD = V CL= 8 pf IDD RL = kω IDD RL = 6 Ω SD Off t - Time - µs Figure 6 Shutdown Pulse - V PARAMETER MEASUREMENT INFORMATION _ + Rnull RL CL Figure APPLICATION INFORMATION input offset voltage null circuit The TLC7 and TLC7 has an input offset nulling function. Refer to Figure 6 for the diagram. IN IN + N N kω + OUT R NOTE A: R =.6 kω for offset voltage adjustment of ± mv. R = kω for offset voltage adjustment of ±3 mv. VDD Figure 6. Input Offset Voltage Null Circuit POST OFFICE BOX 633 DALLAS, TEXAS 76 7

18 driving a capacitive load APPLICATION INFORMATION When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than pf, it is recommended that a resistor be placed in series (R NULL ) with the output of the amplifier, as shown in Figure 7. A minimum value of Ω should work well for most applications. RF Input RG _ + RNULL Output CLOAD Figure 7. Driving a Capacitive Load offset voltage The output offset voltage, (V OO ) is the sum of the input offset voltage (V IO ) and both input bias currents (I IB ) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF RG IIB RS VI + + VO IIB+ V OO V IO.. R F R G.. I IB R S.. R F R G.. I IB R F Figure 8. Output Offset Voltage Model 8 POST OFFICE BOX 633 DALLAS, TEXAS 76

19 high speed CMOS input amplifiers TLC7, TLC7, TLC7, TLC73, TLC7, TLC7, TLC7xA APPLICATION INFORMATION The TLC7x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance of the order of pf. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance. For example, a gain of, a source resistance of kω, and a feedback resistance of kω add an additional pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater input capacitance. This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their unity-gain bandwidth. However, the TLC7x with its -MHz bandwidth means that this pole normally occurs at frequencies where there is on the order of db gain left and the phase shift adds considerably. The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the feedback resistance is increased, the gain peaking increases at a lower frequency and the 8 phase shift crossover point also moves down in frequency, decreasing the phase margin. For the TLC7x, the maximum feedback resistor recommended is kω; larger resistances can be used but a capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance pole. The TLC73 with a -V step response has an 8% overshoot with a natural frequency of 3. MHz when configured as a unity gain buffer and with a -kω feedback resistor. By adding a -pf capacitor in parallel with the feedback resistor, the overshoot is reduced to % and eliminates the natural frequency, resulting in a much faster settling time (see Figure 9). The -pf capacitor was chosen for convenience only. Load capacitance had little effect on these measurements due to the excellent output drive capability of the TLC7x. V O Output Voltage V... VOUT VIN With CF = pf VDD = ± V AV = + RF = kω RL = 6 Ω CL = pf t - Time - µs V I Input Voltage V IN Figure 9. -V Step Response kω _ + Ω pf 6 Ω pf POST OFFICE BOX 633 DALLAS, TEXAS 76 9

20 general configurations APPLICATION INFORMATION When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure ). RG RF VI R V O V I C + f 3dB. R F R G.. src. VO RC Figure. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. VI R R C C + _ R = R = R C = C = C Q = Peaking Factor (Butterworth Q =.77) f 3dB RC RG RF RG = ( RF Q ) Figure. -Pole Low-Pass Sallen-Key Filter POST OFFICE BOX 633 DALLAS, TEXAS 76

21 APPLICATION INFORMATION shutdown function Three members of the TLC7x family (TLC7/3/) have a shutdown terminal (SHDN) for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to µa/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split supply voltages (e.g. ±. V), the shutdown terminal needs to be pulled to V DD (not system ground) to disable the operational amplifier. The amplifier s output with a shutdown pulse is shown in Figures 3 and. The amplifier is powered with a single -V supply and is configured as noninverting with a gain of. The amplifier turnon and turnoff times are measured from the % point of the shutdown pulse to the % point of the output waveform. The times for the single, dual, and quad are listed in the data tables. Figures 37, 38, 39, and show the amplifier s forward and reverse isolation in shutdown. The operational amplifier is configured as a voltage follower (A V = ). The isolation performance is plotted across frequency using. V PP,. V PP, and V PP input signals at ±. V supplies and. V PP, 8 V PP, and V PP input signals at ±6 V supplies. circuit layout considerations To achieve the levels of high performance of the TLC7x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. Ground planes It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling Use a 6.8-µF tantalum capacitor in parallel with a.-µf ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a.-µf ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the.-µf capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than. inches between the device power terminals and the ceramic capacitors. Sockets Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. Surface-mount passive components Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. POST OFFICE BOX 633 DALLAS, TEXAS 76

22 general PowerPAD design considerations APPLICATION INFORMATION The TLC7x is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure (a) and Figure (b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure (c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. Single or Dual Thermal Pad Area Quad 68 mils x 7 mils with vias (Via diameter = 3 mils) 78 mils x 9 mils with 9 vias (Via diameter = 3 mils) Figure 3. PowerPAD PCB Etch and Via Pattern POST OFFICE BOX 633 DALLAS, TEXAS 76

23 APPLICATION INFORMATION general PowerPAD design considerations (continued). Prepare the PCB with a top side etch pattern as shown in Figure 3. There should be etch for the leads as well as etch for the thermal pad.. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 3 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLC7x IC. These additional vias may be larger than the 3-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem.. Connect all holes to the internal ground plane.. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLC7x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the TLC7x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given θ JA, the maximum power dissipation is shown in Figure and is calculated by the following formula: P D. T MAX T A JA. Where: P D = Maximum power dissipation of TLC7x IC (watts) T MAX = Absolute maximum junction temperature ( C) T A θ JA = Free-ambient air temperature ( C) = θ JC + θ CA θ JC = Thermal coefficient from junction to case θ CA = Thermal coefficient from case to ambient air ( C/W) POST OFFICE BOX 633 DALLAS, TEXAS 76 3

24 APPLICATION INFORMATION general PowerPAD design considerations (continued) Maximum Power Dissipation W MAXIMUM POWER DISSIPATION FREE-AIR TEMPERATURE DGN Package Low-K Test PCB θ JA =.3 C/W PDIP Package Low-K Test PCB θ JA = C/W PWP Package Low-K Test PCB θ JA = 9.7 C/W SOT-3 Package Low-K Test PCB θ JA = 3 C/W T J = C SOIC Package Low-K Test PCB θ JA = 76 C/W TA Free-Air Temperature C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure. Maximum Power Dissipation Free-Air Temperature The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ JA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper package. POST OFFICE BOX 633 DALLAS, TEXAS 76

25 macromodel information TLC7, TLC7, TLC7, TLC73, TLC7, TLC7, TLC7xA APPLICATION INFORMATION Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note ) and subcircuit in Figure are generated using the TLC7x typical electrical and operating characteristics at T A = C. Using this information, output simulations of the following key parameters can be generated to a tolerance of % (in most cases): Maximum positive output voltage swing Unity-gain frequency Maximum negative output voltage swing Common-mode rejection ratio Slew rate Phase margin Quiescent power dissipation DC output resistance Input bias current AC output resistance Open-loop voltage amplification Short-circuit output current limit NOTE : G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 33 (97). PSpice and Parts are trademarks of MicroSim Corporation. POST OFFICE BOX 633 DALLAS, TEXAS 76

26 APPLICATION INFORMATION VDD + RP IN IN + DP 3 RSS ISS J J RD C RD VC DC + R 3 EGND 9 + VB 6 GCM 99 + FB C GA 9 RO HLIM 7 + VLIM 8 + DLP DLN VLP VLN + VDD VAD VE DE OUT RO *DEVICE=TLC7X_V, OPAMP, PJF, INT * TLC7X V operational amplifier macromodel subcircuit * created using Parts release 8. on /6/99 at 8:38 * Parts is a MicroSim product. * * connections: non-inverting input * inverting input * positive power supply * negative power supply * output *.subckt TLC7X_V 3 * c.8697e c E css 99.63E dc 3 dy de dy dlp 9 9 dx dln 9 9 dx dp 3 dx egnd 99 poly() (3,) (,).. fb 7 99 poly() vb vc ve vlp vln 6.93E6 E3 E3 6E6 6E6 ga 6 7.E 6 gcm E 6 iss 3 dc 83.67E 6 ioff 6 dc.86e 6 hlim 9 vlim K j jx j jx r 6 9.E3 rd.86e3 rd.86e3 ro 8 ro 7 99 rp 3.78E3 rss E6 vb 9 dc vc 3 3 dc. ve dc.83 vlim 7 8 dc vlp 9 dc 9 vln 9 dc 9.model dx D(Is=8.E 8).model dy D(Is=8.E 8 Rs=m Cjo=p).model jx PJF(Is=7.E Beta=.39E 3 Vto= ).model jx PJF(Is=7.E Beta=.39E 3 Vto= ).ends Figure. Boyle Macromodel and Subcircuit 6 POST OFFICE BOX 633 DALLAS, TEXAS 76

27 D (R-PDSO-G**) PIN SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE. (,7). (,). (,3). (,) M 8.7 (,). (3,8). (6,).8 (,8).8 (,) NOM Gage Plane A 7 8. (,). (,).6 (,).69 (,7) MAX. (,). (,) Seating Plane. (,) DIM PINS ** 8 6 A MAX.97 (,).3 (8,7).39 (,) A MIN.89 (,8).337 (8,).386 (9,8) 7/ D /96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed.6 (,). D. Falls within JEDEC MS- POST OFFICE BOX 633 DALLAS, TEXAS 76 7

28 DGN (S-PDSO-G8) MECHANICAL INFORMATION PowerPAD PLASTIC SMALL-OUTLINE PACKAGE,38,6, M, 8 Thermal Pad (See Note D) 3,,9,98,78, NOM Gage Plane, 3,,9 6,69,,7 MAX,, Seating Plane, 737/A /98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions include mold flash or protrusions. D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal pad is 68 mils (height as illustrated) 7 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package. E. Falls within JEDEC MO-87 PowerPAD is a trademark of Texas Instruments. 8 POST OFFICE BOX 633 DALLAS, TEXAS 76

29 DGQ (S-PDSO-G) MECHANICAL INFORMATION PowerPAD PLASTIC SMALL-OUTLINE PACKAGE,7,, M,7 6 Thermal Pad (See Note D) 3,,9,98,78, NOM Gage Plane, 3,,9 6,69,,7 MAX,, Seating Plane, 7373/A /98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal pad is 68 mils (height as illustrated) 7 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package. PowerPAD is a trademark of Texas Instruments. POST OFFICE BOX 633 DALLAS, TEXAS 76 9

30 N (R-PDIP-T**) 6 PIN SHOWN MECHANICAL INFORMATION PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** 6 8 A A MAX.77 (9,69).77 (9,69).9 (3.37).97 (,77) 6 9 A MIN.7 (8,9).7 (8,9).8 (.9).9 (3,88).6 (6,6). (6,) 8.7 (,78) MAX.3 (,89) MAX. (,) MIN.3 (7,87).9 (7,37). (,8) MAX. (3,8) MIN Seating Plane. (,). (,3). (,38). (,) M. (,) NOM /8 PIN ONLY 9/C 8/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS- ( pin package is shorter then MS-.) 3 POST OFFICE BOX 633 DALLAS, TEXAS 76

31 P (R-PDIP-T8) MECHANICAL INFORMATION PLASTIC DUAL-IN-LINE PACKAGE. (,6).3 (9,) 8.6 (6,6). (6,).7 (,78) MAX. (,) MIN.3 (7,87).9 (7,37). (,8) MAX Seating Plane. (3,8) MIN. (,). (,3). (,38). (,) M. (,) NOM 8/ B 3/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS- POST OFFICE BOX 633 DALLAS, TEXAS 76 3

32 PWP (R-PDSO-G**) PINS SHOWN MECHANICAL INFORMATION PowerPAD PLASTIC SMALL-OUTLINE,6,3,9, M Thermal Pad (See Note D),,3 6,6 6,, NOM Gage Plane, A 8,7,, MAX,, Seating Plane, DIM PINS ** 6 8 A MAX,, 6,6 7,9 9,8 A MIN,9,9 6, 7,7 9,6 73/F /98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusions. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimension of the thermal pad is 78 mils (height as illustrated) 9 mils (width as illustrated) (maximum). The pad is centered on the bottom of the package. E. Falls within JEDEC MO-3 3 POST OFFICE BOX 633 DALLAS, TEXAS 76

33 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright, Texas Instruments Incorporated

34 This datasheet has been download from: Datasheets for electronics components.