TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS

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1 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL Self-Calibrates Input Offset Voltage to µv Max Low Input Offset Voltage Drift... µv/ C Input Bias Current... pa Open Loop Gain... db Rail-To-Rail Output Voltage Swing Stable Driving pf Capacitive Loads Gain Bandwidth Product....7 MHz Slew Rate....5 V/µs High Output Drive Capability... ±5 ma Calibration Time... ms Characterized From 55 C to 5 C Available in Q-Temp Automotive HighRel Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards description The TLC5 and TLC5 are the highest precision CMOS single supply rail-to-rail operational amplifiers available today. The input offset voltage is µv typical and µv maximum. This exceptional precision, combined with a.7-mhz bandwidth,.5-v/µs slew rate, and 5-mA output drive, is ideal for multiple applications including: data acquisition systems, measurement equipment, industrial control applications, and portable digital scales. These amplifiers feature self-calibrating circuitry which digitally trims the input offset voltage to less than µv within the first ms of operation. The offset is then digitally stored in an integrated successive approximation register (SAR). Immediately after the data is stored, the calibration circuitry effectively drops out of the signal path, shuts down, and the device functions as a standard operational amplifier. IN Offset Control OUT IN Calibration Circuitry SAR D/A A/D VDD 8 5 V GND Power-On Reset Control Logic Oscillator Figure. Channel One of the TLC5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinEPIC and Self-Cal are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655 DALLAS, TEXAS 7565 Copyright, Texas Instruments Incorporated On products compliant to MIL-PRF-855, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

2 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL description (continued) Using this technology eliminates the need for noisy and expensive chopper techniques, laser trimming, and power hungry, split supply bipolar operational amplifiers. TLC5 D PACKAGE (TOP VIEW) TLC5 D OR JG PACKAGE (TOP VIEW) TLC5 U PACKAGE (TOP VIEW) NC IN IN V DD /GND NC V DD OUT NC OUT IN IN V DD /GND V DD OUT IN IN NC OUT IN IN V DD /GND NC V DD OUT IN IN TLC5 FK PACKAGE (TOP VIEW) NC No internal connection NC IN NC IN NC NC NC V DD /GND OUT NC NC IN V DD NC NC NC OUT NC IN NC TA VIOmax AT 5 C SMALL OUTLINE (D) C to7 C C to5 C C to5 C 55 C to5 C The D package is also available taped and reeled. AVAILABLE OPTIONS PACKAGED DEVICES CHIP CARRIER (FK) CERAMIC DIP (JG) CERAMIC FLAT PACK (U) µv TLC5ACD 5 µv TLC5ACD 8 µv TLC5CD µv TLC5CD µv TLC5AID 5 µv TLC5AID 8 µv TLC5ID µv TLC5ID 5 µv TLC5AQD µv TLC5QD 5 µv TLC5AMD TLC5AMFKB TLC5AMJGB TLC5AMUB µv TLC5MD TLC5MFKB TLC5MJGB TLC5MUB POST OFFICE BOX 655 DALLAS, TEXAS 7565

3 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V DD (see Note ) V Differential input voltage, V ID (see Note ) ±7 V Input voltage range, V I (any input, see Note ) V to 7 V Input current, I I (each input) ±5 ma Output current, I O (each output) ± ma Total current into V DD ± ma Total current out of V DD /GND ± ma Electrostatic discharge (ESD) > kv Duration of short-circuit current at (or below) 5 C (see Note ) unlimited Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : TLC5C C to 7 C TLC5I C to 5 C TLC5Q C to 5 C TLC5M C to 5 C Storage temperature range, T stg C to 5 C Case temperature for 6 seconds, T C : FK package C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltage values, except differential voltages, are with respect to VDD /GND.. Differential voltages are at IN with respect to IN. Excessive current flows when an input is brought below VDD. V.. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. PACKAGE DISSIPATION RATING TABLE TA 5 C DERATING FACTOR TA = 7 C TA = 85 C TA = 5 C POWER RATING ABOVE TA = 5 C POWER RATING POWER RATING POWER RATING D FK 75 mw 75 mw 5.8 mw/ C. mw/ C JG 5 mw 8. mw/ C U 675 mw 5. mw/ C recommended operating conditions 6 mw 77 mw 5 mw 88 mw 75 mw 75 mw 67 mw 56 mw mw mw 5 mw 5 mw TLC5C TLC5I TLC5Q TLC5M MIN MAX MIN MAX MIN MAX MIN MAX Supply voltage, VDD V Input voltage range, VI VDD VDD. VDD VDD. VDD VDD. VDD VDD. V Common-mode input voltage, VIC VDD VDD. VDD VDD. VDD VDD. VDD VDD. V Operating free-air temperature, TA C UNIT POST OFFICE BOX 655 DALLAS, TEXAS 7565

4 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL electrical characteristics at specified free-air temperature, V DD = 5 V, GND = (unless otherwise noted) TLC5xC PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VDD = ±.5 V, VO =, TLC5A VIO Input offset voltage VIC =, RS = 5 Ω TLC5 αvio IIO IIB VOH VOL AVD Temperature coefficient of input offset voltage Input offset current Input bias current High-level output voltage Low-level output voltage TLC5 8 8 Full range TLC5A 5 5 µv Full range µv/ C = = 5 C 6 VDD ±.5 V, VO, VIC =, RS = 5 Ω Full range 5 5 C 6 Full range 5 IOH = 5 µa 5 C.99 IOH = 5mA pa pa 5 C.9 V Full range.7 VIC =.5 V, IOL = 5 µa 5 C. VIC =5V.5 V, IOL =5mA 5 C. V Full range. Large-signal g differential voltage VIC =.5 V, VO O = V to V, 5 C amplification RL = kω, See Note Full range RI(D) Differential input resistance 5 C kω RL Input resistance See Note 5 C Ω CL Common-mode input capacitance f = khz, P package 5 C 8 pf zo Closed-loop output impedance AV =, f = khz 5 C Ω mode VIC = to.7 V, VO =.5 V, 5 C 9 CMRR Common-mode rejection ratio O RS = kω Full range 85 ksvr Supply-voltage rejection ratio ( VDD ±/ VIO) VDD =Vto6V V, VIC =, No load IDD Supply current VO =5V.5 V, No load 5 C 9 Full range 9 V/mV db db 5 C.5 TLC5/A Full range ma 5 C.5.5 TLC5/A Full range VIT(CAL) Calibration input threshold voltage Full range V Full range is C to 7 C. NOTE : RL and CL values are referenced to.5 V. POST OFFICE BOX 655 DALLAS, TEXAS 7565

5 operating characteristics, V DD = 5 V TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TLC5xC, TLC5xAC PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SR Slew rate at unity gain VO =5Vto5V.5.5 V, CL = pf Vn VN(PP) Equivalent input noise voltage 5 C.5.5 V/µs Full range V/µs f = Hz 5 C 7 f = khz 5 C Peak-to-peak equivalent input noise f =. to Hz 5 C voltage f =. to Hz 5 C.5 nv/ Hz In Equivalent input noise current 5 C.6 fa/ Hz THD N BOM ts Total harmonic distortion plus noise Gain-bandwidth product Maximum output swing bandwidth Settling time VO =.5 V to.5 V, AV = 5 C.% f = khz, = AV = 5 C.8% RL kω, CL = pf AV = 5 C.55% f = khz, CL = pf VO(PP) = V, RL = kω, AV =, Step =.5 V to.5 V, RL = kω, CL = pf RL = kω, AV =, CL = pf µv 5 C.7 MHz 5 C MHz to.% 5 C.6 to.% 5 C. φm Phase margin at unity gain RL = kω, CL = pf 5 C 7 Calibration time 5 C ms Full range is C to 7 C. NOTE : RL and CL values are referenced to.5 V. µs POST OFFICE BOX 655 DALLAS, TEXAS

6 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL electrical characteristics at specified free-air temperature, V DD = 5 V, GND = (unless otherwise noted) TLC5xI PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT VDD = ±.5 V, VO =, TLC5A VIO Input offset voltage VIC =, RS = 5 Ω TLC5 αvio IIO IIB VOH VOL AVD Temperature coefficient of input offset voltage Input offset current Input bias current High-level output voltage Low-level output voltage TLC5 8 8 Full range TLC5A 5 5 µv Full range µv/ C VDD = ±.5 V, VO O =, 5 C 6 VIC =, RS = 5 Ω C to 5 85 C VDD = ±.5 V, VIC =, VO =, RS = 5 Ω pa Full range 5 na 5 C 6 C to 85 C 5 pa Full range na IOH = 5 µa 5 C.99 IOH = 5mA 5 C.9 V Full range.7 VIC =.5 V, IOL = 5 µa 5 C. VIC =5V.5 V, IOL =5mA 5 C. V Full range. Large-signal g differential voltage VIC =.5 V, VO = V to V, 5 C amplification RL = kω, See Note Full range RI(D) Differential input resistance 5 C kω RL Input resistance See Note 5 C Ω CL Common-mode input capacitance f = khz, P package 5 C 8 pf zo Closed-loop output impedance AV =, f = khz 5 C Ω mode VIC = to.7 V, VO =.5 V, 5 C 9 CMRR Common-mode rejection ratio O RS = kω Full range 85 ksvr Supply-voltage rejection ratio ( VDD ±/ VIO) VDD =Vto6V V, VIC =, No load IDD Supply current VO =5V.5 V, No load 5 C 9 Full range 9 V/mV db db 5 C.5 TLC5/A Full range ma 5 C.5.5 TLC5/A Full range VIT(CAL) Calibration input threshold voltage Full range V Full range is C to 5 C. NOTE : RL and CL values are referenced to.5 V. 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

7 operating characteristics, V DD = 5 V TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TLC5xI, TLC5xAI PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT SR Slew rate at unity gain VO =5Vto5V.5.5 V, CL = pf Vn VN(PP) Equivalent input noise voltage 5 C.5.5 V/µs Full range V/µs f = Hz 5 C 7 f = khz 5 C Peak-to-peak equivalent input noise f =. to Hz 5 C voltage f =. to Hz 5 C.5 nv/ Hz In Equivalent input noise current 5 C.6 fa/ Hz THD N BOM ts Total harmonic distortion plus noise Gain-bandwidth product Maximum output swing bandwidth Settling time VO =.5 V to.5 V, AV = 5 C.% f = khz, = AV = 5 C.8% RL kω, CL = pf AV = 5 C.55% f = khz, CL = pf VO(PP) = V, RL = kω, AV =, Step =.5 V to.5 V, RL = kω, CL = pf RL = kω, AV =, CL = pf µv 5 C.7 MHz 5 C MHz to.% 5 C.6 to.% 5 C. φm Phase margin at unity gain RL = kω, CL = pf 5 C 7 Calibration time 5 C ms Full range is C to 5 C. NOTE : RL and CL values are referenced to.5 V. µs POST OFFICE BOX 655 DALLAS, TEXAS

8 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL electrical characteristics at specified free-air temperature, V DD = 5 V, GND = (unless otherwise noted) PARAMETER TEST CONDITIONS TA TLC5M TLC5Q, MIN TYP MAX VDD = ±.5 V, VO =, TLC5 VIO Input offset voltage O VIC =, RS = 5 Ω TLC5A Full range 5 5 UNIT µv αvio IIO IIB VOH VOL AVD Temperature coefficient of input offset voltage Input offset current Input bias current High-level output voltage Low-level output voltage Full range µv/ C = = 5 C 6 VDD ±.5 V, VO, VIC =, RS = 5 Ω 5 C 5 5 C 6 5 C IOH = 5 µa 5 C.99 IOH = 5mA na na 5 C.9 V Full range.7 VIC =.5 V, IOL = 5 µa 5 C. VIC =5V.5 V, IOL =5mA 5 C. V Full range. Large-signal g differential voltage VIC =.5 V, VO O = V to V, 5 C amplification RL = kω, See Note Full range RI(D) Differential input resistance 5 C kω RL Input resistance See Note 5 C Ω CL Common-mode input capacitance f = khz, P package 5 C 8 pf zo Closed-loop output impedance AV =, f = khz 5 C Ω mode VIC = to.7 V, VO =.5 V, 5 C 9 CMRR Common-mode rejection ratio RS = kω Full range 85 ksvr Supply-voltage rejection ratio VDD = V to 6 V, VIC = VDD /, 5 C 9 ( VDD ±/ VIO) No load Full range 9 IDD Supply current VO =5V.5 V, No load 5 C.5.5 Full range VIT(CAL) Calibration input threshold voltage Full range V Full range is C to 5 C for Q suffix, 55 C to 5 C for M suffix. NOTE : RL and CL values are referenced to.5 V. V/mV db db ma 8 POST OFFICE BOX 655 DALLAS, TEXAS 7565

9 operating characteristics, V DD = 5 V TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL PARAMETER TEST CONDITIONS TA TLC5Q, TLC5M, TLC5AQ, TLC5AM UNIT MIN TYP MAX VO =.5 V to.5 V, CL = pf 5 C.5.5 V/µs SR Slew rate at unity gain O L See Note Full range V/µs Vn VN(PP) Equivalent input noise voltage f = Hz 5 C 7 f = khz 5 C Peak-to-peak equivalent input noise f =. to Hz 5 C voltage f =. to Hz 5 C.5 nv/ Hz In Equivalent input noise current 5 C.6 fa/ Hz THD N BOM ts Total harmonic distortion plus noise Gain-bandwidth product Maximum output swing bandwidth Settling time VO =.5 V to.5 V, AV = 5 C.% f = khz, = AV = 5 C.8% RL kω, CL = pf AV = 5 C.55% f = khz, CL = pf VO(PP) = V, RL = kω, AV =, Step =.5 V to.5 V, RL = kω, CL = pf RL = kω, AV =, CL = pf µv 5 C.7 MHz 5 C MHz to.% 5 C.6 to.% 5 C. φm Phase margin at unity gain RL = kω, CL = pf 5 C 7 Calibration time 5 C ms Full range is C to 5 C for Q suffix, 55 C to 5 C for M suffix. NOTE : RL and CL values are referenced to.5 V. µs POST OFFICE BOX 655 DALLAS, TEXAS

10 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution,, vs Common-mode input voltage 5 αvio Input offset voltage temperature coefficient Distribution 6, 7 VOH High-level output voltage vs High-level output current 8 VOL Low-level output voltage vs Low-level output current 9 VO(PP) Maximum peak-to-peak output voltage vs Frequency IOS Short-circuit output current vs Free-air temperature VO Output voltage vs Differential input voltage AVD Large-signal differential voltage amplification vs Free-air temperature vs Frequency zo Output impedance vs Frequency 5 CMRR Common-mode mode rejection ratio vs Frequency 6 vs Free-air temperature 7 SR Slew rate vs Load capacitance 8 vs Free-air temperature 9 Inverting large-signal pulse response Voltage-follower large-signal pulse response Inverting small-signal pulse response Voltage-follower small-signal pulse response Vn Equivalent input noise voltage vs Frequency Input noise voltage Over a -second period 5 THD N Total harmonic distortion plus noise vs Frequency 6 Gain-bandwidth product vs Free-air temperature 7 φm Phase margin vs Load capacitance 8 vs Frequency Gain margin vs Load capacitance 9 PSRR Power-supply rejection ratio vs Free-air temperature Calibration time at C Calibration time at 5 C Calibration time at 85 C Calibration time at 5 C POST OFFICE BOX 655 DALLAS, TEXAS 7565

11 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS Percentage Of Amplification % DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE 9 Amplifier From Wafer Lot VDD = ±.5 V TA = C Percentage of Amplifiers % 8 6 DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE 86 Amplifier From 8 Wafer Lot VDD = ±.5 V TA = 5 C VIO Input Offset Voltage µv 6 5 VIO Input Offset Voltage µv 5 6 Figure Figure Percentage Of Amplification % DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE 96 Amplifier From Wafer Lot VDD = ±.5 V TA = 85 C V IO Input Offset Voltage µ V INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE VDD = ±.5 V RS = 5 Ω TA = 5 C 5 5 VIO Input Offset Voltage µv VIC Common-Mode Input Voltage v Figure Figure 5 5 POST OFFICE BOX 655 DALLAS, TEXAS 7565

12 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS Percentage Of Amplifiers % DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT Amplifiers From Wafer Lot VDD = ±.5 V TA = 5 C To C Percentage Of Amplifiers % DISTRIBUTION OF TLC5 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT Amplifiers From Wafer Lot VDD = ±.5 V TA = 5 C To 85 C α VIO Temperature Coefficient µv/ C Figure Figure α VIO Temperature Coefficient µv/ C V VOH High-Level Output Voltage V ÁÁ HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TA = 5 C TA = C TA = 5 C IOH High-Level Output Current ma Figure 8 TA = 85 C VDD = 5 V VIC =.5 V Low-Level Output Voltage V V OL LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VDD = 5 V VIC =.5 V TA = 85 C TA = 5 C TA = 5 C 5 IOL Low-Level Output Current ma Figure 9 TA = C POST OFFICE BOX 655 DALLAS, TEXAS 7565

13 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS Maximum Peak-To-Peak Output Voltage V V O(PP) 8 6 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY VDD = 5 V k k k M M f Frequency Hz Short-Circuit Output Current ma I OS SHORT-CIRCUIT OUTPUT CURRENT vs FREE-AIR TEMPERATURE IOS IOS TA Free-Air Temperature C 5 75 Figure Figure V O Output Voltage V OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE VDD = 5 V VIC =.5 V RL = kω TA = 5 C A VD Large-Signal Differential Voltage Amplification V/mV LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE RL = kω VID Differential Input Voltage mv Figure TA Free-Air Temperature C Figure 7 95 POST OFFICE BOX 655 DALLAS, TEXAS 7565

14 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE MARGIN vs FREQUENCY Large-Signal Differential A VD Voltage Amplification db 8 6 VDD = 5 V RL = kω CL = pf TA = 5 C Phase Margin k 9 k k M M M f Frequency Hz Figure OUTPUT IMPEDANCE vs FREQUENCY z O Output Impedance Ω... AV = AV = AV = k k k M f Frequency Hz Figure 5 POST OFFICE BOX 655 DALLAS, TEXAS 7565

15 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO vs FREQUENCY VDD = 5 V VIC =.5 V TA = 5 C CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE VDD = 5 V k k k M M f Frequency Hz TA Free-Air Temperature C Figure 6 Figure 7 µ s SR Slew Rate V/ 6 5 SLEW RATE vs LOAD CAPACITANCE SR SR V/µ s SR Slew Rate 8 6 VDD = 5 V RL = kω CL = pf AV = SLEW RATE vs FREE-AIR TEMPERATURE SR SR k k k CL Load Capacitance pf Figure TA Free-Air Temperature C Figure POST OFFICE BOX 655 DALLAS, TEXAS

16 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS.5 INVERTING LARGE-SIGNAL PULSE RESPONSE.5 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE V O Output Voltage V.5.5 VDD = 5 V.5 RL = kω CL = pf AV = TA = 5 C t Time µs 5 75 V O Output Voltage V VDD = 5 V RL = kω CL = pf AV = TA = 5 C t Time µs 5 75 Figure Figure INVERTING SMALL-SIGNAL PULSE RESPONSE VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE V O Output Voltage V VDD = 5 V RL = kω CL = pf AV = TA 5 C V O Output Voltage V VDD = 5 V RL = kω CL = pf AV = TA = 5 C t Time µs t Time µs 5 Figure Figure 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

17 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS VN Vn Equivalent Input Noise Voltage nv/ nv//hz Hz EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY VDD = 5 V RS = Ω TA = 5 C k f Frequency Hz Figure k k Input Noise Voltage nv INPUT NOISE VOLTAGE OVER A -SECOND PERIOD VDD = 5 V f =. Hz To Hz TA = 5 C 5 6 t Time s Figure THDN Total Harmonic Distortion Plus Noise %. TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY VDD = 5 V RL = kω TIED.5 V AV = AV = AV =. k k k f Frequency Hz Gain-Bandwidth Product MHz GAIN-BANDWIDTH PRODUCT vs FREE-AIR TEMPERATURE VDD = 5 V F = khz RL = kω CL = pf TA Free-Air Temperature C Figure 6 Figure 7 POST OFFICE BOX 655 DALLAS, TEXAS

18 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS 9 PHASE MARGIN vs LOAD CAPACITANCE TA 5 C GAIN MARGIN vs LOAD CAPACITANCE 75 Rnull = 5 Ω 5 Phase Margin kω Rnull = Rnull = Ω Gain Margin db 5 Rnull = 5 Ω Rnull = Ω 5 VI 5 kω VDD R null CL 5 Rnull = VDD k k k CL Load Capacitance pf k k k CL Load Capacitance pf Figure 8 Figure 9 POWER SUPPLY REJECTION RATIO vs FREE-AIR TEMPERATURE CALIBRATION TIME AT C PSRR Power Supply Rejection Ratio db VDD = V To 6 V VIC = VO = VDD/ TA Free-Air Temperature C V O Output Voltage V t Time ms VDD =.5 V GND =.5 V RL = kω to GND AV = VI = Figure Figure 8 POST OFFICE BOX 655 DALLAS, TEXAS 7565

19 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL TYPICAL CHARACTERISTICS.5 CALIBRATION TIME AT 5 C.5 CALIBRATION TIME AT 85 C V O Output Voltage V VDD =.5 V GND =.5 V RL = kω to GND AV = VI = V O Output Voltage V VDD =.5 V GND =.5 V RL = kω to GND AV = VI = 5 6 t Time ms t Time ms Figure Figure.5 CALIBRATION TIME AT 5 C V O Output Voltage V t Time ms VDD =.5 V GND =.5 V RL = kω to GND AV = VI = Figure POST OFFICE BOX 655 DALLAS, TEXAS

20 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL APPLICATION INFORMATION The TLC5 is designed to operate with only a single 5-V power supply, have true differential inputs, and remain in the linear mode with an input common-mode voltage of. The TLC5 has a standard dual-amplifier pinout, allowing for easy design upgrades. Large differential input voltages can be easily accommodated and, as input differential-voltage protection diodes are not needed, no large input currents result from large differential input voltage. Protection should be provided to prevent the input voltages from going negative more than. V at 5 C. An input clamp diode with a resistor to the device input terminal can be used for this purpose. For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor can be used from the output of the amplifier to ground. This increases the class-a bias current and prevents crossover distortion. Where the load is directly coupled, for example in dc applications, there is no crossover distortion. Capacitive loads, which are applied directly to the output of the amplifier, reduce the loop stability margin. Values of 5 pf can be accommodated using the worst-case noninverting unity-gain connection. Resistive isolation should be considered when larger load capacitance must be driven by the amplifier. The following typical application circuits emphasize operation on only a single power supply. When complementary power supplies are available, the TLC5 can be used in all of the standard operational amplifier circuits. In general, introducing a pseudo-ground (a bias voltage of V I / like that generated by the TLE6) allows operation above and below this value in a single-supply system. Many application circuits shown take advantage of the wide common-mode input-voltage range of the TLC5, which includes ground. In most cases, input biasing is not required and input voltages that range to ground can easily be accommodated. description of calibration procedure To achieve high dc gain, large bandwidth, high CMRR and PSRR, as well as good output drive capability, the TLC5 is built around a -stage topology: two gain stages, one rail-to-rail, and a class-ab output stage. A nested Miller topology is used for frequency compensation. During the calibration procedure, the operational amplifier is removed from the signal path and both inputs are tied to GND. Figure 5 shows a block diagram of the amplifier during calibration mode. POST OFFICE BOX 655 DALLAS, TEXAS 7565

21 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL VDD POWER-ON RESET S R Q Q ENABLE RC OSCILLATOR COUNTER RCO CLOCK RESET SAR CAL DAC CORE AMPLIFIER LPF RCO Figure 5. Block Diagram During Calibration Mode The class AB output stage features rail-to-rail voltage swing and incorporates additional switches to put the output node into a high-impedance mode during the calibration cycle. Small-replica output transistors (matched to the main output transistors) provide the amplifier output signal for the calibration circuit. The TLC5 also features built-in output short-circuit protection. The output current flowing through the main output transistors is continuously being sensed. If the current through either of these transistors exceeds the preset limit (6 ma 7 ma) for more than about µs, the output transistors are shut down to approximately their quiescent operating point for approximately 5 ms. The device is then returned to normal operation. If the short circuit is still in place, it is detected in less than µs and the device is shut down for another 5 ms. The offset cancellation uses a current-mode digital-to-analog converter (DAC), whose full-scale current allows for an adjustment of approximately ± 5 mv to the input offset voltage. The digital code producing the cancellation current is stored in the successive-approximation register (SAR). During power up, when the offset cancellation procedure is initiated, an on-chip RC oscillator is activated to provide the timing of the successive-approximation algorithm. To prevent wide-band noise from interfering with the calibration procedure, an analog low-pass filter followed by a Schmitt trigger is used in the decision chain to implement an averaging process. Once the calibration procedure is complete, the RC oscillator is deactivated to reduce supply current and the associated noise. POST OFFICE BOX 655 DALLAS, TEXAS 7565

22 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL APPLICATION INFORMATION The key operational-amplifier parameters CMRR, PSRR, and offset drift were optimized to achieve superior offset performance. The TLC5 calibration DAC is implemented by a binary-weighted current array using a pseudo-r-r MOSFET ladder architecture, which minimizes the silicon area required for the calibration circuitry, and thereby reduces the cost of the TLC5. Due to the performance (precision, PSRR, CMRR, gain, output drive, and ac performance) of the TLC5, it is ideal for applications like: Data acquisition systems Medical equipment Portable digital scales Strain gauges Automotive sensors Digital audio circuits Industrial control applications It is also ideal in circuits like: A precision buffer for current-to-voltage converters, a/d buffers, or bridge applications High-impedance buffers or preamplifiers Long term integration Sample-and-hold circuits Peak detectors The TLC5 self-calibrating operational amplifier is manufactured using Texas instruments LinEPIC process technology and is available in an 8-pin SOIC (D) Package. The C-suffix devices are characterized for operation from C to 7 C. The I-suffix devices are characterized for operation from C to 5 C. The M-suffix devices are characterized for operation from 55 C to 5 C. POST OFFICE BOX 655 DALLAS, TEXAS 7565

23 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL APPLICATION INFORMATION V(REF) V(REF) R 9 kω R 9 kω R kω R kω R5 9 kω R6 9 kω Gain = Gain = Gain = Gain = VDD 8. pf 6 VI RP kω / TLC5 5 / TLC5 7 VO VO RP VI kω (Gain ) V O. VI V I.. R6 R R5. V (REF) Where R R6, R R5, and R R (Gain ) V O. VI V I.. R5 R6. V R (REF) Where R R6, R R5, and R R RP < kω Figure 6. Single-Supply Programmable Instrumentation Amplifier Circuit VI RP < kω / TLC5 R 5 6 / TLC5 R 7 VO R RG V(REF) R V O V I *. R R..R R G.* V (REF) Where : R R and R R Figure 7. Two Operational-Amplifier Instrumentation Amplifier Circuit POST OFFICE BOX 655 DALLAS, TEXAS 7565

24 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL APPLICATION INFORMATION / TLC5 R R5 R VI RG R / TLC5 VO 6 5 / TLC5 7 R R6 V(REF) V O V I. R5 R..R R G. V (REF) Where : R R, R R, and R5 R6 Figure 8. Three Operational-Amplifier Instrumentation Amplifier Circuit VI R R R / TLC5 R5 I I R Figure 9. Fixed Current-Source Circuit POST OFFICE BOX 655 DALLAS, TEXAS 7565

25 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL APPLICATION INFORMATION / TLC5 VO VI V I V O Figure. Voltage-Follower Circuit VI / TLC5 ma Ω β 6 ma Figure. Lamp-Driver Circuit / TLC5 RL Ω Figure. TTL-Driver Circuit POST OFFICE BOX 655 DALLAS, TEXAS

26 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL APPLICATION INFORMATION IO VI / TLC5 I O V I R E RE Figure. High-Compliance Current-Sink Circuit VI V(REF) R kω / TLC5 VO R MΩ Figure. Comparator With Hysteresis Circuit IB 6 / TLC5 IB 5 / TLC5 7 ZO VO VI ZI C µf Figure 5. Low-Drift Detector Circuit 6 POST OFFICE BOX 655 DALLAS, TEXAS 7565

27 TLC5, TLC5A, TLC5, TLC5A SLOSB MAY 998 REVISED APRIL macromodel information APPLICATION INFORMATION Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note ) and subcircuit in Figure 6 are generated using the TLC5 typical electrical and operating characteristics at T A = 5 C. Using this information, output simulations of the following key parameters can be generated to a tolerance of % (in most cases): Maximum positive output voltage swing Unity-gain frequency Maximum negative output voltage swing Common-mode rejection ratio Slew rate Phase margin Quiescent power dissipation DC output resistance Input bias current AC output resistance Open-loop voltage amplification Short-circuit output current limit NOTE : G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 5 (97). 99 VDD IN IN DP VDD RP ISS RSS J RD C CSS J RD VD DC DE VE EGND R 6 VB GCM 9 DLP HLIM C GA DLN 9 VLP FB 7 VLIM 8 9 VLN RO RO OUT 5.subckt TLC5 5 * c.559e c E css 99.E dc 5 5 dy de 5 5 dy dlp 9 9 dx dln 9 9 dx dp dx egnd 99 poly() (,) (,).5.5 fb 7 99 poly(5) vb vc ve vlp vln 8.657E9 E E 85E9 85E9 ga 6 6.5E6 gcm E9 iss dc.e6 hlim 9 vlim K j jx j jx r 6 9.E rd.8e rd.8e ro E ro E rp 5.E rss 99.E6 vb 9 dc vc 5 dc.998 ve 5 dc.898 vlim 7 8 dc vlp 9 dc 67 vln 9 dc 67.model dx D(Is=8.E8).model dy D(Is=8.E8 Rs=m Cjo=p).model jx NJF(Is=5.E5 Beta=.797E Vto=).model jx NJF(Is=5.E5 Beta=.797E Vto=).ends Figure 6. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. POST OFFICE BOX 655 DALLAS, TEXAS

28 PACKAGE OPTION ADDENDUM 8-Sep-7 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish (6) MSL Peak Temp () Op Temp ( C) QPA ACTIVE CDIP JG 8 TBD A N / A for Pkg Type -55 to QPA TLC5M QHA ACTIVE CFP U TBD A N / A for Pkg Type -55 to QHA TLC5AM QPA ACTIVE CDIP JG 8 TBD A N / A for Pkg Type -55 to QPA TLC5AM TLC5ACD ACTIVE SOIC D 8 75 Green (RoHS TLC5AID ACTIVE SOIC D 8 75 Green (RoHS TLC5AIDR ACTIVE SOIC D 8 5 Green (RoHS TLC5CD ACTIVE SOIC D 8 75 Green (RoHS TLC5CDG ACTIVE SOIC D 8 75 Green (RoHS TLC5ID ACTIVE SOIC D 8 75 Green (RoHS TLC5IDG ACTIVE SOIC D 8 75 Green (RoHS TLC5IDR ACTIVE SOIC D 8 5 Green (RoHS TLC5IDRG ACTIVE SOIC D 8 5 Green (RoHS TLC5ACD ACTIVE SOIC D 8 75 Green (RoHS TLC5ACDG ACTIVE SOIC D 8 75 Green (RoHS TLC5ACDR ACTIVE SOIC D 8 5 Green (RoHS TLC5ACDRG ACTIVE SOIC D 8 5 Green (RoHS TLC5AID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level--6C-UNLIM to 7 5AC CU NIPDAU Level--6C-UNLIM - to 5 5AI CU NIPDAU Level--6C-UNLIM - to 5 5AI CU NIPDAU Level--6C-UNLIM to 7 5C CU NIPDAU Level--6C-UNLIM to 7 5C CU NIPDAU Level--6C-UNLIM - to 5 5I CU NIPDAU Level--6C-UNLIM - to 5 5I CU NIPDAU Level--6C-UNLIM - to 5 5I CU NIPDAU Level--6C-UNLIM - to 5 5I CU NIPDAU Level--6C-UNLIM to 7 5AC CU NIPDAU Level--6C-UNLIM to 7 5AC CU NIPDAU Level--6C-UNLIM to 7 5AC CU NIPDAU Level--6C-UNLIM to 7 5AC CU NIPDAU Level--6C-UNLIM - to 5 5AI Device Marking (/5) Samples Addendum-Page

29 PACKAGE OPTION ADDENDUM 8-Sep-7 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan TLC5AIDG ACTIVE SOIC D 8 75 Green (RoHS TLC5AIDR ACTIVE SOIC D 8 5 Green (RoHS TLC5AMD ACTIVE SOIC D 8 75 Green (RoHS () Lead/Ball Finish (6) MSL Peak Temp () Op Temp ( C) CU NIPDAU Level--6C-UNLIM - to 5 5AI CU NIPDAU Level--6C-UNLIM - to 5 5AI CU NIPDAU Level--6C-UNLIM -55 to 5 5AM TLC5AMJGB ACTIVE CDIP JG 8 TBD A N / A for Pkg Type -55 to QPA TLC5AM TLC5AMUB ACTIVE CFP U TBD A N / A for Pkg Type -55 to QHA TLC5AM TLC5CD ACTIVE SOIC D 8 75 Green (RoHS TLC5CDG ACTIVE SOIC D 8 75 Green (RoHS TLC5CDR ACTIVE SOIC D 8 5 Green (RoHS TLC5CDRG ACTIVE SOIC D 8 5 Green (RoHS TLC5ID ACTIVE SOIC D 8 75 Green (RoHS TLC5IDG ACTIVE SOIC D 8 75 Green (RoHS TLC5IDR ACTIVE SOIC D 8 5 Green (RoHS TLC5IDRG ACTIVE SOIC D 8 5 Green (RoHS TLC5MDG ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level--6C-UNLIM to 7 5C CU NIPDAU Level--6C-UNLIM to 7 5C CU NIPDAU Level--6C-UNLIM to 7 5C CU NIPDAU Level--6C-UNLIM to 7 5C CU NIPDAU Level--6C-UNLIM - to 5 5I CU NIPDAU Level--6C-UNLIM - to 5 5I CU NIPDAU Level--6C-UNLIM - to 5 5I CU NIPDAU Level--6C-UNLIM - to 5 5I CU NIPDAU Level--6C-UNLIM 5M TLC5MJGB ACTIVE CDIP JG 8 TBD A N / A for Pkg Type -55 to QPA TLC5M TLC5QD ACTIVE SOIC D 8 75 Green (RoHS TLC5QDG ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level--6C-UNLIM - to 5 C5Q CU NIPDAU Level--6C-UNLIM C5Q Device Marking (/5) Samples () The marketing status values are defined as follows: Addendum-Page

30 PACKAGE OPTION ADDENDUM 8-Sep-7 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all RoHS substances, including the requirement that RoHS substance do not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS79B low halogen requirements of <=ppm threshold. Antimony trioxide based flame retardants must also meet the <=ppm threshold requirement. () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC5, TLC5A, TLC5AM, TLC5M : Catalog: TLC5A, TLC5 Military: TLC5M, TLC5AM NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Addendum-Page

31 PACKAGE OPTION ADDENDUM 8-Sep-7 Military - QML certified for Military and Defense Applications Addendum-Page

32 PACKAGE MATERIALS INFORMATION -Feb-6 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A (mm) B (mm) K (mm) P (mm) W (mm) Pin Quadrant TLC5AIDR SOIC D Q TLC5IDR SOIC D Q TLC5ACDR SOIC D Q TLC5AIDR SOIC D Q TLC5CDR SOIC D Q TLC5IDR SOIC D Q Pack Materials-Page

33 PACKAGE MATERIALS INFORMATION -Feb-6 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5AIDR SOIC D TLC5IDR SOIC D TLC5ACDR SOIC D TLC5AIDR SOIC D TLC5CDR SOIC D TLC5IDR SOIC D Pack Materials-Page

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37 MECHANICAL DATA MCERA JANUARY 995 REVISED JANUARY 997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE. (,6).55 (9,) (7,).5 (6,).65 (,65).5 (,).6 (,6).5 (,8). (,5) MIN. (7,87).9 (7,7). (5,8) MAX Seating Plane. (,) MIN. (,5). (,58).5 (,8). (,6).8 (,) 5 7/C 8/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 85 GDIP-T8 POST OFFICE BOX 655 DALLAS, TEXAS 7565

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