Lecture 2 - A Analog Signal Conditioning

Transcription

1 Lecture 2 - A Analog Signal Conditioning EE 521: Instrumentation and Measurements Lecture Notes Update on September 10, 2009 Aly El-Osery, Electrical Engineering Dept., New Mexico Tech 2 - A.1 Contents 1 Op-Amps - Handbook 1 2 Differential Amplifiers (DA) CMRR - Measurement Source Resistance Asymmetry Operational Amplifiers Broadband Amplifier A.2 1 Op-Amps - Handbook Handbook of Operational Amplifier A.3 2 Differential Amplifiers (DA) Overview Used for a wide variety of applications. Responds to the use difference in the input signals. Discriminates against changes in the dc power supply voltage. 2 - A.4 DA Basics Given two inputs v i,1 and v i,2 define difference mode and common-mode input and output signals as v id (v i,1 v i,2 )/2, v ic (v i,1 + v i,2 )/2 (1) See Figure 1. v od (v o,1 v o,2 )/2, v oc (v o,1 + v o,2 )/2 (2) v i,1 v i,2 Differential Amplifier v o,1 v o,2 Figure 1: Differential amplifier block 1

2 Middlebrook Equations v od A dd v id + A dc v ic, v oc A cd v id + A cc v ic (3) 2 - A.5 Output Equations For single output v o v o,1 v o A dd + A cd + A dc + A cc v i,1 + A cc + A dc A dd A cd v i,2 2 2 (4) A D v id + A C v ic Note. These gains are frequency dependent. Ideal DA A cc A cd A dc 0 (5) A C 0, A D A dd (6) 2 - A.6 Common-Mode Rejection Ratio (CMRR) How close is the real differential amplifier close to an ideal one? CMRR ( v ic to give a certain v o ) ( v id to give the same v o ) (7) CMRR A dd A cc A D (8) A C 2 - A CMRR - Measurement Measurement of A D and A C First case, connect both inputs to v s1 generating a common mode input signal which results in an output v o. Second Case, connect the + input to v s2 and negative input to ground. v id v s2 /2, v ic v s2 /2 Adjust v s2 such that the output is equal to v o generated in the common mode input. A C v o /v ic v o /v s1 also consequently, and v o A D v s2 /2+A C v s2 /2 A D v o (2/v s2 1/v s1 ) (9) CMRR A D /A C (2v s1 /v s2 1) (10) 2 - A Source Resistance Asymmetry DC Equivalent Input Circuit Most frequently, common-mode input resistance,, measured between one input to ground using common mode input, and a difference-mode input resistance, R id, measured using difference mode input from either inputs to ground, are provided by the manufacturer. 2 - A.9 2

3 R s v i,1 V s,1 V s,2 R s + δr v i,2 Figure 2: Differential amplifier input circuit at dc showing source resistance unbalance. DA Input Circuit See Figure A.10 CMRR-Computation Under difference mode excitation, the current into the non-inverting input is given by: and i d 2v id / + v id / (11) i d /v id 1/R id 2/ + 1/ (12) 2R id /( R id ) (13) If R id, then. Using this assumption as well as the fact that δr is numerically negligible, then under common mode excitation v sc, v id δr v sc 2( + R s ) 2 (14) For purely difference mode excitation v sd v ic (15) v sc + R s Using v o A D v id + A C v ic, v id (16) v sd + R s v ic δr v sd 2( + R s ) 2 (17) v o A D v sc δr/[2( + R s ) 2 ]+A C v sc /( + R s ) (18) and v o A D v sd /( + R s )+A C v sd δr/[2( + R s ) 2 ] (19) CMRR sys A D/A C + δr/[2( + R s )] [A D /A C ]δr/[2( + R s )]+1 CMRR A CMRR A δr/[2( + R s )]+1 (20) CMRR A is specified by the manufacturer 2 - A.11 3

4 CMRR sys CMRR A ( /R s +1) CMRR A 0 δr/r s Figure 3: Differential amplifier CMRR magnitude vs fractional unbalance in source resistance. CMRR - Special Cases If the thevenin source resistance are matched CMRR sys CMRR A (21) When then δr/r s 2( /R s + 1)/CMRR A CMRR sys 2 - A.12 Source Resistance Asymmetry See Figure 3 We can increase the systems CMRR by adding an external resistance. 2 - A.13 3 Operational Amplifiers Typical Op-Amp Open-loop Transfer Function v o k ov A D v i v i (τ 1 s+1)(τ 2 s+1) (22) f 1 1/(2πτ 1 ) and f 2 1/(2πτ 2 ). To ensure stability A D ( j f 2 ) 1. f 1 occurs at a relatively low value. Small-signal gain bandwidth product GBWP k ov /(2πτ 1 ) (23) The unity gain of 0dB frequency of the open loop, f T, is approximately equal to the GBWP. Slew rate η. 2 - A.14 4

5 Notes Two pieces of information define are required to define the op-amp s open-loop characteristics. DC open-loop gain k ov, and 0dB frequency, f T. Closed-loop gain is limited by the open-loop gain. The higher the closed-loop gain is the smaller the bandwidth. To overcome this problem, it is better to cascade identical amplification stages rather than having one op-amp with a high gain. 2 - A Broadband Amplifier Non-inverting Amplifier See Figure 4A. v o (v s v i) k vo τs+1 (24) v i v o + R F βv o (25) (A) (B) V s V i V i + V o V s V i V i + V o R F Figure 4: Non-inverting op-amp circuits v o /v s which, assuming that βk ov 1 reduces to v o /v s k ov/(τs+1) 1+βk ov /(τs+1) 1/β s(τ/(βk ov ))+1 (26) (27) GBWP [k ov /(1+βk ov )][(βk ov )/(2πτ)] k ov /(2πτ) (28) If is infinite and R F is shortcircuit, then we obtain a voltage follower that can be used as impedance isolation, see Figure 4B. 2 - A.16 Inverting Amplifier and Summer See Figure 5. The gain for the kth inverting input is v o /v sk (G 1 /G F ) s(τ G/(k ov G F )+1 (29) 2 - A.17 5

6 R 2 R F V s2 Vs1 + V o Figure 5: Summing op-amp 6