Describe the basic DC characteristics of an op amp. Sketch a diagram of the op amp DC test circuit. Input Offset Voltage. Input Offset Current

Transcription

1 Testing Op Amps Chapter 3 Goals Understand the requirements for testing Op Amp DC parameters. Objectives Describe the basic DC characteristics of an op amp. Select a test methodology for evaluating voltage offset, gain, and bias current. Sketch a diagram of the op amp DC test circuit. In This Chapter Op Amp Basics Input Offset oltage Input Offset Current Input Bias Current oltage Gain Common Mode Rejection Ratio (CMRR) Power Supply Rejection Ratio (PSRR) Output Impedance 3-1

2 IDEAL Op Amp Characteristics An Operational Amplifier (OP-AMP) is a building block for many types of analog circuits. The Op Amp circuit symbol shows two inputs and one output. The input with the - sign is referred to as the inverting input, and the input with the sign is the non-inverting input. The characteristics of an op-amp circuit are defined by the feedback circuit. The op amp is a voltage difference amplifier that is, the voltage level on the output is dependent on the difference between the two inputs. Inverting Input _ Output Non-inverting Input Figure 3.1 Op Amp Circuit Symbol An IDEAL op amp has IDEAL characteristics (either infinite or zero) as listed below. Name Symbol IDEAL alue Typical alue Input Z i M - T Impedance Output Impedance Z o Open-loop A vo / 10 5 / Gain Input Offset io 0 m oltage Input Bias I B, I B- 0 A pa - A - Current Slew Rate /s /s to k/s Common-mode Rejection Ratio CMRR -80dB to -120dB 3-2

3 Input Offset oltage ( io ). Input offset voltage is the dc voltage which must be applied between the input terminals through two equal resistances to force the quiescent dc output to zero or other specified level. Input Bias Current (I B-, I B ) The input bias currents are the currents flowing into the inverting (-) and non-inverting () terminals of an operational amplifier. Input Offset Current (I io ) The input offset current is the algebraic sum of the currents entering into the input terminals of a differential input amplifier. I io = I B - I B- Common Mode Rejection Ratio (CMRR). The common mode rejection ratio is the ratio of the change in input common mode voltage to the resulting change in the input offset voltage. CMRR is usually expressed in decibels. CMRR 20log cm io Power Supply Rejection Ratio (PSRR). The power supply rejection ratio is the ratio of the change in input offset voltage, io to the corresponding change in power supply voltage usually expressed in micro volts per volt or db. io PSRR cc oltage Gain (Avo). The voltage gain (open loop) is the ratio of the change in the output voltage to the differential change in the input voltage. The input not connected to the signal source is at zero potential. Output oltage Swing (OP). The maximum output voltage swing that can be achieved for a specified load without causing voltage limiting. 3-3

4 Understanding Op Amp DC Parameters A real op amp has non-ideal features which are somewhat processdependent. Op amp characteristics are tested as to be within an acceptable range of a specified parameter. A simple model of a real op amp includes several sources of error. I B, I B- (input bias currents) act as a series current sources. io (input offset voltage) acts as a series voltage source. Zdiff (differential impedance) is the effective impedance between inputs. ZCm (common mode impedance) is the effective impedance between the inputs and ground. Ro (output impedance) is added in series with the output. I B - IO "REAL" (EQUIALENT MODEL) I IO IN v cc Z CM Z DIFF IDEAL OUT v EE - I B- Figure 3.14 Simple Op Amp Model 3-4

5 Op Amp Rules of the Road First, because of the op amp s very high input impedance, the current flowing into or out of the op amp s input terminals is extremely small. This current is usually negligible compared to conventional op amp circuit currents and is ignored without controversy. Secondly, since the output of the op amp circuit is based on the difference between the two inputs, it follows that the output will be stable when the two inputs are equal. An op amp circuit with negative feedback will drive the output in such a way that the inputs are at the same potential. This behavior is often called a virtual short because the two input terminals have the same potential even though their currents are completely decoupled. There two properties are essential to understanding op amp circuits: 1. Zero input (terminal) current 2. irtual (input terminal) short Basic Op Amp Configurations Inverting Amplifier 1.0 volt 1K _ 10K volt Rf Gain = - Ri Figure 3.12 Inverting Amplifier Inverting Amplifier Properties Allows negative gain factors (less than unity). Input impedance is a co-factor of the feedback ratio. 3-5

6 Convenient for level shifting Input is referenced to virtual ground. Non-Inverting Amplifier Basic Op Amp Configurations 1.0 volt 11.0 volt 1K Ri _ 10K Rf Gain = Rf Ri 1 Figure 3.13 Non-inverting amplifier Only positive gain (unity or greater) factors High input impedance, isolated from the feedback ratio Awkward for level shifting The op amp s high input impedance makes testing its characteristics challenging. For example, in order to measure an op amp s input 3-6

7 Op Amp Test Circuits voltage offset, io, one might consider the following test circuit. In theory, a voltmeter placed across the input terminals should read io. 15 R R2 R3 10k -15 Figure 3.15 Theoretical Op Amp Test Circuit This circuit and approach does not work because the voltmeter s impedance is small or about the same as that of the op amp itself. Idealyy, the meter s impedance should be several orders of magnitude greater than that of the Device Under Test (DUT). In this case, placing the meter across the op amp s input terminal s causes significant loading, yielding an unacceptable measurement. A more realistic DC test circuit for op amps places the DUT within the feedback circuit of the control amplifier A1. There is no feedback 3-7

8 Op Amp Test Circuits circuit for the DUT, resulting in an effective open loop configuration. Performance of the device is evaluated by measuring and / or adjusting parameters on the control amplifier. The error of the DUT is illustrated in Figure 3.15A by voltage source s1. R2 50k 10.00n DC s1 1m - R R1A DUT OP AMP DC TEST CIRCUIT A A DC Figure 3.16A Practical Op Amp Test Circuit (first level) The first iteration of the DC test circuit of Figure 3.15A shows a gain of A v The 1m into R2 generates a current flow of A (1 / 50 ). 1m 50 R R A In order to sink 20.0A of current across R1, the control amplifier, A1, must generate a voltage level of olts ( -1v / 50k =20.0uA). 1 50K 20uA Suppose the open-loop gain of A1 is known to be 100 million, or

9 Op Amp Test Circuit A (continued) In order to generate an output level of 1 volt, the A1 s differential input voltage must be 1 / 10 8 = 10 nanovolts. A 1 10 o o id vo 10 8 id A vo n Some observations: 1. The Amplifier A1 will generate an output level so the current flowing through R1 is equal to the current flowing through R2. 2. The input voltage level to Amplifier A1 is equal to the (Output oltage of A1) / (Open-loop Gain of A1) 3. The control Amplifier, A1, must be well characterized. In particular, the open-loop gain of A1 must be accurately determined beforehand. 4. In general, the more IDEAL the control Amplifier is, the better the accuracy of the test results of this test circuit. The second iteration of the test circuit adds a summing junction of two 100K resistors, R3 and R4, at the inverting input of the control amplifier A1. (Figure 3.16) Now instead of amplifier A1 responding to the input of the DUT, the 3-9

10 Op Amp Test Circuit B DUT is responding to the input of A1. R k DC R R1B 100k R3 R4 100k - s1 1.0 Figure 3.16B Op Amp Test Circuit with oltage Sum Node (second level) The 1 input level applied to R3 generates a current of 10uA. Since the current cannot flow into A1, it must flow into R4. In order to generate a current flow of -10A through resistor R4, the output of the DUT must provide a voltage level equal to R4 * 10a = -1. Observations: 1. By forcing a voltage into a summing junction, the DUT is forced to generate an equal and opposite output level. 3-10

11 Op Amp Test Circuit B (continued) 2. The 1 of source s1 and its -1 reflection at the DUT output is not directly useful for measuring input offset voltage. 3. The technique of forcing the DUT to respond with any reasonable voltage level (-s1) is extremely useful for testing many op amp characteristics including io. 4. For determining the actual input offset voltage, s1 is set to 0 as presented and discussed below. Input Offset oltage ( IO ) is the DC voltage which must be applied between the two input pins through two equal resistors, to force the quiescent DC output to zero volts (or other specified level). Measuring Input Offset oltage The test circuit forces the output of the DUT to 0.0 volts via the s1 level applied to the junction of R3 and R4. Under these conditions, the DUT s differential input voltage, id DUT, is indeed DUT s input offset voltage, io. In this example, the DUT must have an input offset voltage of 8.75u to achieve an output level of 0.0 volts. To force the DUT input to 8.75u, the output of Amplifier A1 must generate a voltage level that is sufficient to drive the simple voltage-divider network of R2 and R1. The voltage gain, A v, of this resistor network is equal to (R2/R1) 1, or 1001 in this example. o R 1 R1 o R Av 1 R R io 2 io 2 1 The output of control amplifier A1 for this test is recorded as E0. The DUT output voltage is therefore equal to the E0 level / To find the DUT offset voltage, the output of Amplifier A1 is divided by

12 R k R k 8.761m DC 49.9 R1B R3 R4 100k - s1 0.0 Figure 3.17 Input Offset oltage Test Circuit Measuring Input Offset oltage (continued) io E0 ( R2 / R1) 1 The Open-loop oltage Gain (A vo ) is the ratio of change in the DUT output voltage to a change in the DUT input differential voltage. 3-12

13 Measuring oltage Gain A vo o id open loop The oltage Gain test is usually performed with a specified load resistance (RL) on the output of the DUT. Supply s1 is set to a specified voltage. To null the R4/R5 junction, the control amplifier A1 will cause the DUT output to comply to a level that is equal and opposite to the voltage on s1. Example: Step One: The test circuit forces the output of the DUT to 0.0 volts via the s1 level applied to the junction of R3 and R4. The output of M2 R k M1 R R1B DUT NO DATA DC RL 10k 100k R3 R4 100k s A1 M2 NO DATA DC Figure 3.18 Open-loop oltage Gain Test Circuit 3-13

14 Gain Test Calculations is measured 10.75m. (E7) Step Two: The test circuit forces the output of the DUT to 10.0 volts via the s1 level applied to the junction of R3 and R4. The output of M2 is measured 30.9m. (E8) The change in the A1 output voltage is: o E E8 E7 Change in input voltage corresponding to the output level change: E8 id E7 1 R2 / R1 With E8 = 30.9m, E7 = 10.75m, R2=49.9k and R1= m 10.75m id The open-loop voltage gain, A vo, being the ratio of the output change to input change: 10 0 A vo 496.3k / The common mode rejection ratio is the ratio of the change in input common mode voltage to the resulting change in the input offset voltage. CMRR is usually expressed in decibels: 3-14

15 Measuring Common Mode Rejection Ratio (CMRR): where and CMRR 20log io icm _ cm icm = change in common-mode input voltage io _ cm = change in input offset voltage under common-mode conditions The first CMRR test circuit applies a change common-mode input voltage directly by changing the power supply level driving both DUT input pins via the small input resistors. This circuit differs from the following circuit mainly in the fact that it requires an additional poiwer supply. Note that forcing the DUT output to 0 causes the effective DUT input voltage to be, by definition, the input offset voltage under common-mode conditions. The second CMRR test circuit applies an effective change common mode input voltage by changing the power supply levels and the DUT output level, relative to the DUT input pins. Compared with the first CMRR test circuit, this circuit has the advantage of not requiring an additional power supply. This technique was initially applied due to the limited number of independent voltage sources for early ATE systems. The second CMRR test circuit is shown under two distinct commonmode conditions: 3-15

16 R k DUT 5 15/ 15 R1 R k A1 A1 M m DC 10 or R1B -15 R4 100k - s1 0 Figure 3.18 Open-loop CMRR Test Circuit R k DUT 5 / or R1 R k A1 A1 M m DC 49.9 R1B or -5 R4 100k s1 s or Figure 3.18 Open-loop CMRR Test Circuit 3-16

17 Case 1: effective common-mode input voltage = 10 DUT power (15) > 5 DUT - power ( -15) > -25 DUT output ( 0) > -10 DUT c-m input ( 10) > 0 Case 2: effective common-mode input voltage = -10 DUT power (15) > 25 DUT - power ( -15) > -5 DUT output ( 0) > 10 DUT c-m input (-10) > 0 Referring back to the first CMRR test circuit, applying a commonmode input voltage directly to the DUT, the CMRR may be evaluated as follows: CMRR Calculations 0. Apply 15, -15 and 0 to the DUT power pin, the DUT power pin, and s1, respectively, throughout the entire CMRR measurement. 1. Apply 10.0 to the DUT via the input resistors. 2. Measure o (E11) of the control amplifier A1. Example measurement = 30.78m. At this point, the DUT s effective input offset is io_cm with icm equal to Now Apply to the DUT via the input resistors. 4. Measure o (E12) of the control amplifier A1. Example measurement = m. Now the DUT s effective input offset is io_cm with icm equal to -10. The difference of input offset voltage under common-mode conditions is calculated by: 3-17

18 CMRR Calculations (continued) io _ cm A E voltage _ divider v E12 E11 R2 1 R m ( 9.286m ) 1001 io _ cm Finally, the log ratio of the Common Mode Rejection Ratio is calculated by: CMRR 20log io icm _ cm 10 ( 10 ) 20log dB The power supply rejection ratio is the ratio of the change in the power supply voltage to the resulting change in the input offset voltage. PSRR is expressed as microvolts per volt (u/), or as a db ratio. 3-18

19 Measuring Power Supply Rejection Ratio (PSRR) () where and PSRR io _ ps CC io _ ps = change in input offset voltage (E14-E13) under altered power supply conditions cc = change in positive power supply voltage Note that this expression for PSRR is inverse with respect to the similar expression for CMRR. Unfortunately, both expressions for PSRR are cited commonly in device specifications. The following test circuit and calculation focuses on the Positive PSRR measurement, that is, the DUT s ability to maintain small variations in its output voltage due to significant variations in the DUT s positive power supply voltage. The test process measures the effective input offset voltage for two levels of CC. R k DUT R or 5 R3 100k A m DC 49.9 R1B / -15 R4 100k s Figure 3.22 Positive PSRR Test Circuit 3-19

20 Positive PSRR () Calculations 1. Apply 5.0 to the positive DUT supply and measure the effective input offset voltage (E13). Example measurement o_ps = 9.5m. 2. Apply 15.0 to the positive DUT supply and measure the effective input offset voltage (E14). Example measurement o_ps = 10.7m. 3. Calculate the PSRR ratio. PSRR io _ ps ps o _ ps /1000 CC (10.7m 9.5m ) /1000 ( ) 0.12u / Negative PSRR is defined and tested in similar fashion as Positive PSRR: Measuring Negative Power Supply Rejection Ratio (PSRR) (--): where and io _ PSRR ps io _ ps EE = change in input offset voltage (E16-E15) under altered power supply conditions = change in negative power supply EE voltage The test process measures the effective input offset voltage for two levels of EE. 3-20

21 Negative PSRR () Calculations 1. Apply -5.0 to the negative DUT supply and measure the input offset voltage (E15). Example measurement = 13.2m. 2. Apply to the positive DUT supply and measure the input offset voltage (E16). Example measurement = 10.7m. 3. Calculate the PSRR ratio: PSRR io _ ps ps (10.7m o _ ps /1000 EE 13.2m ) / ( 5.0 ) 0.25u / The ICC test measures the power supply current at both the positive and negative supply pins. The DUT output is forced to 0.0 volts, with both inputs at 0.0 volts. R k DUT R R3 100k A m DC 49.9 R1B -15 or -5-5 / -15 R4 100k s Figure 3.22 Negative PSRR Test Circuit 3-21

22 Power Supply Current (ICC Output voltage swing (peak-to-peak) is tested by forcing the DUT output to the specified levels The test determines whether the operational amplifier will reach the specified positive and negative output voltage levels, OP and -OP, for the device. The test is mA DC A R k R R1B DUT mA DC A -15 R3 100k R4 100k s1 0-0 A m DC Figure 3.23 Power Supply Current Test Circuit 3-22

23 Output oltage Swing accomplished by driving the input of the control amplifier A1 with power supply S1 through resistor junction R4 and R5. The output voltage is measured directly on the DUT output pin. The output voltage swing is defined by: OP = E9 - OP = E10. By adding series resistors to the DUT input terminals, a test circuit can be configured to measure the very small currents actually flowing into or out of the op amp s inputs. These currents are the input bias currents, I B and I B-, and the input offset current, I io, which is simply the R k DC R R3 100k A m DC 49.9 R1B -15 R4 100k s Figure 3.23 Output Swing Test - Step One R k DC R R3 100k A m DC 49.9 R1B -15 R4 100k s1-12 Figure 3.24 Output Swing Test Step Two 3-23

24 Measuring Input Currents - I B, I B- and I io difference between I B and I B-. Note that theoretically I B should equal I B- so that I io should be = 0 pa (theoretically). S1 R1A R3a I B- v cc R1B R3b I B v EE S2 Figure 3.26 Input Bias Currents and Test Circuit The input bias currents, I B and I B-, force an additional voltage drop across the added series resistors, R3a and R3b. This additional voltage may be measured (indirectly) using the same technique as applied for measuring the input offset voltage, io, under four separate cases defined by the position of switches S1 and S2: 1. S1 closed and S2 closed. The inferred input voltage is simply io. 2. S1 opened and S2 closed. The inferred input voltage is io - I B *R3a. 3. S1 closed and S2 opened. The inferred input voltage is io I B- *R3b. 4. S1 opened and S2 opened. The inferred input voltage is io - I B *R3a I B- *R3b. The test method for measuring the bias currents is to determine the effective input offset voltage for each case and isolating the separate components, I B, I B- and I io ( = I B - I B- ), arithmetically. Step One: Measure the voltage E3 with both Switch 1 and 2 closed. This measurement is the baseline, or reference value, with no added serial resistance on the input pins. Series resistors R3A and R3B are 3-24

25 Input Current Calculations Baseline ( io ) by-passed. In this example, control amplifier A1 must generate 10.74m in order to null the DUT offset voltage of For future reference, let this voltage be called E0. R k 1 0 R1A 50 S1 R3A 10k DUT R4 100k A1 out 10.74m DC 50 R1B S2 R5 R3B 100k 10k s1 OP Figure AMP 3.27 Input Current Test 0 Step One - DC TEST Baseline CIRCUIT ( E io ) Measurement A1 out R2 1 R1 E io The negative sign in this calculation stems from the polarity of io (non-inverting terminal to the inverting terminal) relative to the voltage divider midpoint voltage (inverting terminal to ground). Step Two: Measure the output voltage of control amplifier A1 with switch S1 open and switch S2 closed. For reference, let this voltage be called E

26 Input Current Calculations I B- R k 1 0 R1A 50 S1 R3A 10k DUT R4 100k A1 out 19.06m DC 50 R1B S2 R3B 10k R5 100k s1 OP AMP 0 Figure 3.27 Input Current Test - Step Two DC TEST CIRCUIT E I B- Measurement Because I B- flows into the inverting input terminal and because of the polarity of the baseline voltage ( io ), the voltage drop across R3a subtracts from the measured input offset voltage, io_s1 : io _ S1 io I B R3A I B io R3A io _ S1 Now io_s1 may be computed similarly as io was computed: A1 out R2 1 R1 E io _ S And finally I B- itself may be computed: E0 E1 R3A ( ) I B 831pA R1 1 10k R2 Step Three: Measure the output voltage of control amplifier A1 with switch S1 closed and switch S2 open. For reference, let this voltage be called E

27 Input Current Calculations I B R k 1 0 R1A 50 S1 R3A 10k DUT R4 100k A1 out 5.403m DC 50 R1B S2 OP AMP R3B 10k R5 100k DC Figure TEST 3.27 CIRCUIT Input Current E Test Step Three I B Measurement - s1 0 Now I B flows into the non-inverting input terminal so that the voltage drop across R3b adds to the measured input offset voltage, io_s2 : io _ S 2 I R3B io B B I io _ S 2 Now io_s2 may be computed in the same as was io_s1 : A1 out R2 1 R1 E R3B io _ S And finally I B itself may be computed: E2 E0 R3B ( ) I B 533pA R1 1 10k R2 io Step Four: Measure the output voltage of control amplifier A1 with both switch S1 open and switch S2 open. For reference, let this voltage be called E

28 Input Current Calculations I io R k 1 0 R1A 50 S1 R3A 10k DUT R4 100k A1 out 13.73m DC Figure 3.27 Input Current Test s1 OP AMP Step Three 0 DC TEST CIRCUIT I B Measurement - E The measured input offset voltage, io_s1_s2 :, must now account for the voltage drop across both R3A and R3B: 50 R1B io _ S1_ S 2 io I B I B I R3B B I B io _ S1_ S 2 R3A R3A Now io_s1_s2 may be computed as before: A1 out R2 1 R1 io _ S1_ S And finally I io = I B - I B- may be computed: E3 E0 io E assuming R3A = R3B R3A ( ) Iio 299 pa R1 1 10k R2 S2 R3B 10k R5 100k By selectively adding series resistors to the DUT input terminals, test circuits have been configured to determine the very small currents actually flowing into each of the op amp s inputs. The values obtained for I B and I B-, along with the induced voltage drops across the 3-28

29 Input Current Calculations Summary and Conclusions additional series resistors are shown in the following figure. Note that the input offset current, I io, although not shown, is -299pA. This negative value simply means that I B < I B- ; in other words, the difference between the input currents causes op amp behavior as if an additional 299pA was flowing into the inverting terminal. S1 v cc R1A R1B 8.31 R3A - R3B I B- 831pA pA I B v EE S2 Integrating Capacitor Test Method Figure 3.26 Input Bias Currents and Test Circuit The input bias currents values were deduced by determining the effective input offset voltage under four separate cases: 1. S1 closed and S2 closed. The inferred input voltage is simply io = S1 opened and S2 closed. The inferred input voltage is pA*10k = S1 closed and S2 opened. The inferred input voltage is pA*10k = S1 opened and S2 opened. The inferred input voltage is pA*10k - 831pA*10k = Step Four, although not technically necessary, provides a valuable check of the validity of the results from previous steps. The integrating capacitor method may be used for the measurement of very low input bias currents. The approach relies on the basic relationship of the current to the rate of change of voltage when a capacitor is charged by a constant current. 3-29

30 Integrating Capacitor Test Method for Determining Input Currents i C * Current is equal to capacitance times the change in voltage over the change in time. t The example circuit uses a data sequencer to close both relays K1 and K2 to establish the initial condition. K2 is then opened for ten seconds and then closed, to generate the ramp for the I B- test. After a delay, K1 is opened for ten seconds and then closed, to generate the ramp for the I B test. During the time the relays are open, current flowing into the series input capacitor generates a ramp, which is amplified by the DUT. Since the value of the capacitor is known, the input current can be calculated by measuring the slope of the ramp. 3-30

31 Integrating Capacitor Test Method (continued) CP1 CP2 DS1 Data Seq R R1B R2 49.5k DUT A out 10.62m DC Figure 3.30 Current Measurement - Capacitance Method Xa: Xb: Yc: Yd: a-b: 923.1m c-d: freq: A 3 b a 0-3 c -6-9 d Ref=Ground X=time(S) Y=voltage Figure 2.3A Slope for I B 3-31

32 Integrating Capacitor Test Method (continued) A Xa: Xb: Yc: Yd: b a a-b: 923.1m c-d: freq: c -6-9 d Ref=Ground X=time(S) Y=voltage Relay K2 is open for ten seconds. The measured slope generated by the I B- current is 5 volts across.973 seconds. The capacitance is 0.1uF, and the circuit gain is Xa: Xb: Yc: Yd: v *0.1uF.953sec 1000Gain a-b: 610.7m c-d: pa freq: A 15.2 b a c d Ref=Ground X=time(S) Y=voltage 393% Relay K1 is open for ten seconds. The measured slope generated by the I B current is 5 volts across.610 seconds. The capacitance is 0.1uF, and the circuit gain is

33 Output Impedance Test Circuit For the output impedance test, the DUT is operated in open loop and forced to a maximum output level by applying a differential DC input voltage. The output voltage is measured twice with two different current loads. The output impedance is determined by calculating the change in voltage drop divided by the change in output (load) current. in -10u -10 POS 15v NO DATA DC R R1B -15v NEG Is1 10mA or 20mA Figure 3.34 Output Impedance Test Circuit Example: 1. With a 10mA current sink applied, the output level of the DUT is volts. With a 20mA current sink applied, the output level is volts. 2. The change in voltage divided by the change in current equals the output impedance. R o I 10mA 20mA 10mA 3-33

34 Chapter Three Op Amp Testing Knowledge Check 1. Design an op amp circuit with the following characteristics: Non-inverting Gain of 0.5 (0.5) Input impedance of 600 ohms (It s OK to use more than one op amp!) 2. Sketch the op amp test circuit for measuring offset voltage. 3. Describe the procedure for measuring PSRR. 4. Calculate the CMRR ratio in db from the following measurements: Common Mode Swing (cm) = 10.0 volts Change in offset voltage (io) = 27.0 u 3-34

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